CY29350 [CYPRESS]
2.5V or 3.3V, 200-MHz, 9-Output Clock Driver; 2.5V或3.3V ， 200 MHz时， 9路输出时钟驱动器
| 型号： | CY29350 |
| 厂家： | 
CYPRESS |
| 描述： | 2.5V or 3.3V, 200-MHz, 9-Output Clock Driver |
| 文件： | 总7页 (文件大小：187K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY29350
2.5V or 3.3V, 200-MHz, 9-Output Clock Driver
Features
Functional Description
• Output frequency range: 25 MHz to 200 MHz
• Input frequency range: 6.25 MHz to 31.25 MHz
• 2.5V or 3.3V operation
The CY29350 is a low-voltage high-performance 200-MHz
PLL-based clock driver designed for high speed clock distri-
bution applications.
The CY29350 features Xtal and LVCMOS reference clock
inputs and provides nine outputs partitioned in four banks of 1,
1, 2, and 5 outputs. Bank A divides the VCO output by 2 or 4
while the other banks divide by 4 or 8 per SEL(A:D) settings,
see . These dividers allow output to input ratios of 16:1, 8:1,
4:1, and 2:1. Each LVCMOS compatible output can drive 50Ω
series or parallel terminated transmission lines. For series
terminated transmission lines, each output can drive one or
two traces giving the device an effective fanout of 1:18.
The PLL is ensured stable given that the VCO is configured to
run between 200 MHz to 500 MHz. This allows a wide range
of output frequencies from 25 MHz to 200 MHz. The internal
VCO is running at multiples of the input reference clock set by
the feedback divider, see Table 1.
• Split 2.5V/3.3V outputs
• ±2.5% max Output duty cycle variation
• Nine Clock outputs: Drive up to 18 clock lines
• Two reference clock inputs: Xtal or LVCMOS
• 150-ps max output-output skew
• Phase-locked loop (PLL) bypass mode
• Spread Aware™
• Output enable/disable
• Pin-compatible with MPC9350
• Industrial temperature range: –40°C to +85°C
• 32-pin 1.0mm TQFP package
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully static
and the minimum input clock frequency specification does not
apply.
Pin Configuration
Block Diagram
SELA
PLL_EN
REF_SEL
TCLK
VCO
Phase
Detector
QA
QB
÷2 / ÷4
XIN
200 -
OSC
XOUT
500MHz
AVDD
FB_SEL
SELA
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
QC0
VDDQC
QC1
VSS
QD0
VDDQD
QD1
VSS
÷4 / ÷8
÷4 / ÷8
LPF
÷16 / ÷32
SELB
CY29350
SELC
SELD
AVSS
XOUT
FB_SEL
SELB
QC0
QC1
SELC
QD0
QD1
÷4 / ÷8
SELD
QD2
QD3
QD4
OE#
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-07474 Rev. *A
Revised July 26, 2004
CY29350
Pin Definitions[1]
Pin
Name
XOUT
XIN
I/O
O
I
Type
Analog
Analog
Description
Oscillator Output. Connect to a crystal.
Oscillator Input. Connect to a crystal.
8
9
30
28
26
22, 24
TCLK
QA
QB
I, PD
O
O
LVCMOS LVCMOS/LVTTL reference clock input
LVCMOS Clock output bank A
LVCMOS Clock output bank B
QC(1:0)
O
LVCMOS Clock output bank C
12, 14, 16, 18, 20 QD(4:0)
O
LVCMOS Clock output bank D
2
10
31
32
3, 4, 5, 6
27
23
15, 19
1
FB_SEL
OE#
I, PD
I, PD
I, PU
I, PD
I, PD
Supply
Supply
Supply
Supply
Supply
LVCMOS Internal Feedback Select Input. See Table 1.
LVCMOS Output enable/disable input. See Table 2.
LVCMOS PLL enable/disable input. See Table 2.
LVCMOS Reference select input. See Table 2.
PLL_EN
REF_SEL
SEL(A:D)
VDDQB
VDDQC
VDDQD
AVDD
LVCMOS Frequency select input, Bank (A:D). See Table 2.
VDD
VDD
VDD
VDD
VDD
2.5V or 3.3V Power supply for bank B output clock[2,3]
2.5V or 3.3V Power supply for bank C output clocks[2,3]
2.5V or 3.3V Power supply for bank D output clocks[2,3]
2.5V or 3.3V Power supply for PLL[2,3]
11
VDD
2.5Vor3.3V Power supply for core, inputs, and bank Aoutput
clock[2,3]
7
AVSS
Supply
Supply
Ground
Ground
Analog ground
Common ground
13, 17, 21, 25, 29 VSS
Table 1. Frequency Table
Input Frequency Range
(AVDD = 3.3V)
Input Frequency Range
(AVDD = 2.5V)
FB_SEL
Feedback Divider
VCO
0
÷32
Input Clock * 32
6.25 MHz to 15.625 MHz
6.25 MHz to 11.875 MHz
1
÷16
Input Clock * 16
12.5 MHz to 31.25 MHz
12.5 MHz to 23.75 MHz
Table 2. Function Table
Control
REF_SEL
PLL_EN
Default
0
Xtal
1
0
1
TCLK
Bypass mode, PLL disabled. The input PLL enabled. The VCO output connects to the
clock connects to the output dividers
Outputs enabled
Feedback divider ÷ 32
÷ 2 (Bank A)
output dividers
Outputs disabled (three-state)
Feedback divider ÷ 16
OE#
FB_SEL
SELA
SELB
SELC
0
0
0
0
0
0
÷ 4 (Bank A )
÷ 4 (Bank B)
÷ 4 (Bank C)
÷ 4 (Bank D)
÷ 8 (Bank B)
÷ 8 (Bank C)
÷ 8 (Bank D)
SELD
Notes:
1. PU = Internal pull-up, PD = Internal pull-down.
2. A 0.1µF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their
high frequency filtering characteristics will be cancelled by the lead inductance of the traces.
3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQB, VDDQC, and VDDQD output power supply
pins.
Document #: 38-07474 Rev. *A
Page 2 of 7
CY29350
Absolute Maximum Conditions
Parameter
VDD
VDD
VIN
VOUT
VTT
Description
DC Supply Voltage
DC Operating Voltage
DC Input Voltage
DC Output Voltage
Output termination Voltage
Latch Up Immunity
Condition
Functional
Relative to VSS
Relative to VSS
Min.
–0.3
2.375
–0.3
–0.3
Max.
5.5
3.465
VDD + 0.3
VDD + 0.3
Unit
V
V
V
V
V
mA
mVp-p
°C
°C
°C
VDD ÷ 2
LU
Functional
200
RPS
TS
TA
TJ
ØJC
ØJA
Power Supply Ripple
Temperature, Storage
Ripple Frequency < 100 kHz
Non-functional
Functional
Functional
Functional
150
–65
–40
+150
+85
+150
42
Temperature, Operating Ambient
Temperature, Junction
Dissipation, Junction to Case
Dissipation, Junction to Ambient
ESD Protection (Human Body Model)
Failure in Time
°C/W
°C/W
Volts
ppm
Functional
105
ESDH
FIT
2000
Manufacturing test
10
Typ.
DC Electrical Specifications (VDD = 2.5V ± 5%, TA = –40°C to +85°C)
Parameter Description Condition
VIL Input Voltage, Low
Min.
–
1.7
–
1.8
–
–
–
–
–
–
Max.
0.7
VDD+0.3
0.6
–
–100
100
10
7
Unit
V
V
V
V
µA
µA
mA
mA
mA
LVCMOS
LVCMOS
IOL = 15mA
IOH = –15mA
VIL = VSS
VIL = VDD
AVDD only
All VDD pins except AVDD
Outputs loaded @ 100 MHz
Outputs loaded @ 200 MHz
–
–
–
–
–
–
5
–
VIH
VOL
VOH
IIL
Input Voltage, High
Output Voltage, Low[4]
Output Voltage, High[4]
Input Current, Low[5]
Input Current, High[5]
PLL Supply Current
IIH
IDDA
IDDQ
IDD
Quiescent Supply Current
Dynamic Supply Current
180
210
4
–
–
–
CIN
ZOUT
Input Pin Capacitance
Output Impedance
–
14
pF
Ω
18
22
DC Electrical Specifications (VDD= 3.3V ± 5%, TA = –40°C to +85°C)
Parameter Description Condition
VIL Input Voltage, Low
Min.
–
2.0
–
Typ.
–
–
–
–
–
–
–
5
Max.
0.8
VDD+0.3
0.55
0.30
–
–100
100
10
7
Unit
V
V
LVCMOS
LVCMOS
VIH
VOL
Input Voltage, High
Output Voltage, Low[4]
IOL = 24 mA
V
IOL = 12 mA
IOH = –24 mA
VIL = VSS
VIL = VDD
–
VOH
IIL
IIH
IDDA
IDDQ
IDD
Output Voltage, High[4]
Input Current, Low[5]
Input Current, High[5]
PLL Supply Current
Quiescent Supply Current
Dynamic Supply Current
2.4
––
–
–
–
–
–
–
12
V
µA
µA
mA
mA
mA
AVDD only
All VDD pins except AVDD
Outputs loaded @ 100 MHz
Outputs loaded @ 200 MHz
–
270
300
4
–
–
–
18
CIN
ZOUT
Notes:
Input Pin Capacitance
Output Impedance
pF
Ω
15
4. Driving one 50Ω parallel terminated transmission line to a termination voltage of V . Alternatively, each output drives up to two 50Ω series terminated
TT
transmission lines.
5. Inputs have pull-up or pull-down resistors that affect the input current.
Document #: 38-07474 Rev. *A
Page 3 of 7
CY29350
AC Electrical Specifications (VDD = 2.5V ± 5%, TA = –40°C to +85°C) [6]
Parameter
fVCO
Description
VCO Frequency
Input Frequency
Condition
Min.
200
12.5
6.25
0
10
25
–
100
50
25
47.5
45
0.1
–
Typ.
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Max.
Unit
MHz
MHz
380
23.75
11.87
200
23.75
75
1.0
190
95
47.5
52.5
55
1.0
150
10
fin
÷16 Feedback
÷32 Feedback
Bypass mode (PLL_EN = 0)
fXTAL
frefDC
tr , tf
Crystal Oscillator Frequency
Input Duty Cycle
TCLK Input Rise/FallTime
Maximum Output Frequency
MHz
%
ns
0.7V to 1.7V
÷2 Output
÷4 Output
÷8 Output
MAX < 100 MHz
MAX > 100 MHz
fMAX
MHz
DC
Output Duty Cycle
f
f
%
tr , tf
tsk(O)
tPLZ, HZ
tPZL, ZH
BW
Output Rise/Fall times
Output-to-Output Skew
Output Disable Time
Output Enable Time
PLL Closed Loop Bandwidth (-3dB) ÷16 Feedback
÷32 Feedback
0.6V to 1.8V
ns
ps
ns
ns
MHz
–
–
–
–
–
10
–
–
0.7 - 0.9
0.6 - 0.8
tJIT(CC)
tJIT(PER)
tLOCK
Cycle-to-Cycle Jitter
Same frequency
Multiple frequencies
Same frequency
–
–
–
–
–
–
–
–
–
150
250
100
175
1
ps
ps
Period Jitter
Multiple frequencies
Maximum PLL Lock Time
–
ms
AC Electrical Specifications (VDD = 3.3V ± 5%, TA = –40°C to +85°C) [6]
Parameter
Description
VCO Frequency
Input Frequency
Condition
Min.
200
12.5
6.25
0
10
25
–
100
50
25
47.5
45
0.1
–
Typ.
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Max.
500
31.25
15.625
200
25
Unit
MHz
MHz
f
f
VCO
÷16 Feedback
÷32 Feedback
Bypass mode (PLL_EN = 0)
in
f
f
Crystal Oscillator Frequency
Input Duty Cycle
TCLK Input Rise/FallTime
Maximum Output Frequency
MHz
%
ns
XTAL
refDC
75
1.0
t , t
0.8V to 2.0V
÷2 Output
÷4 Output
÷8 Output
< 100 MHz
> 100 MHz
0.8V to 2.4V
r
f
f
200
125
62.5
52.5
55
MHz
MAX
DC
t , t
Output Duty Cycle
f
f
%
MAX
MAX
Output Rise/Fall times
Output-to-Output Skew
Bank-to-Bank Skew
Output Disable Time
Output Enable Time
1.0
ns
ps
ps
ns
ns
r
t
f
Banks at same voltage
Banks at different voltages
150
350
10
sk(O)
tsk(B)
–
–
–
t
t
PLZ, HZ
–
10
PZL, ZH
Note:
6. AC characteristics apply for parallel output termination of 50Ω to V . Parameters are guaranteed by characterization and are not 100% tested.
TT
Document #: 38-07474 Rev. *A
Page 4 of 7
CY29350
AC Electrical Specifications (VDD = 3.3V ± 5%, TA = –40°C to +85°C)(continued)[6]
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
BW
PLL Closed Loop Bandwidth
÷16 Feedback
÷32 Feedback
–
–
0.7 – 0.9
0.6 – 0.8
–
–
MHz
(–3dB)
tJIT(CC)
tJIT(PER)
tLOCK
Cycle-to-Cycle Jitter
Period Jitter
Same frequency
Multiple frequencies
Same frequency
Multiple frequencies
–
–
–
–
–
–
–
–
–
150
250
100
150
1
ps
ps
Maximum PLL Lock Time
–
ms
Zo = 50 ohm
Zo = 50 ohm
Pulse
Generator
Z = 50 ohm
RT = 50 ohm
RT = 50 ohm
VTT
VTT
Figure 1. AC Test Reference for VDD = 3.3V / 2.5V
VDD
VDD/2
tP
GND
T0
DC = tP / T0 x 100%
Figure 2. Output Duty Cycle (DC)
VDD
VDD/2
GND
VDD
VDD/2
GND
tSK(O)
Figure 3. Output-to-Output Skew , tsk(O)
Table 3. Suggested Oscillator Crystal Parameters
Characteristic
Frequency Tolerance
Frequency Temperature Stability
Aging
Load Capacitance
Effective Series Resistance
Symbol
TC
TS
TA
CL
RESR
Conditions
Min
–
–
–
–
Typ
–
–
–
20
40
Max
Units
PPM
PPM
PPM/yr
pF
±100
±00
5
–
80
(TA –10 +60C)
First three years @ 25C
Crystal’s rated load
–
Ω
Ordering Information
Part Number
Package Type
Product Flow
CY29350AI
32-pin TQFP
Industrial, –40°C to +85°C
CY29350AIT
32-pin TQFP – Tape and Reel
Industrial, –40°C to 85°C
Document #: 38-07474 Rev. *A
Page 5 of 7
CY29350
Package Drawing and Dimension
32-Lead Thin Plastic Quad Flatpack 7 x 7 x 1.0 mm A32
51-85063-*B
Spread Aware is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the
trademarks of their respective holders.
Document #: 38-07474 Rev. *A
Page 6 of 7
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY29350
Document History Page
Document Title:CY29350 2.5V or 3.3V, 200-MHz, 9-Output Clock Driver
Document Number: 38-07474
Orig. of
Rev.
ECN No. Issue Date
Description of Change
Change
RGL
**
*A
128104
245393
07/07/03
See ECN
New Data Sheet
Re-worded Select Function Descriptions in table 2.
RGL
Document #: 38-07474 Rev. *A
Page 7 of 7
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