CY29350AXIT [CYPRESS]
2.5 V or 3.3 V, 200-MHz, 9-Output Clock Driver Nine Clock outputs: Drive up to 18 clock lines; 2.5 V或3.3 V ， 200 - MHz时， 9路输出时钟驱动器九时钟输出：驱动多达18时钟线
| 型号： | CY29350AXIT |
| 厂家： | 
CYPRESS |
| 描述： | 2.5 V or 3.3 V, 200-MHz, 9-Output Clock Driver Nine Clock outputs: Drive up to 18 clock lines |
| 文件： | 总13页 (文件大小：431K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY29350
2.5 V or 3.3 V, 200-MHz,
9-Output Clock Driver
2.5
V or 3.3 V, 200-MHz, 9-Output Clock Driver
Features
Functional Description
■ Output frequency range: 25 MHz to 200 MHz
■ Input frequency range: 6.25 MHz to 31.25 MHz
■ 2.5 V or 3.3 V operation
The CY29350 is a low-voltage high-performance 200-MHz
PLL-based clock driver designed for high speed clock
distribution applications.
The CY29350 features Xtal and LVCMOS reference clock inputs
and provides nine outputs partitioned in four banks of 1, 1, 2, and
5 outputs. Bank A divides the VCO output by 2 or 4 while the
other banks divide by 4 or 8 per SEL(A:D) settings, see . These
dividers allow output to input ratios of 16:1, 8:1, 4:1, and 2:1.
Each LVCMOS compatible output can drive 50 series or
parallel terminated transmission lines. For series terminated
transmission lines, each output can drive one or two traces giving
the device an effective fanout of 1:18.
■ Split 2.5 V/3.3 V outputs
■ ±2.5% max Output duty cycle variation
■ Nine Clock outputs: Drive up to 18 clock lines
■ Two reference clock inputs: Xtal or LVCMOS
■ 150-ps max output-output skew
■ Phase-locked loop (PLL) bypass mode
■ Spread Aware™
The PLL is ensured stable given that the VCO is configured to
run between 200 MHz to 500 MHz. This allows a wide range of
output frequencies from 25 MHz to 200 MHz. The internal VCO
is running at multiples of the input reference clock set by the
feedback divider, see Table 1.
■ Output enable/disable
■ Pin-compatible with MPC9350
When PLL_EN is LOW, PLL is bypassed and the reference clock
directly feeds the output dividers. This mode is fully static and the
minimum input clock frequency specification does not apply.
■ Industrial temperature range: –40 °C to +85 °C
■ 32-pin 1.0 mm TQFP package
Block Diagram
SELA
PLL_EN
REF_SEL
TCLK
VCO
200 -
500MHz
Phase
Detector
QA
QB
XIN
OSC
XOUT
LPF
FB_SEL
SELB
QC0
QC1
SELC
QD0
QD1
SELD
OE#
QD2
QD3
QD4
Cypress Semiconductor Corporation
Document Number: 38-07474 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 12, 2011
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CY29350
Contents
Pin Configuration .............................................................3
Pin Definitions ..................................................................4
Absolute Maximum Conditions .......................................5
DC Electrical Specifications ............................................6
DC Electrical Specifications ............................................6
AC Electrical Specifications ............................................7
AC Electrical Specifications ............................................8
Ordering Information ......................................................10
Ordering Code Definitions .........................................10
Package Drawing and Dimension .................................10
Acronyms ........................................................................11
Document Conventions .................................................11
Units of Measure .......................................................11
Document History Page .................................................12
Sales, Solutions, and Legal Information ......................13
Worldwide Sales and Design Support .......................13
Products ....................................................................13
PSoC Solutions .........................................................13
Document Number: 38-07474 Rev. *C
Page 2 of 13
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CY29350
Pin Configuration
AVDD
FB_SEL
SELA
SELB
SELC
SELD
AVSS
XOUT
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
QC0
VDDQC
QC1
VSS
QD0
VDDQD
QD1
VSS
CY29350
Document Number: 38-07474 Rev. *C
Page 3 of 13
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CY29350
Pin Definitions[1]
Pin
Name
XOUT
XIN
I/O
O
Type
Description
Oscillator Output. Connect to a crystal.
Oscillator Input. Connect to a crystal.
8
Analog
Analog
9
I
30
28
26
22, 24
TCLK
QA
I, PD
O
LVCMOS LVCMOS/LVTTL reference clock input
LVCMOS Clock output bank A
QB
O
LVCMOS Clock output bank B
QC(1:0)
O
LVCMOS Clock output bank C
12, 14, 16, 18, 20 QD(4:0)
O
LVCMOS Clock output bank D
2
FB_SEL
OE#
I, PD
I, PD
I, PU
I, PD
I, PD
Supply
Supply
Supply
Supply
Supply
LVCMOS Internal Feedback Select Input. See Table 1.
LVCMOS Output enable/disable input. See Table 2.
LVCMOS PLL enable/disable input. See Table 2.
LVCMOS Reference select input. See Table 2.
LVCMOS Frequency select input, Bank (A:D). See Table 2.
10
31
PLL_EN
REF_SEL
SEL(A:D)
VDDQB
VDDQC
VDDQD
AVDD
32
3, 4, 5, 6
27
VDD
VDD
VDD
VDD
VDD
2.5 V or 3.3 V Power supply for bank B output clock[2, 3]
23
2.5 V or 3.3 V Power supply for bank C output clocks[2, 3]
2.5 V or 3.3 V Power supply for bank D output clocks[2, 3]
2.5 V or 3.3 V Power supply for PLL[2, 3]
15, 19
1
11
VDD
2.5 V or 3.3 V Power supply for core, inputs, and bank A
output clock[2, 3]
7
AVSS
Supply
Supply
Ground
Ground
Analog ground
13, 17, 21, 25, 29 VSS
Common ground
Table 1. Frequency Table
Input Frequency Range
(AVDD = 3.3 V)
Input Frequency Range
(AVDD = 2.5 V)
FB_SEL
Feedback Divider
VCO
0
1
32
16
Input Clock * 32
Input Clock * 16
6.25 MHz to 15.625 MHz
12.5 MHz to 31.25 MHz
6.25 MHz to 11.875 MHz
12.5 MHz to 23.75 MHz
Table 2. Function Table
Control
REF_SEL
PLL_EN
Default
0
1
0
Xtal
TCLK
1
Bypass mode, PLL disabled. The input PLL enabled. The VCO output connects to the
clock connects to the output dividers
Outputs enabled
Feedback divider 32
2 (Bank A)
output dividers
OE#
FB_SEL
SELA
0
0
0
0
0
0
Outputs disabled (three-state)
Feedback divider 16
4 (Bank A )
SELB
4 (Bank B)
8 (Bank B)
8 (Bank C)
8 (Bank D)
SELC
SELD
4 (Bank C)
4 (Bank D)
Notes
1. PU = Internal pull-up, PD = Internal pull-down.
2. A 0.1F bypass capacitor should be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins their high
frequency filtering characteristics will be cancelled by the lead inductance of the traces.
3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQB, VDDQC, and VDDQD output power supply pins.
Document Number: 38-07474 Rev. *C
Page 4 of 13
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CY29350
Absolute Maximum Conditions
Parameter
VDD
VDD
VIN
Description
DC Supply Voltage
Condition
Functional
Min
–0.3
2.375
–0.3
–0.3
–
Max
5.5
Unit
V
DC Operating Voltage
3.465
VDD + 0.3
VDD + 0.3
VDD 2
–
V
DC Input Voltage
Relative to VSS
Relative to VSS
V
VOUT
VTT
DC Output Voltage
V
Output termination Voltage
Latch Up Immunity
V
LU
Functional
200
–
mA
mVp-p
°C
RPS
TS
Power Supply Ripple
Ripple Frequency < 100 kHz
Non-functional
Functional
150
Temperature, Storage
–65
–40
–
+150
+85
TA
Temperature, Operating Ambient
Temperature, Junction
Dissipation, Junction to Case
Dissipation, Junction to Ambient
ESD Protection (Human Body Model)
Failure in Time
°C
TJ
Functional
+150
42
°C
ØJC
ØJA
Functional
–
°C/W
°C/W
Volts
ppm
Functional
–
105
ESDH
FIT
2000
–
Manufacturing test
10
Document Number: 38-07474 Rev. *C
Page 5 of 13
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CY29350
DC Electrical Specifications
(VDD = 2.5 V ± 5%, TA = –40 °C to +85 °C)
Parameter
VIL
Description
Input Voltage, Low
Condition
Min
–
Typ
–
Max
Unit
V
LVCMOS
LVCMOS
0.7
VIH
VOL
VOH
IIL
Input Voltage, High
1.7
–
–
VDD + 0.3
V
Output Voltage, Low[4]
Output Voltage, High[4]
Input Current, Low[5]
Input Current, High[5]
PLL Supply Current
IOL = 15mA
–
0.6
–
V
IOH = –15mA
1.8
–
–
V
VIL = VSS
–
–100
100
10
7
A
A
mA
mA
mA
IIH
VIL = VDD
–
–
IDDA
IDDQ
IDD
AVDD only
–
5
Quiescent Supply Current
Dynamic Supply Current
All VDD pins except AVDD
Outputs loaded @ 100 MHz
Outputs loaded @ 200 MHz
–
–
–
180
210
4
–
–
–
CIN
Input Pin Capacitance
Output Impedance
–
–
pF
ZOUT
14
18
22
DC Electrical Specifications
(VDD = 3.3 V ± 5%, TA = –40 °C to +85 °C)
Parameter
VIL
Description
Input Voltage, Low
Condition
LVCMOS
Min
–
Typ
–
Max
Unit
V
0.8
VIH
Input Voltage, High
Output Voltage, Low[4]
LVCMOS
2.0
–
–
VDD + 0.3
V
VOL
IOL = 24 mA
–
0.55
0.30
–
V
IOL = 12 mA
–
–
VOH
IIL
Output Voltage, High[4]
Input Current, Low[5]
Input Current, High[5]
PLL Supply Current
IOH = –24 mA
2.4
––
–
–
V
VIL = VSS
–
–100
100
10
7
A
A
mA
mA
mA
IIH
VIL = VDD
–
IDDA
IDDQ
IDD
AVDD only
–
5
Quiescent Supply Current
Dynamic Supply Current
All VDD pins except AVDD
Outputs loaded @ 100 MHz
Outputs loaded @ 200 MHz
–
–
–
270
300
4
–
–
–
CIN
Input Pin Capacitance
Output Impedance
–
–
pF
ZOUT
12
15
18
Notes
4. Driving one 50 parallel terminated transmission line to a termination voltage of V . Alternatively, each output drives up to two 50 series terminated transmission
TT
lines.
5. Inputs have pull-up or pull-down resistors that affect the input current.
Document Number: 38-07474 Rev. *C
Page 6 of 13
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CY29350
AC Electrical Specifications
(VDD = 2.5 V ± 5%, TA = –40 °C to +85 °C) [6]
Parameter
fVCO
Description
VCO Frequency
Condition
16 Feedback
Min
200
12.5
6.25
0
Typ
Max
380
23.75
11.87
200
23.75
75
Unit
MHz
MHz
–
fin
Input Frequency
–
32 Feedback
–
Bypass mode (PLL_EN = 0)
–
fXTAL
frefDC
tr , tf
Crystal Oscillator Frequency
Input Duty Cycle
10
25
–
–
MHz
%
–
TCLK Input Rise/FallTime
Maximum Output Frequency
0.7 V to 1.7 V
2 Output
4 Output
8 Output
–
1.0
ns
fMAX
100
50
25
47.5
45
0.1
–
–
190
95
MHz
–
–
47.5
52.5
55
DC
Output Duty Cycle
f
f
MAX < 100 MHz
MAX > 100 MHz
–
%
–
tr, tf
Output Rise/Fall times
Output-to-Output Skew
Output Disable Time
Output Enable Time
0.6V to 1.8V
–
1.0
ns
ps
tsk(O)
tPLZ, HZ
tPZL, ZH
BW
–
150
10
–
–
ns
–
–
10
ns
PLL Closed Loop Bandwidth (–3 dB) 16 Feedback
32 Feedback
–
0.7–0.9
–
MHz
–
0.6–0.8
–
tJIT(CC)
tJIT(PER)
tLOCK
Cycle-to-Cycle Jitter
Same frequency
–
–
–
–
–
–
150
250
100
175
1
ps
ps
Multiple frequencies
Same frequency
–
Period Jitter
–
Multiple frequencies
–
Maximum PLL Lock Time
–
ms
Note
6. AC characteristics apply for parallel output termination of 50 to V . Parameters are guaranteed by characterization and are not 100% tested.
TT
Document Number: 38-07474 Rev. *C
Page 7 of 13
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CY29350
AC Electrical Specifications
(VDD = 3.3 V ± 5%, TA = –40 °C to +85 °C) [7]
Parameter
Description
VCO Frequency
Condition
16 Feedback
Min
200
12.5
6.25
0
Typ
Max
500
31.25
15.625
200
25
Unit
MHz
MHz
f
f
–
VCO
Input Frequency
–
in
32 Feedback
–
Bypass mode (PLL_EN = 0)
–
f
f
Crystal Oscillator Frequency
Input Duty Cycle
10
25
–
–
MHz
%
XTAL
–
75
refDC
t , t
TCLK Input Rise/FallTime
Maximum Output Frequency
0.8 V to 2.0 V
2 Output
4 Output
8 Output
–
1.0
ns
r
f
f
100
50
25
47.5
45
0.1
–
–
200
125
62.5
52.5
55
MHz
MAX
–
–
DC
Output Duty Cycle
f
f
< 100 MHz
> 100 MHz
–
%
MAX
MAX
–
t , t
Output Rise/Fall times
Output-to-Output Skew
Bank-to-Bank Skew
Output Disable Time
Output Enable Time
0.8 V to 2.4 V
–
1.0
ns
ps
r
f
t
Banks at same voltage
Banks at different voltages
–
150
350
10
sk(O)
tsk(B)
–
–
ps
t
t
–
–
ns
PLZ, HZ
PZL, ZH
–
–
10
ns
BW
PLL Closed Loop Bandwidth (–3 dB) 16 Feedback
32 Feedback
–
0.7–0.9
–
MHz
–
0.6–0.8
–
tJIT(CC)
tJIT(PER)
tLOCK
Cycle-to-Cycle Jitter
Same frequency
–
–
–
–
–
–
150
250
100
150
1
ps
ps
Multiple frequencies
Same frequency
–
Period Jitter
–
Multiple frequencies
–
Maximum PLL Lock Time
–
ms
Note
7. AC characteristics apply for parallel output termination of 50 to V . Parameters are guaranteed by characterization and are not 100% tested.
TT
Document Number: 38-07474 Rev. *C
Page 8 of 13
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CY29350
Figure 1. AC Test Reference for VDD = 3.3 V / 2.5 V
Zo = 50 ohm
Zo = 50 ohm
Pulse
Generator
Z = 50 ohm
RT = 50 ohm
RT = 50 ohm
VTT
VTT
Figure 2. Output Duty Cycle (DC)
VDD
VDD/2
GND
tP
T0
DC = tP / T0 x 100%
Figure 3. Output-to-Output Skew , tsk(O)
VDD
VDD/2
GND
VDD
VDD/2
GND
tSK(O)
Table 3. Suggested Oscillator Crystal Parameters
Characteristic
Frequency Tolerance
Frequency Temperature Stability
Aging
Symbol
TC
Conditions
Min
Typ
–
Max
±100
±00
5
Units
ppm
ppm
ppm/yr
pF
–
–
–
–
–
TS
(TA –10 +60 °C)
First three years @ 25 °C
Crystal’s rated load
–
TA
–
Load Capacitance
CL
20
40
–
Effective Series Resistance
RESR
80
Document Number: 38-07474 Rev. *C
Page 9 of 13
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CY29350
Ordering Information
Part Number
Package Type
Product Flow
CY29350AXI
32-pin TQFP, Pb-free
Industrial, –40 °C to +85 °C
Industrial, –40 °C to 85 °C
CY29350AXIT
32-pin TQFP – Tape and Reel, Pb-free
Ordering Code Definitions
CY 29350 AX
X
T
T = Tape and Reel
Temperature Range: X = C or I
C = Commercial; I = Industrial
Package Type:
AX = 32-pin TQFP
Base Device Part Number
Company ID: CY = Cypress
Package Drawing and Dimension
Figure 4. 32-pin TQFP 7 x 7 x 1.0 mm A3210
51-85063 *C
Document Number: 38-07474 Rev. *C
Page 10 of 13
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CY29350
Acronyms
Acronym
CMOS
ESD
Description
complementary metal oxide semiconductor
electrostatic discharge
I/O
Input/Output
LVCMOS
Low Voltage Complementary Metal Oxide
Semiconductor
LVTTL
PLL
Low Voltage Transistor-Transistor Logic
phase-locked loop
TQFP
VCO
thin quad flat pack
voltage-controlled oscillator
Document Conventions
Units of Measure
Symbol
°C
Unit of Measure
degree Celsius
Hertz
Hz
kHz
MHz
µF
µA
mm
mA
ms
ns
kilo Hertz
Mega Hertz
micro Farads
micro Amperes
milli meter
milli Amperes
milli seconds
nano seconds
ohms
%
percent
pF
ppm
ps
pico Farads
parts per million
pico seconds
kilo Volts
kV
mV
V
milli Volts
Volts
W
Watts
Document Number: 38-07474 Rev. *C
Page 11 of 13
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CY29350
Document History Page
Document Title:CY29350 2.5 V or 3.3 V, 200-MHz, 9-Output Clock Driver
Document Number: 38-07474
Orig. of
Change
Rev.
ECN No. Issue Date
Description of Change
**
128104
245393
07/07/03
See ECN
RGL
New Data Sheet
Re-worded Select Function Descriptions in table 2.
*A
RGL
The existing part numbers are replaced with new ones: CY29350AXI and
CY29350AXIT with package type cells: [32-pin TQFP, Pb-free] [32-pin
TQFP – Tape and Reel, Pb-free].
*B
*C
2904632 04/05/2010
3223621 04/12/2011
KVM
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Updated in new template.
BASH
Document Number: 38-07474 Rev. *C
Page 12 of 13
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CY29350
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
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© Cypress Semiconductor Corporation, 2003-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-07474 Rev. *C
Revised April 12, 2011
Page 13 of 13
Spread Aware is a trademark of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders.
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相关型号：
CY29350_11
2.5 V or 3.3 V, 200-MHz, 9-Output Clock Driver Nine Clock outputs: Drive up to 18 clock lines
CYPRESS
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