CY26049ZXC-22T [CYPRESS]
FailSafe⑩ PacketClock⑩ Global Communications Clock Generator; FailSafe⑩ PacketClock⑩全球通信时钟发生器
| 型号： | CY26049ZXC-22T |
| 厂家： | 
CYPRESS |
| 描述： | FailSafe⑩ PacketClock⑩ Global Communications Clock Generator |
| 文件： | 总6页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY26049-22
FailSafe™ PacketClock™
Global Communications Clock Generator
Benefits
Features
• Fully integrated phase-locked loop (PLL)
• FailSafe output
• Integrated high-performance PLL tailored for telecommuni-
cationsfrequencysynthesiseliminatestheneedforexternal
loop filter components
• PLL driven by a crystal oscillator that is phase aligned
• When reference is off, DCXO maintains clock outputs and
with external reference
SAFE pin indicates FailSafe conditions
• 100-MHz output from 10-MHz input
• Low-jitter, high-accuracy outputs
• 3.3V ± 5% operation
• DCXO maintains continuous operation should the input
reference clock fail
• Glitch-free transition simplifies system design
• Works with commonly available, low-cost 10-MHz crystal
• Zero-ppm error for all output frequencies
• 16-lead TSSOP
• Compatible across industry standard design platforms
• Industry standard package with 6.4 × 5.0 mm2 footprint and
a height profile of just 1.1 mm
Logic Block Diagram
external pullable crystal
(10M Hz)
XOUT
XIN
input reference
(10M Hz)
PHASE
FAILSAFETM
CONTROL
ICLK
CLKA
DIGITAL
LOCKED
100M Hz
CONTROLLED
CRYSTAL
OUTPUT
DIVIDER
LOOP
OSCILLATOR
SAFE
ICLK detected
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-07730 Rev. **
Revised January 12, 2005
CY26049-22
Pin Configuration
16-pin TSSOP
Top View
ICLK
NC
1
2
3
4
5
6
7
8
16 NC
15
CLKA
NC
14 NC
NC
VDD
VSS
NC
13 NC
12 VDD
11 VSS
10 SAFE
XIN
9 XOUT
Pin Description
Pin Number Pin Name
Pin Description
1
2
ICLK
NC
Reference Input Clock; 10 MHz.
No Connect.
3
NC
No Connect.
4
NC
No Connect.
5
6
7
VDD
VSS
NC
Voltage Supply; 3.3V.
Ground.
No Connect
8
XIN
Pullable Crystal Input; 10 MHz.
9
XOUT Pullable Crystal Output; 10 MHz.
10
11
12
13
14
15
16
SAFE
VSS
VDD
NC
NC
CLKA
NC
High = reference ICLK within range, Low = reference ICLK out of range.
Ground.
Voltage Supply; 3.3V.
No Connect.
No Connect.
Clock Output. 100 MHz
No Connect.
Selector Guide
Part Number
Input Frequency Range
Outputs
Output Frequencies
CY26049ZXC-22 Reference Input Clock: 10 MHz
1
100 MHz
Crystal: 10-MHz pullable Crystal per Cypress Specification
In the event of a reference clock failure the DCXO maintains
the last frequency of the reference clock. The unique feature
of the CY26049-22 is that the DCXO is, in fact, the primary
clocking source. When the reference clock is restored, the
DCXO automatically resynchronizes to the reference. The
status of the reference clock input, as detected by the
CY26049-22, is reported by the SAFE pin.
Description
CY26049-22 is a FailSafe frequency synthesizer with a
reference clock input and 100-MHz output. The device
provides an optimum solution for applications where
continuous operation is required in the event of a primary clock
failure. The continuous, glitch-free operation is achieved by
using a DCXO, which serves as a primary clock source. The
FailSafe control circuit synchronizes the DCXO oscillator with
the reference as long as the reference is within the pull range
of the crystal.
Document #: 38-07730 Rev. **
Page 2 of 6
CY26049-22
Data Retention @ Tj = 125°C................................ >10 Years
Package Power Dissipation...................................... 350 mW
ESD (Human Body Model) MIL-STD-883.................... 2000V
Absolute Maximum Conditions
Supply Voltage (VDD)........................................–0.5 to +7.0V
DC Input Voltage...................................... –0.5V to VDD + 0.5
Storage Temperature (Non-Condensing)....–55°C to +125°C
Junction Temperature ................................ –40°C to +125°C
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Recommended Pullable Crystal Specifications
Parameter
Name
Comments
Min.
Typ.
Max. Unit
FNOM
Nominal crystal frequency
Parallelresonance,fundamentalmode,
–
10
–
MHz
AT cut
CLNOM
R1
R3/R1
Nominal load capacitance
Equivalent series resistance (ESR)
–
–
3
14
–
–
–
25
–
pF
Ω
Fundamental mode
Ratio of third overtone mode ESR to
Ratio used because typical R1 values
fundamental mode ESR
are much less than the maximum spec
DL
Crystal drive level
No external series resistor assumed
–
400
–
0.5
–
–
2
–
mW
ppm
F3SEPLI
F3SEPLO
C0
Third overtone separation from 3*FNOM High side
Third overtone separation from 3*FNOM Low side
Crystal shunt capacitance
–200 ppm
7
–
–
pF
C0/C1
C1
Ratio of shunt to motional capacitance
Crystal motional capacitance
180
14.4
–
18
250
21.6
fF
Recommended Operating Conditions
Parameter
Description
Min.
3.15
0
–
0.05
Typ.
3.3
–
–
Max.
3.45
70
15
Unit
V
°C
pF
ms
VDD
TAC
CLOAD
tpu
Operating Voltage
Ambient Temperature (Commercial Temperature)
Max Output Load Capacitance
Power-up time for all VDDs to reach minimum specified
–
500
voltage (power ramps must be monotonic)
DC Electrical Specifications (Commercial Temp: 0°to 70°C)
Parameter
IOH
IOL
VIH
VIL
IIH
IIL
CIN
IDD
Description
Output High Current
Output Low Current
Input High Voltage
Input High Voltage
Input High Current
Input Low Current
Input Capacitance
Supply Current
Test Conditions
VOH = VDD – 0.5, VDD = 3.3V (source)
VOL = 0.5, VDD = 3.3V (sink)
CMOS Levels
CMOS Levels
VIH=VDD
Min.
Typ.
24
24
–
–
5
5
–
–
Max.
–
–
Unit
mA
mA
VDD
VDD
µA
µA
pF
mA
12
12
0.7
–
–
–
–
0.3
10
10
7
VIL=0V
–
–
CLOAD = 15 pF, VDD = 3.45V
45
AC Electrical Specifications (Commercial Temp: 0° to 70°C)
Parameter
fICLK-E
LR
Description
Frequency, Input Clock
FailSafe Lock Range[1]
Test Conditions
Input Clock Frequency, External Mode
Range of reference ICLK for Safe = High
Min. Typ. Max. Unit
–
10
–
MHz
–250
–
+250 ppm
DC = t2/t1 Output Duty Cycle
Duty Cycle defined in Figure 1, measured at 50% of VDD 45
50
–
–
55
250
50
%
ps
ps
TPJIT1
Clock Jitter
Period Jitter, Peak to Peak, 10,000 periods
RMS Period Jitter
–
–
Note:
1. Dependent on crystals chosen and crystal specs.
Document #: 38-07730 Rev. **
Page 3 of 6
CY26049-22
AC Electrical Specifications (Commercial Temp: 0° to 70°C) (continued)
Parameter
t6
tfs_lock
Description
PLL Lock Time
FailSafe Lock Time
Test Conditions
Time for PLL to lock within ± 150 ppm of target frequency
Min. Typ. Max. Unit
–
–
3
ms
Time for PLL to lock to ICLK (outputs phase aligned with
–
–
7
s
ICLK and Safe = High)
ferror
ER
Frequency Synthesis Error Actual mean frequency error vs. target
–
0
1.4
–
2
ppm
V/ns
Rising Edge Rate
Output Clock Edge Rate, Measured from 20% to 80% of 0.8
V
DD, CLOAD = 15 pF. See Figure 2.
EF
Falling Edge Rate
Output Clock Edge Rate, Measured from 20% to 80% of 0.8
1.4
2
V/ns
VDD, CLOAD = 15 pF. See Figure 2.
Voltage and Timing Definitions
t1
t2
CLK
50%
50%
Figure 1. Duty Cycle Definition; DC = t2/t1
t4
t3
80%
20%
CLK
Figure 2. Rise and Fall Time Definitions: ER = 0.6 x VDD / t3, EF = 0.6 x VDD / t4
Test Circuit
ICLK
1
2
3
4
5
6
7
8
16
15
14
13
12
11
CLKA
CLOAD
VDD
0.1uF
VDD
0.1uF
10
9
10MHz
Ordering Information
Ordering Code
Package Type
Operating Temperature Range
Lead-Free
CY26049ZXC-22
CY26049ZXC-22T
16-lead TSSOP
16-lead TSSOP—Tape and Reel
Commercial 0° to 70°C
Commercial 0° to 70°C
Document #: 38-07730 Rev. **
Page 4 of 6
CY26049-22
Package Drawing and Dimensions
16-lead TSSOP 4.40 MM Body Z16.173
PIN 1 ID
DIMENSIONS IN MM[INCHES] MIN.
1
MAX.
REFERENCE JEDEC MO-153
PACKAGE WEIGHT 0.05gms
6.25[0.246]
6.50[0.256]
4.30[0.169]
4.50[0.177]
16
0.65[0.025]
BSC.
0.25[0.010]
BSC
0.19[0.007]
0.30[0.012]
1.10[0.043] MAX.
GAUGE
PLANE
0°-8°
0.076[0.003]
0.50[0.020]
0.70[0.027]
0.05[0.002]
0.15[0.006]
0.85[0.033]
0.95[0.037]
0.09[[0.003]
0.20[0.008]
SEATING
PLANE
4.90[0.193]
5.10[0.200]
51-85091-*A
FailSafe and PacketClock are trademarks of Cypress Semiconductor. Corporation. All product and company names mentioned
in this document are the trademarks of their respective holders.
Document #: 38-07730 Rev. **
Page 5 of 6
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY26049-22
Document History Page
Document Title: CY26049-22 FailSafe™ PacketClock™ Global Communications Clock Generator
Document Number: 38-07730
Orig. of
REV.
ECN No. Issue Date Change
Description of Change
**
308456
See ECN
RGL
New Data Sheet
Document #: 38-07730 Rev. **
Page 6 of 6
相关型号：
CY26049ZXC-36
Clock Generator, 155.52MHz, CMOS, PDSO16, 4.40 MM, LEAD FREE, MO-153, TSSOP-16
CYPRESS
CY26049ZXI-36
Clock Generator, 155.52MHz, CMOS, PDSO16, 4.40 MM, LEAD FREE, MO-153, TSSOP-16
CYPRESS
CY26049ZXI-36T
Clock Generator, 155.52MHz, CMOS, PDSO16, 4.40 MM, LEAD FREE, MO-153, TSSOP-16
CYPRESS
©2020 ICPDF网 联系我们和版权申明