CY26111 [ETC]
Clocks and Buffers ; 时钟和缓冲器\n
| 型号： | CY26111 |
| 厂家： | 
ETC |
| 描述： | Clocks and Buffers
|
| 文件： | 总5页 (文件大小：53K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY26111
One-PLL General Purpose
Clock Generator
Features
• Integrated phase-locked loop
• Low skew, low jitter, high-accuracy outputs
• 3.3V Operation with 2.5V Output Option
• 16-TSSOP
Benefits
Internal PLL with up to 333 MHz internal operation
Meets critical timing requirements in complex system designs
Enables application compatibility
Industry standard package saves on board space
Part Number Outputs
CY26111
Input Frequency
Output Frequency Range
4
25 MHz
3 x 25 MHz, 1 x 125 MHz
Logic Block Diagram
Pin Configurations
XIN
CY26111
16-pin TSSOP
Q
OSC.
Φ
LCLK1 25 MHz
XOUT
VCO
OUTPUT
LCLK2 25 MHz
P
MULTIPLEXER
AND
DIVIDERS
XOUT
1
2
3
4
5
6
16
15
14
13
12
XIN
VDD
AVDD
OE
LCLK3 25 MHz
CLK4 125 MHz
PLL
CLK4
NC
VSS
AVSS
VSSL
N/C
11
10
VDDL
7
8
NC
LCLK1
LCLK2
9
LCLK3
OE
VDDL
VSS
VSSL
VDD
AVDD AVSS
Output
Pin
7
Default Frequency
Unit
MHz
MHz
MHz
MHz
LCLK1
LCLK2
LCLK3
CLK4
25
25
8
9
25
15
125
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-07095 Rev. *A
Revised December 14, 2002
CY26111
Summary
Name
XIN
Pin Number
Description
1
Reference Input
VDD
2
Voltage Supply
AVDD
OE
3
Analog Voltage Supply
Output Enable, OE = 0 three-state; OE = 1 active
Analog Ground
4
AVSS
VSSL
LCLK 1
LCLK 2
LCLK 3
NC
5
6
LCLK Ground
7
Clock output 1–25 MHz at VDDL level
Clock output 2–25 MHz at VDDL level
Clock output 3–25 MHz at VDDL level
No Connect - Reserved
LCLK Voltage Supply (2.5V or 3.3V)
No Connect - Reserved
Ground
8
9
10
11
12
13
14
15
16
VDDL
NC
VSS
NC
No Connect - Reserved
Clock output 4 - 125 MHz
Reference Output
CLK 4
XOUT[1]
Absolute Maximum Conditions
Parameter
VDD
Description
Min.
Max.
7.0
Unit
V
Supply Voltage
I/O Supply Voltage
–0.5
VDDL
7.0
V
TJ
Junction Temperature
Digital Inputs
125
°C
V
AVSS – 0.3V
VSS – 0.3V
VSS – 0.3V
2
AVDD + 0.3V
VDD + 0.3V
VDDL +0.3V
Digital Outputs referred to VDD
Digital Outputs referred to VDDL
Electro-Static Discharge
V
V
kV
Recommended Operating Conditions
Parameter
VDD
Description
Operating Voltage
Min.
Typ.
3.3
Max.
3.6
Unit
V
3.0
2.375
0
VDDL
TA
Operating Voltage
2.5
2.625
70
V
Ambient Temperature
Max. Load Capacitance
Driven Reference Frequency
°C
CLOAD
fREF
15
pF
25
MHz
Power-up time for all VDD's to
reach minimum specified voltage
(power ramps must be
monotonic)
tPU
0.05
500
ms
Note:
1. Float XOUT if XIN is externally driven.
Document #: 38-07095 Rev. *A
Page 2 of 5
CY26111
DC Electrical Characteristics
Parame-
ter[1]
IOH
Name
Description
VOH = VDD – 0.5, VDD/VDDL = 3.3V
VOL = 0.5, VDD/VDDL = 3.3V
VOH = VDDL – 0.5, VDDL = 2.5V
VOL = 0.5, VDDL = 2.5V
Min.
12
12
8
Typ.
24
Max.
Unit
mA
mA
mA
mA
VDD
VDD
pF
Output High Current
Output Low Current
Output High Current
Output Low Current
Input High Voltage
Input Low Voltage
Input Capacitance
IOL
24
IOH
16
IOL
8
16
VIH
CMOS levels, 70% of VDD
CMOS levels, 30% of VDD
OE Pin
0.7
VIL
0.3
7
CIN
IIZ
Input Leakage Current OE Pin
5
µA
IVDD
IVDDL
IVDDL
Supply Current
Supply Current
Supply Current
AVDD/VDD Current
30
10
8
mA
mA
mA
VDDL Current (VDDL=3.6V)
VDDL Current (VDDL = 2.625V)
AC Electrical Characteristics
Parameter[1]
Name
Description
Min.
Typ.
Max.
Unit
DC
Duty Cycle is defined in Figure 1; t1/t2, 50% of
VDD
40
50
60
%
t3
t3
t4
t4
Rising Edge Slew Rate Output Clock Rise Time, 20% – 80% of
0.8
0.6
0.8
0.6
1.4
1.2
1.4
1.2
V/ns
V/ns
V/ns
V/ns
VDD/VDDL = 3.3V
Rising Edge Slew Rate Output Clock Rise Time, 20% – 80% of
VDDL = 2.5V
Falling Edge Slew
Rate
Output Clock Fall Time, 80% – 20% of
VDD/VDDL = 3.3V
Falling Edge Slew
Rate
Output Clock Fall Time, 80% – 20% of
VDDL = 2.5V
t5
t9
Skew
Delay between related outputs at rising edge
Peak to Peak period jitter
200
250
3
ps
ps
Clock Jitter
PLL Lock Time
t10
ms
Note:
2. Not 100% tested.
t1
t2
50%
50%
CLK
CLK
Figure 1. Duty Cycle Definition; DC = t2/t1.
t3
t4
80%
20%
Figure 2. Rise and Fall Time Definitions.
Document #: 38-07095 Rev. *A
Page 3 of 5
CY26111
Ordering Information
Ordering Code
Package Name
Z16
Package Type
Operating Range
Operating Voltage
3.3V
CY26111ZC
16-Pin TSSOP
Commercial
Test Circuit
V
DD
CLK out
CLOAD
0.1 µF
0.1 µF
OUTPUTS
AV
DD
GND
Document #: 38-07095 Rev. *A
Page 4 of 5
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY26111
Document Title: CY26111 One-PLL General Purpose Clock Generator
Document Number: 38-07095
REV.
**
ECN NO.
107330
121865
Issue Date
08/28/01
12/14/02
Orig. of Change
Description of Change
CKN
RBI
New Data Sheet
*A
Power up requirements added to Operating
Conditions Information
Document #: 38-07095 Rev. *A
Page 5 of 5
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