CY26049ZXI-36T_技术文档

CY26049-36

FailSafe™ PacketClock™ Global Communications

Clock Generator

• When reference is in range, SAFE pin is driven high.

• When reference is off, DCXO maintains clock outputs.

Features

• Fully integrated phase-locked loop (PLL)

SAFE pin is low.

• FailSafe output

• DCXOmaintainscontinuousoperationshouldtheinput

reference clock fail

• PLL driven by a crystal oscillator that is phase aligned

with external reference

• Glitch-free transition simplifies system design

• Output frequencies selectable and/or programmed to

standard communication frequencies

• Selectable output clock rates include T1/DS1, E1,

T3/DS3, E3, and OC-3.

• Low-jitter, high-accuracy outputs

• Commercial and Industrial operation

• 3.3V ± 5% operation

• Works with commonly available, low-cost 18.432-MHz

crystal

• Zero-ppm error for all output frequencies

• Performance guaranteed for applications that require

• 16-lead TSSOP

an extended temperature range

Benefits

• Compatible across industry standard design platforms

• Industry standard package with 6.4 x 5.0 mm²footprint

and a height profile of just 1.1 mm.

• Integrated high-performance PLL tailored for telecom-

munications frequency synthesis eliminates the need

for external loop filter components

Logic Block Diagram

external pullable crystal

(18.432 MHz)

XOUT

XIN

Input reference

(typical 8 kHz)

PHASE

LOCKED

LOOP

TM

ICLK

CLK

FAILSAFE

DIGITAL

CONTROL

CONTROLLED

CRYSTAL

OUTPUT

DIVIDERS

CLK/2

OSCILLATOR

FS[3:0]

frequency select

8K

SAFE

High=ICLK detected

Pin Configuration

CY26049-36

16-pin TSSOP

Top View

ICLK

8K

1

2

3

4

5

6

7

8

16 NC

15 CLK

14 FS0

13 FS3

12 VDD

11 VSS

10 SAFE

FS1

FS2

VDD

VSS

CLK/2

XIN

9

XOUT

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-07415 Rev. *C

Revised July 16, 2004

CY26049-36

Pin Definitions

Pin Name Pin Number

Pin Description

Reference Input Clock; 8 kHz or 10 to 60 MHz.

ICLK

1

8K

FS1

FS2

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

Clock Output; 8 kHz or high impedance in buffer mode.

Frequency Select 1; Determines CLK outputs per Table 1.

Frequency Select 2; Determines CLK outputs per Table 1.

Voltage Supply; 3.3V.

VDD

VSS

CLK/2

XIN

XOUT

SAFE

VSS

VDD

FS3

Ground

Clock Output; Frequency per Table 1.

Pullable Crystal Input; 18.432 MHz.

Pullable Crystal Output; 18.432 MHz.

High = reference ICLK within range, Low = reference ICLK out of range.

Ground

Voltage Supply; 3.3V.

Frequency Select 3; Determines CLK outputs per Table 1.

Frequency Select 0; Determines CLK outputs per Table 1.

Clock Output; Frequency per Table 1.

No Connect

FS0

CLK

NC

Selector Guide

Part Number

Input Frequency Range

Outputs

Output Frequencies

CY26049-36 8 kHz or 10 to 60 MHz Reference Input

3

8 kHz to 155.52 MHz

Crystal: 18.432-MHz pullable Crystal per Cypress Specification

Selectable (see Table 1)

is in fact the primary clocking source. When the reference

clock is restored, the DCXO automatically re-synchronizes to

the reference. The status of the reference clock input, as

detected by the CY26049-36, is reported by the SAFE pin.

In the buffer mode (FS3:FS0 = 1110 or 1111), the CY26049-36

can be used as a jitter attenuator. In this mode, extensive jitter

on the input clock will be “filtered”, resulting in a low-jitter

output clock.

Functional Description

CY26049 is a FailSafe frequency synthesizer with a reference

clock input and three clock outputs. The device provides an

optimum solution for applications where continuous operation

is required in the event of a primary clock failure. The

continuous, glitch-free operation is achieved by using a DCXO

which serves as a primary clock source. The FailSafe control

circuit synchronizes the DCXO with the reference as long as

the reference is within the pull range of the crystal.

In the event of a reference clock failure the DCXO maintains

the last frequency and phase information of the reference

clock. The unique feature of the CY26049-36 is that the DCXO

Document #: 38-07415 Rev. *C

Page 2 of 7

CY26049-36

Frequency Select Tables

Table 1. CY26049-36 Frequency Select–Output Decoding Table–External Mode (MHz except as noted)

ICLK

8 kHz

FS3

0

1

FS2

0

1

0

1

FS1

0

1

0

1

0

1

0

FS0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

CLK/2

1.544

2.048

22.368

17.184

77.76

CLK

3.088

4.096

8K

8 kHz

High Z^[1]

8 kHz

High Z^[1]

8 kHz

Crystal

18.432

44.736

34.368

155.52

32.768

28.704

High Z^[1]

37.056

24.704

15.36

16.384

14.352

High Z^[1]

18.528

12.352

7.68

High Z^[1]

12.288

16.384

High Z^[1]

24.576

32.768

Table 2. CY26049-36 Frequency Select–Output Decoding Table–Buffer Mode

ICLK

20 to 60

10 to 30

FS3

1

FS2

1

FS1

1

FS0

0

1

CLK/2

ICLK/2

2*ICLK

CLK

ICLK

4*ICLK

8K

Crystal

ICLK/2

ICLK

High Z^[1]

Note:

1. High Z = high impedance.

Document #: 38-07415 Rev. *C

Page 3 of 7

CY26049-36

Data Retention @ Tj=125°C...................................>10 years

Package Power Dissipation...................................... 350 mW

ESD (Human Body Model) MIL-STD-883.................... 2000V

Absolute Maximum Conditions

Supply Voltage (V_DD)........................................–0.5 to +7.0V

DC Input Voltage........................................–0.5V to V_DD+0.5

Storage Temperature (Non-Condensing)....–55°C to +125°C

Junction Temperature ................................ –40°C to +125°C

(Above which the useful life may be impaired. For user guide-

lines, not tested.

Recommended Pullable Crystal Specifications^[2]

Parameter

Description

Comments

Min.

Typ.

Max. Units

F_NOM

Nominal crystal frequency

Parallelresonance,fundamentalmode,

–

18.432

–

MHz

AT cut

C_LNOM

R₁

R₃/R₁

Nominal load capacitance

Equivalent series resistance (ESR)

–

3

14

–

25

–

pF

Ω

Fundamental mode

Ratio of third overtone mode ESR to

Ratio used because typical R₁values

fundamental mode ESR

are much less than the maximum spec

DL

Crystal drive level

No external series resistor assumed

–

400

–

0.5

–

2

–

mW

ppm

F_3SEPHI

F_3SEPLO

C₀

Third overtone separation from 3*F_NOMHigh side

Third overtone separation from 3*F_NOMLow side

Crystal shunt capacitance

–200 ppm

7

–

pF

C₀/C₁

C₁

Ratio of shunt to motional capacitance

Crystal motional capacitance

180

14.4

–

18

250

21.6

fF

Recommended Operating Conditions

Parameter

Description

Min.

3.15

0

–40

–

Typ.

3.3

–

Max.

3.45

70

85

Unit

V

° C

pF

V_DD

T_AC

T_AI

Operating Voltage

Ambient Temperature (Commercial Temperature)

Ambient Temperature (Industrial Temperature)

Max Output Load Capacitance

C_LOAD

t_pu

–

15

Power-up time for all V_DDs to reach minimum

0.05

–

500

ms

specified voltage (power ramps must be monotonic)

t_ER(I)

8 kHz Input Edge Rate, 20% to 80% of V_DD= 3.3V

0.07

–

V/ns

DC Electrical Specifications (Commercial Temp: 0° to 70°C)

Parameter

I_OH

I_OL

V_IH

V_IL

I_IH

Description

Output High Current

Output Low Current

Input High Voltage

Input High Current

Input Low Current

Input Capacitance

Test Conditions

V_OH= V_DD– 0.5, V_DD= 3.3V (source)

V_OL= 0.5, V_DD= 3.3V (sink)

CMOS Levels

V_IH=V_DD

Min.

Typ.

24

–

5

–

± 5

–

Max.

–

Unit

mA

V_DD

µA

pF

µA

mA

12

0.7

–

0.3

10

7

–

45

30

I_IL

V_IL=0V

C_IN

I_OZ

I_DD

Output Leakage Current High Z^[1]output

Supply Current C_LOAD= 15 pF, V_DD= 3.45V, FS [3:0] = 0100

_LOAD= 15 pF, V_DD= 3.45V, FS [3:0] = 1101

C

Note:

2. Ecliptek ECX-5761-18.432 M and ECX-5762-18.432 M meets these specifications.

Document #: 38-07415 Rev. *C

Page 4 of 7

CY26049-36

DC Electrical Specifications (Industrial Temp: –40° to 85°C)

Parameter

I_OH

I_OL

V_IH

V_IL

I_IH

Description

Output High Current

Output Low Current

Input High Voltage

Input High Current

Input Low Current

Input Capacitance

Test Conditions

V_OH= V_DD– 0.5, V_DD= 3.3V (source)

V_OL= 0.5, V_DD= 3.3V (sink)

CMOS Levels

V_IH= V_DD

Min. Typ. Max. Unit

10

0.7

–

20

–

5

–

0.3

10

7

mA

V_DD

µA

I_IL

V_IL= 0V

5

–

µA

pF

C_IN

I_OZ

I_DD

–

Output Leakage Current High Z^[1]output

Supply Current C_LOAD= 15 pF, V_DD= 3.45V, FS [3:0] = 0100

C_LOAD= 15 pF, V_DD= 3.45V, FS [3:0] = 1101

–

± 5

–

50

35

µA

mA

AC Electrical Specifications (Commercial Temp: 0° to 70° C and Industrial Temp: –40° to 85°C)

Parameter

f_ICLK-E

f_ICLK-B

LR

Description

Frequency, Input Clock

FailSafe Lock Range^[3]

Test Conditions

Input Clock Frequency, External Mode

Input Clock Frequency, Buffer Mode

Range of reference ICLK for Safe = High

Min. Typ. Max. Unit

–

8.00

–

kHz

10

–

60 MHz

–250

–

+250 ppm

DC = t₂/t₁Output Duty Cycle

T_PJIT1

Duty Cycle defined in Figure 1, measured at 50% of V_DD45

50

–

55

250

50

500

100

3

%

ps

ms

s

Clock Jitter; output > 5 MHz Period Jitter, Peak to Peak, 10,000 periods

–

RMS Period Jitter, RMS

Clock Jitter; output <5 MHz Period Jitter, Peak to Peak, 10,000 periods

RMS Period Jitter, RMS

–

T_PJIT2

t₆

PLL Lock Time

Time for PLL to lock within ± 150 ppm of target frequency

–

t_{fs_lock}

Failsafe Lock Time

Time for PLL to lock to ICKL (outputs phase aligned with

7

ICKL and Safe = High)

f_error

ER

Frequency Synthesis Error Actual mean frequency error vs. target

–

0

1.4

–

2

ppm

V/ns

Rising Edge Rate

Output Clock Edge Rate, Measured from 20% to 80% of 0.8

V

_DD, C_LOAD= 15 pF See Figure 2.

EF

Falling Edge Rate

Output Clock Edge Rate, Measured from 20% to 80% of 0.8

1.4

2

V/ns

V_DD, C_LOAD= 15 pF See Figure 2.

Voltage and Timing Definitions

t1

t2

CLK

50%

Figure 1. Duty Cycle Definition; DC = t2/t1

t4

t3

80%

20%

CLK

Figure 2. Rise and Fall Time Definitions: ER = 0.6 x VDD / t3, EF = 0.6 x VDD / t4

Note:

3. Dependent on crystals chosen and crystal specs.

Document #: 38-07415 Rev. *C

Page 5 of 7

CY26049-36

Test Circuit

ICLK

8K

1

2

3

4

5

6

7

8

16

15

14

13

12

11

CLK

C_LOAD

VDD

0.1uF

VDD

0.1uF

CLK/2

10

9

C_LOAD

18.432 MHz

Ordering Information

Ordering Code

CY26049ZC-36

CY26049ZC-36T

CY26049ZI-36

Package Type

16-lead TSSOP

16-lead TSSOP–Tape and Reel

16-lead TSSOP

Operating Temperature Range

Commercial 0 to 70°C

Industrial –40 to 85°C

CY26049ZI-36T

Lead Free

CY26049ZXC-36

CY26049ZXC-36T

CY26049ZXI-36

CY26049ZXI-36T

16-lead TSSOP–Tape and Reel

Industrial –40 to 85°C

16-lead TSSOP

16-lead TSSOP–Tape and Reel

16-lead TSSOP

Commercial 0 to 70°C

Industrial –40 to 85°C

16-lead TSSOP–Tape and Reel

Package Diagram

16-lead TSSOP 4.40 MM Body Z16.173

PIN 1 ID

DIMENSIONS IN MM[INCHES] MIN.

MAX.

1

REFERENCE JEDEC MO-153

6.25[0.246]

6.50[0.256]

PACKAGE WEIGHT 0.05 gms

4.30[0.169]

4.50[0.177]

PART #

Z16.173 STANDARD PKG.

ZZ16.173 LEAD FREE PKG.

16

0.65[0.025]

BSC.

0.25[0.010]

BSC

0.19[0.007]

0.30[0.012]

1.10[0.043] MAX.

GAUGE

PLANE

0°-8°

0.076[0.003]

0.50[0.020]

0.70[0.027]

0.05[0.002]

0.15[0.006]

0.85[0.033]

0.95[0.037]

0.09[[0.003]

0.20[0.008]

SEATING

PLANE

4.90[0.193]

5.10[0.200]

51-85091-*A

FailSafe and PacketClock are trademarks of Cypress Semiconductor. All product and company names mentioned in this document

are the trademarks of their respective holders.

Document #: 38-07415 Rev. *C

Page 6 of 7

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

CY26049-36

Document History Page

Document Title: CY26049-36 FailSafe™ PacketClock™ Global Communications Clock Generator

Document Number: 38-07415

Orig. of

REV. ECN NO. Issue Date Change

Description of Change

**

114749

08/08/02

CKN

New Data Sheet

*A

120067

01/06/03

CKN

Changed “FailSafe is a trademark of Silicon Graphics, Inc.” to read “FailSafe is a

trademark of Cypress Semiconductor”

*B

128000

07/15/03

IJA

Changed Benefits to read “When reference is in range, SAFE pin is driven high”

Changed first sentence to “CY26049 is a FailSafe frequency synthesizer with a

reference clock input and three clock outputs”

Changed title from “Failsafe PacketClock Global Communications Clocks” to

“FailSafe PacketClock Global Communications Clock Generator”

Changed definitions in Pin Description Table

Replaced format for Absolute Maximum Conditions

Replaced Recommended Pullable Crystal Specifications table

Added t_puto Recommended Operating Conditions

Added I_IHand I_ILto DC Electrical Specifications

Replaced AC Electrical Specifications from Cy26049-16 data sheet

Changed Voltage and Timing Definitions to match CY2410 data sheet

Moved Package Diagram to end of data sheet

*C

244412

See ECN

RGL

Spec. (t_ER(I)) Input Edge Rate in the Recommended Operating Conditions Table

Added Lead Free Devices

Document #: 38-07415 Rev. *C

Page 7 of 7


型号：	CY26049ZXI-36T
厂家：	CYPRESS
描述：	Clock Generator, 155.52MHz, CMOS, PDSO16, 4.40 MM, LEAD FREE, MO-153, TSSOP-16 时钟光电二极管外围集成电路晶体
文件：	总7页 (文件大小：147K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY26049ZXI-36T [CYPRESS]

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