CY23S05SC-1H [CYPRESS]
Low-Cost 3.3V Spread Aware⑩ Zero Delay Buffer; 低成本3.3V传播感知™零延迟缓冲器
| 型号： | CY23S05SC-1H |
| 厂家： | 
CYPRESS |
| 描述： | Low-Cost 3.3V Spread Aware⑩ Zero Delay Buffer |
| 文件： | 总9页 (文件大小：174K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
05
CY23S09
CY23S05
Low-Cost 3.3V Spread Aware™ Zero Delay Buffer
up to 100-/133-MHz frequencies, and have higher drive than
the -1 devices. All parts have on-chip PLLs that lock to an input
Features
• 10-MHz to 100-/133-MHz operating range, compatible
with CPU and PCI bus frequencies
clock on the REF pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad.
• Zero input-output propagation delay
• Multiple low-skew outputs
The CY23S09 has two banks of four outputs each, which can
be controlled by the Select inputs as shown in the Select Input
Decoding table on page 2. If all output clocks are not required,
Bank B can be three-stated. The select inputs also allow the
input clock to be directly applied to the outputs for chip and
system testing purposes.
— Output-output skew less than 250 ps
— Device-device skew less than 700 ps
— One input drives five outputs (CY23S05)
The CY23S09 and CY23S05 PLLs enter a power-down mode
when there are no rising edges on the REF input. In this state,
the outputs are three-stated and the PLL is turned off, resulting
in less than 12.0 µA of current draw (for commercial temper-
ature devices) and 25.0 µA (for industrial temperature
devices). The CY23S09 PLL shuts down in one additional
case, as shown in the table below.
— One input drives nine outputs, grouped as 4 + 4 + 1
(CY23S09)
• Less than 200 ps cycle-to-cycle jitter is compatible with
Pentium -based systems
• Test Mode to bypass PLL (CY23S09 only, see Select
Input Decoding table on page 2)
Multiple CY23S09 and CY23S05 devices can accept the same
input clock and distribute it. In this case, the skew between the
outputs of two devices is guaranteed to be less than 700 ps.
• Available in space-saving 16-pin, 150-mil SOIC, 4.4 mm
TSSOP, and 150-mil SSOP ( CY23S09) or 8-pin, 150-mil
SOIC package (CY23S05)
All outputs have less than 200 ps of cycle-to-cycle jitter. The
input to output propagation delay on both devices is
guaranteed to be less than 350 ps, and the output to output
skew is guaranteed to be less than 250 ps.
• 3.3V operation, advanced 0.65µ CMOS technology
• Spread Aware™
Functional Description
The CY23S05/CY23S09 is available in two different configu-
rations, as shown in the ordering information on page 6. The
CY23S05-1/CY23S09-1 is the base part. The CY23S05-1H/
CY23S09-1H is the high-drive version of the -1, and its rise
and fall times are much faster than -1.
The CY23S09 is a low-cost 3.3V zero delay buffer designed to
distribute high-speed clocks and is available in a 16-pin SOIC
package. The CY23S05 is an eight-pin version of the
CY23S09. It accepts one reference input, and drives out five
low-skew clocks. The -1H versions of each device operate at
Block Diagram
Pin Configuration
SOIC/TSSOP/SSOP
Top View
CLKOUT
PLL
MUX
REF
CLKA1
CLKA2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
REF
CLKA1
CLKOUT
CLKA4
CLKA3
VDD
CLKA3
CLKA4
CLKA2
VDD
GND
CLKB4
CLKB3
S1
GND
CLKB1
CLKB1
CLKB2
CLKB3
CLKB4
S2
Select Input
Decoding
CLKB2
S2
S1
CY23S09
CY23S09
SOIC
Top View
REF
PLL
CLKOUT
CLK1
CLK2
CLK3
1
8
CLKOUT
CLK4
V
DD
REF
CLK2
CLK1
GND
2
3
4
7
6
5
CLK3
CLK4
CY23S05
CY23S05
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-07296 Rev. *B
Revised December 22, 2002
CY23S05
CY23S09
Select Input Decoding for CY23S09
S2
S1
CLOCK A1–A4
Three-state
Driven
CLOCK B1–B4
Three-state
Three-state
Driven
CLKOUT[1]
Driven
Output Source
PLL
PLL Shut-down
0
0
N
N
Y
N
0
1
Driven
PLL
1
0
Driven
Driven
Reference
PLL
1
1
Driven
Driven
Driven
Spread Aware
Zero Delay and Skew Control
Many systems being designed now utilize a technology called
Spread Spectrum Frequency Timing Generation. Cypress has
been one of the pioneers of SSFTG development, and we
designed this product so as not to filter off the Spread
Spectrum feature of the Reference input, assuming it exists.
When a zero delay buffer is not designed to pass the SS
feature through, the result is a significant amount of tracking
skew which may cause problems in systems requiring
synchronization.
All outputs should be uniformly loaded to achieve Zero Delay
between the input and output. Since the CLKOUT pin is the
internal feedback to the PLL, its relative loading can adjust the
input-output delay. This is shown in the above graph.
For applications requiring zero input-output delay, all outputs,
including CLKOUT, must be equally loaded. Even if CLKOUT
is not used, it must have a capacitive load equal to that on
other outputs, for obtaining zero input-output delay. If input to
output delay adjustments are required, use the above graph to
calculate loading differences between the CLKOUT pin and
other outputs.
For more details on Spread Spectrum timing technology,
please see the Cypress application note entitled, “EMI
Suppression Techniques with Spread Spectrum Frequency
Timing Generator (SSFTG) ICs.”
For zero output-output skew, be sure to load all outputs
equally. For further information, refer to the application note
“CY23S05 and CY23S09 as PCI and SDRAM Buffers.”
Note:
1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output.
Document #: 38-07296 Rev. *B
Page 2 of 9
CY23S05
CY23S09
Pin Description for CY23S09
Pin
Signal
Description
Input reference frequency, 5V-tolerant input
1
REF[2]
CLKA1[3]
CLKA2[3]
VDD
2
Buffered clock output, bank A
Buffered clock output, bank A
3.3V supply
3
4
5
GND
Ground
6
CLKB1[3]
CLKB2[3]
S2[4]
Buffered clock output, bank B
Buffered clock output, bank B
Select input, bit 2
7
8
9
S1[4]
Select input, bit 1
10
11
12
13
14
15
16
CLKB3[3]
CLKB4[3]
GND
Buffered clock output, bank B
Buffered clock output, bank B
Ground
VDD
3.3V supply
CLKA3[3]
CLKA4[3]
Buffered clock output, bank A
Buffered clock output, bank A
Buffered output, internal feedback on this pin
CLKOUT[3]
Pin Description for CY23S05
Pin
Signal
Description
Input reference frequency, 5V-tolerant input
Buffered clock output
1
REF[2]
CLK2[3]
CLK1[3]
GND
2
3
Buffered clock output
4
Ground
5
CLK3[3]
Buffered clock output
6
VDD
3.3V supply
7
CLK4[3]
Buffered clock output
8
CLKOUT[3]
Buffered clock output, internal feedback on this pin
Notes:
2. Weak pull-down.
3. Weak pull-down on all outputs.
4. Weak pull-up on these inputs.
Document #: 38-07296 Rev. *B
Page 3 of 9
CY23S05
CY23S09
Storage Temperature ................................. –65°C to +150°C
Max. Soldering Temperature (10 sec.) ....................... 260°C
Junction Temperature................................................. 150°C
Maximum Ratings
Supply Voltage to Ground Potential............... –0.5V to +7.0V
DC Input Voltage (Except REF) ............–0.5V to VDD + 0.5V
DC Input Voltage REF............................................. −0.5V to 7V
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ........................... > 2,000V
Operating Conditions for CY23S05SC-XX and CY23S09SC-XX Commercial Temperature Devices [5]
Parameter
Description
Min.
3.0
0
Max.
3.6
70
Unit
V
VDD
TA
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance, below 100 MHz
Load Capacitance, from 100 MHz to 133 MHz
Input Capacitance
°C
pF
pF
pF
CL
30
CL
10
CIN
7
Electrical Characteristics for CY23S05SC-XX and CY23S09SC-XX Commercial Temperature Devices
Parameter
Description
Input LOW Voltage[6]
Input HIGH Voltage[6]
Input LOW Current
Input HIGH Current
Test Conditions
Min.
Max.
Unit
V
VIL
VIH
IIL
0.8
2.0
V
VIN = 0V
50.0
µA
µA
IIH
VIN = VDD
100.0
IOL = 8 mA (–1)
IOH = 12 mA (–1H)
VOL
VOH
Output LOW Voltage[7]
Output HIGH Voltage[7]
0.4
V
IOH = –8 mA (–1)
IOL = –12 mA (–1H)
2.4
V
I
DD (PD mode) Power-down Supply Current
REF = 0 MHz
12.0
32.0
µA
mA
Unloaded outputs at 66.67 MHz,
SEL inputs at VDD
IDD Supply Current
Switching Characteristics for CY23S05SC-1 and CY23S09SC-1 Commercial Temperature Devices[8]
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Unit
t1
Output Frequency
30-pF load
10-pF load
10
10
100
133.33
MHz
MHz
Duty Cycle[7] = t2 ÷ t1
Rise Time[7]
Fall Time[7]
Measured at 1.4V, Fout = 66.67 MHz
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
All outputs equally loaded
40.0
50.0
60.0
2.50
2.50
250
%
ns
ns
ps
ps
t3
t4
t5
t6
Output-to-Output Skew[7]
Delay, REF Rising Edge to
CLKOUT Rising Edge[7]
Device-to-Device Skew[7]
Measured at VDD/2
0
0
±350
t7
Measured at VDD/2 on the CLKOUT
pins of devices
700
ps
tJ
Cycle-to-Cycle Jitter[7]
PLL Lock Time[7]
Measured at 66.67 MHz, loaded outputs
200
1.0
ps
tLOCK
Stable power supply, valid clock
presented on REF pin
ms
Notes:
5. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
6. REF input has a threshold voltage of VDD/2.
7. Parameter is guaranteed by design and characterization. Not 100% tested in production.
8. All parameters specified with loaded outputs.
Document #: 38-07296 Rev. *B
Page 4 of 9
CY23S05
CY23S09
Switching Characteristics for CY23S05SI-1H and CY23S09SI-1H Industrial Temperature Devices[8]
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Unit
30-pF load
10-pF load
10
10
100
133.33
MHz
MHz
t1
Output Frequency
Duty Cycle[7] = t2 ÷ t1
Duty Cycle[7] = t2 ÷ t1
Rise Time[7]
Fall Time[7]
Output-to-Output Skew[7]
Measured at 1.4V, Fout = 66.67 MHz
Measured at 1.4V, Fout <50.0 MHz
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
All outputs equally loaded
40.0
45.0
50.0
50.0
60.0
55.0
1.50
1.50
250
%
%
t3
t4
t5
ns
ns
ps
Delay, REF Rising Edge to
CLKOUT Rising Edge[7]
t6
t7
Measured at VDD/2
0
0
±350
700
ps
ps
Measured at VDD/2 on the CLKOUT
pins of devices
Device-to-Device Skew[7]
Measuredbetween0.8Vand2.0Vusing
Test Circuit #2
t8
tJ
Output Slew Rate[7]
Cycle-to-Cycle Jitter[7]
PLL Lock Time[7]
1
V/ns
ps
Measured at 66.67 MHz, loaded outputs
200
1.0
Stable power supply, valid clock
presented on REF pin
tLOCK
ms
Switching Waveforms
Duty Cycle Timing
t
1
t
2
1.4V
1.4V
1.4V
2309–4
All Outputs Rise/Fall Time
3.3V
2.0V
OUTPUT
0.8V
2.0V
0.8V
0V
t
3
t
4
2309–5
Output-Output Skew
1.4V
OUTPUT
1.4V
OUTPUT
2309–6
t
5
Document #: 38-07296 Rev. *B
Page 5 of 9
CY23S05
CY23S09
Switching Waveforms (continued)
Input-Output Propagation Delay
V
/2
DD
INPUT
V
/2
DD
OUTPUT
2309–7
t
6
Device-Device Skew
CLKOUT, Device 1
CLKOUT, Device 2
V
/2
DD
V
/2
DD
2309–8
t
7
Test Circuits
Test Circuit # 2
Test Circuit # 1
VDD
VDD
1 kΩ
1 kΩ
0.1 µF
CLK out
0.1 µF
0.1 µF
OUTPUTS
OUTPUTS
10 pF
CLOAD
VDD
VDD
0.1 µF
GND
GND
GND
GND
For parameter t (output slew rate) on –1H devices
8
Ordering Information
Ordering Code
CY23S05SC-1
Package Name
Package Type
8-pin 150-mil SOIC
8-pin 150-mil SOIC
16-pin 150-mil SOIC
16-pin 150-mil SOIC
16-pin 4.4mm TSSOP
16-pin 4.4mm TSSOP
16-pin 150-mil SSOP
16-pin 150-mil SSOP
Operating Range
Commercial
S8
S8
CY23S05SC-1H
CY23S09SC-1
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
S16
S16
Z16
Z16
O16
O16
CY23S09SC-1H
CY23S09ZC-1
CY23S09ZC-1H
CY23S09OC-1
CY23S09OC-1H
Document #: 38-07296 Rev. *B
Page 6 of 9
CY23S05
CY23S09
Package Diagram
8-lead (150-Mil) SOIC S8
51-85066-A
16-lead (150-Mil) Molded SOIC S16
51-85068-A
Document #: 38-07296 Rev. *B
Page 7 of 9
CY23S09
CY23S05
16-lead Thin Shrunk Small Outline Package (4.40-MM Body) Z16
51-85091
16-lead (150-mil) QSOP Q1
51-85053-B
Pentium is a registered trademark of Intel Corporation. Spread Aware is a trademark of Cypress Semiconductor Corporation. All
product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-07296 Rev. *B
Page 8 of 9
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY23S05
CY23S09
Document Title: CY23S09/CY23S05 Low-Cost 3.3V Spread Aware™ Zero Delay Buffer
Document Number: 38-07296
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
111147
Description of Change
Change from spec number 38-01094 to 38-07296
Add 150-mil SSOP option
11/14/01
02/20/02
12/22/02
DSG
CTK
RBI
*A
111773
122885
*B
Added power up requirements to Operating Conditions
Document #: 38-07296 Rev. *B
Page 9 of 9
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