CY23S08 [CYPRESS]
3.3V Zero Delay Buffer; 3.3V零延迟缓冲器
| 型号： | CY23S08 |
| 厂家： | 
CYPRESS |
| 描述： | 3.3V Zero Delay Buffer |
| 文件： | 总8页 (文件大小：167K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
CY23S08
3.3V Zero Delay Buffer
The CY23S08 has two banks of four outputs each, which can
be controlled by the Select inputs as shown in Table 1. If all
output clocks are not required, Bank B can be three-stated.
The select inputs also allow the input clock to be directly
applied to the output for chip and system testing purposes.
The CY23S08 PLL enters a power-down state when there are
no rising edges on the REF input. In this mode, all outputs are
three-stated and the PLL is turned off, resulting in less than
50 µA of current draw. The PLL shuts down in two additional
cases as shown in Table 1.
Multiple CY23S08 devices can accept the same input clock
and distribute it in a system. In this case, the skew between
the outputs of two devices is guaranteed to be less than
700 ps.
The CY23S08 is available in five different configurations, as
shown in Table 2. The CY23S08–1 is the base part, where the
output frequencies equal the reference if there is no counter in
the feedback path. The CY23S08–1H is the high-drive version
of the –1, and rise and fall times on this device are much faster.
Features
• Zero input-output propagation delay, adjustable by
capacitive load on FBK input
• Multiple configurations, see Table 2
• Multiple low-skew outputs
— Output-output skew less than 200 ps
— Device-device skew less than 700 ps
— Two banks of four outputs, three-stateable by two
select inputs
• 10-MHz to 133-MHz operating range
• Low jitter, less than 200 ps cycle-cycle (–1, –1H, –4)
• Advanced 0.65µ CMOS technology
• Space-saving 16-pin 150-mil SOIC/TSSOP packages
• 3.3V operation
• Spread Aware™
The CY23S08–2 allows the user to obtain 2X and 1X
frequencies on each output bank. The exact configuration and
output frequencies depends on which output drives the
feedback pin. The CY23S08–2H is the high-drive version of
the –2, and rise and fall times on this device are much faster.
Functional Description
The CY23S08 is a 3.3V zero delay buffer designed to
distribute high-speed clocks in PC, workstation, datacom,
telecom, and other high-performance applications.
The part has an on-chip PLL which locks to an input clock
presented on the REF pin. The PLL feedback is required to be
driven into the FBK pin, and can be obtained from one of the
outputs. The input-to-output propagation delay is guaranteed
to be less than 350 ps, and output-to-output skew is
guaranteed to be less than 250 ps.
The CY23S08–3 allows the user to obtain 4X and 2X
frequencies on the outputs.
The CY23S08–4 enables the user to obtain 2X clocks on all
outputs. Thus, the part is extremely versatile, and can be used
in a variety of applications.
Pin Configuration
Block Diagram
/2
FBK
PLL
SOIC
REF
MUX
Top View
CLKA1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
REF
CLKA1
FBK
CLKA2
CLKA3
CLKA4
Extra Divider (–3, –4)
CLKA4
CLKA3
VDD
CLKA2
VDD
S2
GND
GND
CLKB1
Select Input
CLKB4
CLKB3
S1
Decoding
S1
/2
CLKB2
CLKB1
CLKB2
CLKB3
CLKB4
S2
Extra Divider (–2, –2H, –3)
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-07265 Rev. *D
Revised June 03, 2004
PRELIMINARY
CY23S08
Table 1. Select Input Decoding
S2
0
0
1
1
S1
0
1
0
1
CLOCK A1–A4
Three-State
Driven
CLOCK B1–B4
Three-State
Three-State
Driven
Output Source
PLL
PLL Shutdown
Y
N
Y
N
PLL
Reference
PLL
Driven
Driven
Driven
Table 2. Available CY23S08 Configurations
Device
CY23S08–1
CY23S08–1H
CY23S08–2
CY23S08–2H
CY23S08–2
CY23S08–2H
CY23S08–3
CY23S08–3
CY23S08–4
Pin Description
Pin
Feedback From
Bank A or Bank B
Bank A or Bank B
Bank A
Bank A
Bank B
Bank B
Bank A
Bank B
Bank A or Bank B
Bank A Frequency
Reference
Reference
Reference
Reference
2 X Reference
2 X Reference
2 X Reference
4 X Reference
2 X Reference
Bank B Frequency
Reference
Reference
Reference/2
Reference/2
Reference
Reference
Reference or Reference[1]
2 X Reference
2 X Reference
Signal
Description
1
2
3
4
REF[2]
CLKA1[3]
CLKA2[3]
VDD
Input reference frequency, 5V tolerant input
Clock output, Bank A
Clock output, Bank A
3.3V supply
5
6
7
8
GND
Ground
CLKB1[3]
CLKB2[3]
S2[4]
Clock output, Bank B
Clock output, Bank B
Select input, bit 2
Select input, bit 1
Clock output, Bank B
Clock output, Bank B
Ground
9
S1[4]
10
11
12
13
14
15
16
CLKB3[3]
CLKB4[3]
GND
VDD
3.3V supply
CLKA3[3]
CLKA4[3]
FBK
Clock output, Bank A
Clock output, Bank A
PLL feedback input
For more details on Spread Spectrum timing technology,
please see Cypress’s application note EMI Suppression
Techniques with Spread Spectrum Frequency Timing
Generator (SSFTG) ICs.
Spread Aware™
Many systems being designed now utilize a technology called
Spread Spectrum Frequency Timing Generation. Cypress has
been one of the pioneers of SSFTG development, and we
designed this product so as not to filter off the Spread
Spectrum feature of the Reference input, assuming it exists.
When a zero delay buffer is not designed to pass the SS
feature through, the result is a significant amount of tracking
skew which may cause problems in systems requiring
synchronization.
Notes:
1. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the CY23S08–2.
2. Weak pull-down.
3. Weak pull-down on all outputs.
4. Weak pull-ups on these inputs.
Document #: 38-07265 Rev. *D
Page 2 of 8
PRELIMINARY
CY23S08
Storage Temperature ................................. –65°C to +150°C
Max. Soldering Temperature (10 sec.) ....................... 260°C
Junction Temperature................................................. 150°C
Maximum Ratings
Supply Voltage to Ground Potential............... –0.5V to +7.0V
DC Input Voltage (Except Ref)...............–0.5V to VDD + 0.5V
DC Input Voltage REF............................................–0.5 to 7V
Static Discharge Voltage
(per MIL-STD-883, Method 3015) .............................>2000V
Operating Conditions for CY23S08SC-XX Commercial Temperature Devices[5]
Parameter
VDD
Description
Min.
3.0
0
Max.
3.6
70
30
15
Unit
V
°C
pF
pF
pF
Supply Voltage
TA
CL
Operating Temperature (Ambient Temperature)
Load Capacitance, below 100 MHz
Load Capacitance, from 100 MHz to 133 MHz
Input Capacitance[6]
CIN
7
Electrical Characteristics for CY23S08SC-XX Commercial Temperature Devices
Parameter
Description
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Output LOW Voltage[7]
Test Conditions
Min.
Max
0.8
Unit
V
V
µA
µA
V
VIL
VIH
IIL
2.0
VIN = 0V
50.0
100.0
0.4
IIH
VIN = VDD
VOL
IOL = 8 mA (–1, –2, –3, –4)
I
OL = 12 mA (-1H, -2H)
VOH
Output HIGH Voltage[7]
IOH = –8 mA (–1, –2, –3, –4)
2.4
V
I
OH = –12 mA (–1H, –2H)
IDD (PD mode)
IDD
Power-down Supply Current REF = 0 MHz
12.0
45.0
µA
mA
mA
Supply Current
Unloaded outputs, 100-MHz REF,
Select inputs at VDD or GND
70.0
(–1H, –2H)
Unloaded outputs, 66-MHz REF
(–1,–2,–3,–4)
32.0
18.0
mA
mA
Unloaded outputs, 33-MHz REF
(–1,–2,–3,–4)
Switching Characteristics for CY23S08SC-XX Commercial Temperature Devices [8]
Parameter
t1
t1
t1
t1
t1
Name
Output Frequency
Output Frequency
Output Frequency
Output Frequency
Output Frequency
Test Conditions
30-pF load, –1, –1H, –2, –3 devices
30-pF load, –4 devices
20-pF load, –1H device
15-pF load, –1, –2, –3, devices
15-pF load, –4 devices
Min.
10
15
10
10
15
40.0
Typ.
Max.
100
100
133.3
140.0
140.0
60.0
Unit
MHz
MHz
MHz
MHz
MHz
%
Duty Cycle[7] = t2 ÷ t1
Measured at VDD/2, FOUT = 66.66 MHz
50.0
50.0
(–1,–2,–3,–4,–1H, -2H)
30-pF load
Duty Cycle[7] = t2 ÷ t1
Measured at VDD/2, FOUT <66.66 MHz
15-pf load
45.0
55.0
%
(–1,–2,–3,–4,–1H, -2H)
t3
t3
Rise Time[7] (–1, –2, –3, –4) Measured between 0.8V and 2.0V, 30-pF load
Rise Time[7] (–1, –2, –3, –4) Measured between 0.8V and 2.0V, 15-pF load
2.20
1.50
ns
ns
Notes:
5. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
6. Applies to both Ref Clock and FBK.
7. Parameter is guaranteed by design and characterization. Not 100% tested in production.
8. All parameters are specified with loaded outputs.
Document #: 38-07265 Rev. *D
Page 3 of 8
PRELIMINARY
CY23S08
Switching Characteristics for CY23S08SC-XX Commercial Temperature Devices (continued)[8]
Parameter
t3
t4
t4
t4
t5
Name
Test Conditions
Measured between 0.8V and 2.0V, 30-pF load
Min.
Typ.
Max.
1.50
2.20
1.50
1.25
200
Unit
ns
ns
ns
ns
Rise Time[7] (–1H, -2H)
Fall Time[7] (–1, –2, –3, –4) Measured between 0.8V and 2.0V, 30-pF load
Fall Time[7] (–1, –2, –3, –4) Measured between 0.8V and 2.0V, 15-pF load
Fall Time[7] (–1H, 2H)
Measured between 0.8V and 2.0V, 30-pF load
Output to Output Skew on All outputs equally loaded
ps
same Bank (–1)[7]
Output to Output Skew on All outputs equally loaded
150
ps
same Bank
(–1H,–2,–2H,–3)[7]
Output to Output Skew on All outputs equally loaded
100
200
300
215
250
+275
700
ps
ps
same Bank (–4)[7]
Output to Output Skew
(–1H, -2H)
All outputs equally loaded
All outputs equally loaded
All outputs equally loaded
All outputs equally loaded
Output Bank A to Output
ps
Bank B Skew (–1,–2, –3)
Output Bank A to Output
Bank B Skew (–4)
ps
Output Bank A to Output
ps
Bank B Skew (–1H)
t6
t7
t8
tJ
Delay, REF Rising Edge to Measured at VDD/2
FBK Rising Edge[7]
–250
1
0
0
ps
Device to Device Skew[7] Measured at VDD/2 on the FBK pins of devic-
es
ps
Output Slew Rate[7]
Measured between 0.8V and 2.0V on –1H,
V/ns
ps
–2H device using Test Circuit #2
Cycle to Cycle Jitter[7]
(–1, –1H)
Measured at 66.67 MHz, loaded outputs, 15,
30-pF loads: 133 MHz, 15-pF load
125
300
400
200
1.0
Cycle to Cycle Jitter[7]
(–2)
Measured at 66.67 MHz, loaded outputs,
ps
15-pF load
Cycle to Cycle Jitter[7]
(–2)
Measured at 66.67 MHz, loaded outputs,
30-pF load
ps
tJ
Cycle to Cycle Jitter[7]
(–3,–4)
Measured at 66.67 MHz, loaded outputs
ps
15,30-pF loads
tLOCK
PLL Lock Time[7]
Stable power supply, valid clocks presented
on REF and FBK pins
ms
Switching Waveforms
Duty Cycle Timing
t
1
t
2
1.4V
1.4V
1.4V
All Outputs Rise/Fall Time
3.3V
0V
2.0V
2.0V
0.8V
OUTPUT
0.8V
t
3
t
4
Document #: 38-07265 Rev. *D
Page 4 of 8
PRELIMINARY
CY23S08
Switching Waveforms (continued)
Output-Output Skew
1.4V
OUTPUT
1.4V
OUTPUT
t
5
Input-Output Propagation Delay
V
DD/2
INPUT
FBK
VDD/2
t6
Device-Device Skew
VDD/2
FBK, Device 1
V
DD/2
FBK, Device 2
t7
Test Circuits
Test Circuit # 2
Test Circuit # 1
VDD
VDD
1 KΩ
CLK
0.1 µF
out
CLK OUT
CLOAD
0.1 µF
0.1 µF
OUTPUTS
OUTPUTS
1 KΩ
10 pF
VDD
VDD
0.1 µF
GND
GND
GND
GND
Test Circuit for all parameters except t8
Test Circuit for t8, Output slew rate on –1H device
Document #: 38-07265 Rev. *D
Page 5 of 8
PRELIMINARY
CY23S08
Ordering Information
Ordering Code
CY23S08SC–1
Package Name
Package Type
16-pin 150-mil SOIC
16-pin 150-mil SOIC–Tape and Reel
16-pin 150-mil SOIC
16-pin 150-mil SOIC–Tape and Reel
16-pin 150-mil TSSOP
16-pin 150-mil TSSOP–Tape and Reel
16-pin 150-mil SOIC
16-pin 150-mil SOIC–Tape and Reel
16-pin 150-mil SOIC
16-pin 150-mil SOIC–Tape and Reel
16-pin 150-mil SOIC
16-pin 150-mil SOIC–Tape and Reel
16-pin 150-mil SOIC
Operating Range
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
S16
S16
S16
S16
Z16
Z16
S16
S16
S16
S16
S16
S16
S16
S16
CY23S08SC–1T
CY23S08SC–1H
CY23S08SC–1HT
CY23S08ZC–1H
CY23S08ZC–1HT
CY23S08SC–2
CY23S08SC–2T
CY23S08SC–2H
CY23S08SC–2HT
CY23S08SC–3
CY23S08SC–3T
CY23S08SC–4
CY23S08SC–4T
16-pin 150-mil SOIC–Tape and Reel
Package Drawings and Dimensions
16-Lead (150-Mil) SOIC S16
PIN 1 ID
8
1
DIMENSIONS IN INCHES[MM] MIN.
MAX.
REFERENCE JEDEC MS-012
PACKAGE WEIGHT 0.15gms
0.150[3.810]
0.157[3.987]
0.230[5.842]
0.244[6.197]
PART #
S16.15 STANDARD PKG.
SZ16.15 LEAD FREE PKG.
9
16
0.010[0.254]
X 45°
0.386[9.804]
0.393[9.982]
0.016[0.406]
SEATING PLANE
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.0075[0.190]
0.0098[0.249]
0.016[0.406]
0.035[0.889]
0°~8°
0.0138[0.350]
0.0192[0.487]
0.004[0.102]
0.0098[0.249]
51-85068-*B
Document #: 38-07265 Rev. *D
Page 6 of 8
PRELIMINARY
CY23S08
Package Drawings and Dimensions (continued)
16-Lead Thin Shrunk Small Outline Package (4.40 MM Body) Z16
PIN 1 ID
1
6.25[0.246]
6.50[0.256]
4.30[0.169]
4.50[0.177]
16
0.65[0.025]
BSC.
0.25[0.010]
BSC
0.19[0.007]
0.30[0.012]
1.10[0.043] MAX.
GAUGE
PLANE
0°-8°
0.076[0.003]
0.50[0.020]
0.70[0.027]
0.05[0.002]
0.15[0.006]
0.85[0.033]
0.95[0.037]
0.09[[0.003]
0.20[0.008]
SEATING
PLANE
4.90[0.193]
5.10[0.200]
51-85091-*A
Spread Aware is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are
trademarks of their respective holders.
Document #: 38-07265 Rev. *D
Page 7 of 8
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
PRELIMINARY
CY23S08
Document History Page
Document Title: CY23S08 3.3V Zero Delay Buffer
Document Number: 38-07265
Orig. of
REV.
**
*A
ECN NO. Issue Date Change
Description of Change
Change from Spec number: 38-01107 to 38-07265
Added power-up requirements to operating conditions information.
Corrected the Switching Characteristics parameters to reflect the W152 device
110530
122863
130951
12/02/01
12/20/02
11/26/03
SZV
RBI
RGL
*B
and new characterization.
*C
*D
204201
231100
See ECN
See ECN
RGL
RGL
Corrected the Block Diagram
Fixed Typo in table 2.
Document #: 38-07265 Rev. *D
Page 8 of 8
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