CY23S05SXC-1T [CYPRESS]
PLL Based Clock Driver, 23S Series, 4 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, SOIC-8;
| 型号： | CY23S05SXC-1T |
| 厂家： | 
CYPRESS |
| 描述： | PLL Based Clock Driver, 23S Series, 4 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, SOIC-8 |
| 文件： | 总9页 (文件大小：303K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY23S09, CY23S05
Low Cost 3.3V Spread Aware
Zero Delay Buffer
MHz frequencies and have higher drive than the -1 devices. All
parts have on-chip PLLs that lock to an input clock on the REF
pin. The PLL feedback is on-chip and is obtained from the
CLKOUT pad.
Features
■
10 MHz to 100 and 133 MHz operating range, compatible
with CPU and PCI bus frequencies
The CY23S09 has two banks of four outputs each, which can be
controlled by the select inputs as shown in the Select Input
Decoding table on Select Input Decoding for CY23S09 on page
2. If all output clocks are not required, Bank B can be
three-stated. The select inputs also allow the input clock to be
directly applied to the outputs for chip and system testing
purposes.
■
■
Zero input-output propagation delay
Multiple low skew outputs
❐
❐
❐
❐
Output-output skew less than 250 ps
Device-device skew less than 700 ps
One input drives five outputs (CY23S05)
One input drives nine outputs, grouped as 4 + 4 + 1
(CY23S09)
The CY23S09 and CY23S05 PLLs enter a power down mode
when there are no rising edges on the REF input. In this state,
the outputs are three-stated and the PLL is turned off, resulting
in less than 12.0 μA of current draw (for commercial temperature
devices) and 25.0 μA (for industrial temperature devices). The
CY23S09 PLL shuts down in one additional case, as shown in
the Select Input Decoding for CY23S09 on page 2.
■
■
■
Less than 200 ps cycle-to-cycle jitter is compatible with
Pentium® based systems
Test mode to bypass PLL (CY23S09 only, see Select Input
Decoding for CY23S09 on page 2)
Available in space saving 16-pin, 150-mil SOIC, 4.4 mm
TSSOP, and 150-mil SSOP ( CY23S09) or 8-pin, 150-mil
SOIC package (CY23S05)
Multiple CY23S09 and CY23S05 devices can accept the same
input clock and distribute it. In this case, the skew between the
outputs of two devices is guaranteed to be less than 700 ps.
■
■
3.3V operation, advanced 0.65μ CMOS technology
All outputs have less than 200 ps of cycle-to-cycle jitter. The input
to output propagation delay on both devices is guaranteed to be
less than 350 ps; the output to output skew is guaranteed to be
less than 250 ps.
Spread Aware
Functional Description
The CY23S05 and CY23S09 is available in two different config-
urations, as shown in the Ordering Information on page 6. The
CY23S05-1 and CY23S09-1 is the base part. The CY23S05-1H
and CY23S09-1H is the high drive version of the -1, and its rise
and fall times are much faster than -1.
The CY23S09 is a low cost 3.3V zero delay buffer designed to
distribute high speed clocks and is available in a 16-pin SOIC
package. The CY23S05 is an 8-pin version of the CY23S09. It
accepts one reference input, and drives out five low skew clocks.
The -1H versions of each device operate at up to 100 and 133
Logic Block Diagram
Cypress Semiconductor Corporation
Document Number: 38-07296 Rev. *D
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised October 22, 2008
[+] Feedback
CY23S09, CY23S05
Select Input Decoding for CY23S09
S2
0
S1
0
CLOCK A1–A4
Three-state
Driven
CLOCK B1–B4
Three-state
Three-state
Driven
CLKOUT[1]
Driven
Output Source
PLL Shut-down
PLL
PLL
N
N
Y
N
0
1
Driven
1
0
Driven
Driven
Reference
PLL
1
1
Driven
Driven
Driven
Zero Delay and Skew Control
Spread Aware
All outputs must be uniformly loaded to achieve Zero Delay
between the input and output. Because the CLKOUT pin is the
internal feedback to the PLL, its relative loading can adjust the
input-output delay. This is shown in the above graph.
Many systems being designed now use a technology called
Spread Spectrum Frequency Timing Generation. Cypress is one
of the pioneers of SSFTG development and designed this
product so as not to filter off the Spread Spectrum feature of the
Reference input, assuming it exists. When a zero delay buffer is
not designed to pass the SS feature through, the result is a signif-
icant amount of tracking skew, which may cause problems in
systems requiring synchronization.
For applications requiring zero input-output delay, all outputs,
including CLKOUT, must be equally loaded. Even if CLKOUT is
not used, it must have a capacitive load equal to that on other
outputs, to obtain zero input-output delay. If input to output delay
adjustments are required, use the above graph to calculate
loading differences between the CLKOUT pin and other outputs.
For more details on Spread Spectrum timing technology, please
see the Cypress application note AN1278, EMI Suppression
Techniques with Spread Spectrum Frequency Timing Generator
(SSFTG) ICs.
For zero output-output skew, be sure to load all outputs equally.
For further information, refer to the application note “CY23S05
and CY23S09 as PCI and SDRAM Buffers.”
Pin Configurations
Figure 1. Pin Diagram - CY23S09
Figure 2. Pin Diagram - CY23S05
Note
1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output.
Document Number: 38-07296 Rev. *D
Page 2 of 9
[+] Feedback
CY23S09, CY23S05
Pin Description for CY23S09
Pin
1
Signal
Description
Input reference frequency, 5V tolerant input
REF[2]
CLKA1[3]
CLKA2[3]
VDD
2
Buffered clock output, bank A
Buffered clock output, bank A
3.3V supply
3
4
5
GND
Ground
6
CLKB1[3]
CLKB2[3]
S2[4]
Buffered clock output, bank B
Buffered clock output, bank B
Select input, bit 2
7
8
9
S1[4]
Select input, bit 1
10
11
12
13
14
15
16
CLKB3[3]
CLKB4[3]
GND
Buffered clock output, bank B
Buffered clock output, bank B
Ground
VDD
CLKA3[3]
CLKA4[3]
CLKOUT[3]
3.3V supply
Buffered clock output, bank A
Buffered clock output, bank A
Buffered output, internal feedback on this pin
Pin Description for CY23S05
Pin
1
Signal
Description
Input reference frequency, 5V tolerant input
Buffered clock output
REF[2]
CLK2[3]
CLK1[3]
GND
2
3
Buffered clock output
4
Ground
5
CLK3[3]
Buffered clock output
6
VDD
3.3V supply
7
CLK4[3]
Buffered clock output
8
CLKOUT[3]
Buffered clock output, internal feedback on this pin
Notes
2. Weak pull-down.
3. Weak pull-down on all outputs.
4. Weak pull-up on these inputs.
Document Number: 38-07296 Rev. *D
Page 3 of 9
[+] Feedback
CY23S09, CY23S05
Storage Temperature .................................–65
°
C to +150
°
°
°
C
C
C
Maximum Ratings
Maximum Soldering Temperature (10 seconds)......... 260
Junction Temperature................................................. 150
Static Discharge Voltage
Supply Voltage to Ground Potential................–0.5V to +7.0V
DC Input Voltage (Except REF) ............–0.5V to VDD + 0.5V
DC Input Voltage REF ............................................. −0.5V to 7V
(per MIL-STD-883, Method 3015) ...........................> 2,000V
Operating Conditions for CY23S05SC-XX and CY23S09SC-XX Commercial Temperature Devices[5]
Parameter
VDD
Description
Min
3.0
0
Max
3.6
70
30
10
7
Unit
V
Supply Voltage
TA
Operating Temperature (Ambient Temperature)
Load Capacitance, below 100 MHz
Load Capacitance, from 100 MHz to 133 MHz
Input Capacitance
°C
pF
pF
pF
CL
CL
CIN
Electrical Characteristics for CY23S05SC-XX and CY23S09SC-XX Commercial Temperature Devices
Parameter
Description
Input LOW Voltage[6]
Input HIGH Voltage[6]
Input LOW Current
Input HIGH Current
Output LOW Voltage[7]
Test Conditions
Min
Max
Unit
V
VIL
VIH
IIL
0.8
2.0
V
VIN = 0V
50.0
μA
μA
IIH
VIN = VDD
100.0
VOL
IOL = 8 mA (–1)
IOH = 12 mA (–1H)
0.4
V
VOH
Output HIGH Voltage[7]
IOH = –8 mA (–1)
IOL = –12 mA (–1H)
2.4
V
IDD (PD mode)
IDD
Power Down Supply Current REF = 0 MHz
Supply Current Unloaded outputs at 66.67 MHz,
SEL inputs at VDD
12.0
32.0
μA
mA
Switching Characteristics for CY23S05SC-1 and CY23S09SC-1 Commercial Temperature Devices [8]
Parameter
t1
Description
Test Conditions
Min
Typ
Max
Unit
Output Frequency
30 pF load
10 pF load
10
10
100
133.33
MHz
MHz
Duty Cycle[7] = t2 ÷ t1
Rise Time[7]
Fall Time[7]
Measured at 1.4V, Fout = 66.67 MHz
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
40.0
50.0
60.0
2.50
2.50
250
%
ns
ns
ps
ps
t3
t4
t5
t6
Output-to-Output Skew[7] All outputs equally loaded
Delay, REF Rising Edge to Measured at VDD/2
CLKOUT Rising Edge[7]
Device-to-Device Skew[7] Measured at VDD/2 on the CLKOUT pins
of devices
0
0
±350
t7
700
ps
tJ
Cycle-to-Cycle Jitter[7]
PLL Lock Time[7]
Measured at 66.67 MHz, loaded outputs
200
1.0
ps
tLOCK
Stable power supply, valid clock
presented on REF pin
ms
Notes
5. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power up. Power supply sequencing is NOT required.
6. REF input has a threshold voltage of V /2.
DD
7. Parameter is guaranteed by design and characterization. Not 100% tested in production.
8. All parameters specified with loaded outputs.
Document Number: 38-07296 Rev. *D
Page 4 of 9
[+] Feedback
CY23S09, CY23S05
Switching Characteristics for CY23S05SI-1H and CY23S09SI-1H Industrial Temperature Devices[8]
Parameter
t1
Description
Test Conditions
Min
Typ
Max
Unit
Output Frequency
30 pF load
10 pF load
10
10
100
133.33
MHz
MHz
Duty Cycle[7] = t2 ÷ t1
Duty Cycle[7] = t2 ÷ t1
Rise Time[7]
Measured at 1.4V, Fout = 66.67 MHz
Measured at 1.4V, Fout <50.0 MHz
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
40.0
45.0
50.0
50.0
60.0
55.0
1.50
1.50
250
%
%
t3
t4
t5
t6
ns
ns
ps
Fall Time[7]
Output-to-Output Skew[7] All outputs equally loaded
Delay, REF Rising Edge to Measured at VDD/2
CLKOUT Rising Edge[7]
Device-to-Device Skew[7] Measured at VDD/2 on the CLKOUT pins
of devices
0
0
±350
700
ps
ps
t7
t8
Output Slew Rate[7]
Measured between 0.8V and 2.0V using
Test Circuit #2
1
V/ns
ps
tJ
Cycle-to-Cycle Jitter[7]
PLL Lock Time[7]
Measured at 66.67 MHz, loaded outputs
200
1.0
tLOCK
Stable power supply, valid clock
presented on REF pin
ms
Switching Waveforms
Duty Cycle Timing
t
1
t
2
1.4V
1.4V
1.4V
All Outputs Rise/Fall Time
3.3V
0V
2.0V
OUTPUT
0.8V
2.0V
0.8V
t
3
t
4
Output-Output Skew
1.4V
OUTPUT
1.4V
OUTPUT
t
5
Input-Output Propagation Delay
V
DD/2
INPUT
VDD/2
OUTPUT
t
6
Document Number: 38-07296 Rev. *D
Page 5 of 9
[+] Feedback
CY23S09, CY23S05
Switching Waveforms continued
Device-Device Skew
VDD/2
CLKOUT, Device 1
VDD/2
CLKOUT, Device 2
t7
2309–8
Test Circuits
Test Circuit # 2
Test Circuit # 1
V
DD
OUTPUTS
V
1 kW
DD
0.1 μF
0.1 μF
CLK out
0.1 μF
0.1 μF
OUTPUTS
10 pF
1 kW
C
LOAD
V
DD
V
DD
GND
GND
GND
GND
For parameter t8 (output slew rate) on –1H devices
Ordering Information
Ordering Code
CY23S05SC-1
CY23S05SC-1H
CY23S09SC-1
CY23S09SC-1H
CY23S09ZC-1
Package Name
Package Type
Operating Range
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Status
S8
S8
8-pin 150-mil SOIC
8-pin 150-mil SOIC
16-pin 150-mil SOIC
16-pin 150-mil SOIC
16-pin 4.4 mm TSSOP
16-pin 4.4 mm TSSOP
16-pin 150-mil SSOP
16-pin 150-mil SSOP
Active
Obsolete
Obsolete
Obsolete
Obsolete
Obsolete
Obsolete
Obsolete
S16
S16
Z16
Z16
O16
O16
CY23S09ZC-1H
CY23S09OC-1
CY23S09OC-1H
Pb-Free
CY23S05SXC-1
CY23S05SXC-1H
CY23S09SXC-1
CY23S09SXC-1H
CY23S09ZXC-1
CY23S09ZXC-1H
CY23S09OXC-1
CY23S09OXC-1H
S8
S8
8-pin 150-mil SOIC
8-pin 150-mil SOIC
16-pin 150-mil SOIC
16-pin 150-mil SOIC
16-pin 4.4 mm TSSOP
16-pin 4.4 mm TSSOP
16-pin 150-mil SSOP
16-pin 150-mil SSOP
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Active
Active
S16
S16
Z16
Z16
O16
O16
Active
Active
Obsolete
Active
Obsolete
Obsolete
Document Number: 38-07296 Rev. *D
Page 6 of 9
[+] Feedback
CY23S09, CY23S05
Package Diagrams
Figure 3. 8-Pin (150-Mil) SOIC S8
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
0.150[3.810]
0.157[3.987]
RECTANGULAR ON MATRIX LEADFRAME
3. REFERENCE JEDEC MS-012
4. PACKAGE WEIGHT 0.07gms
0.230[5.842]
0.244[6.197]
PART #
S08.15 STANDARD PKG.
SZ08.15 LEAD FREE PKG.
5
8
0.189[4.800]
0.196[4.978]
0.010[0.254]
0.016[0.406]
X 45°
SEATING PLANE
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.0075[0.190]
0.0098[0.249]
0.004[0.102]
0.0098[0.249]
0°~8°
0.016[0.406]
0.035[0.889]
0.0138[0.350]
0.0192[0.487]
51-85066-*C
Figure 4. 16-Pin (150-Mil) SOIC S16.15
PIN 1 ID
8
1
DIMENSIONS IN INCHES[MM] MIN.
MAX.
REFERENCE JEDEC MS-012
PACKAGE WEIGHT 0.15gms
0.150[3.810]
0.157[3.987]
0.230[5.842]
0.244[6.197]
PART #
S16.15 STANDARD PKG.
SZ16.15 LEAD FREE PKG.
9
16
0.010[0.254]
0.016[0.406]
X 45°
0.386[9.804]
0.393[9.982]
SEATING PLANE
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.0075[0.190]
0.0098[0.249]
0.016[0.406]
0.035[0.889]
0°~8°
0.0138[0.350]
0.0192[0.487]
0.004[0.102]
0.0098[0.249]
51-85068-*B
Document Number: 38-07296 Rev. *D
Page 7 of 9
[+] Feedback
CY23S09, CY23S05
Package Diagrams continued
Figure 5. 16-Pin TSSOP 4.40 mm Body Z16.173
PIN 1 ID
DIMENSIONS IN MM[INCHES] MIN.
MAX.
1
REFERENCE JEDEC MO-153
6.25[0.246]
6.50[0.256]
PACKAGE WEIGHT 0.05 gms
4.30[0.169]
4.50[0.177]
PART #
Z16.173 STANDARD PKG.
ZZ16.173 LEAD FREE PKG.
16
0.65[0.025]
BSC.
0.25[0.010]
BSC
0.19[0.007]
0.30[0.012]
1.10[0.043] MAX.
GAUGE
PLANE
0°-8°
0.076[0.003]
0.50[0.020]
0.70[0.027]
0.05[0.002]
0.15[0.006]
0.85[0.033]
0.95[0.037]
0.09[[0.003]
0.20[0.008]
SEATING
PLANE
4.90[0.193]
5.10[0.200]
51-85091-*A
Figure 6. 16-Pin (150-Mil) QSOP Q1
51-85053-*B
Document Number: 38-07296 Rev. *D
Page 8 of 9
[+] Feedback
CY23S09, CY23S05
Document History Page
Document Title: CY23S09/CY23S05 Low Cost 3.3V Spread Aware Zero Delay Buffer
Document Number: 38-07296
Submission
Date
Orig. of
Change
Rev.
ECN No.
Description of Change
**
111147
111773
122885
267849
2595524
11/14/01
02/20/02
12/22/02
See ECN
10/23/08
DSG
CTK
RBI
Changed from spec number 38-01094 to 38-07296
Added 150-mil SSOP option
*A
*B
*C
*D
Added power-up requirements to Operating Conditions
Added Lead-Free devices
RGL
CXQ/PYRS Added device “Status” to Ordering Information
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
PSoC
PSoC Solutions
General
psoc.cypress.com
clocks.cypress.com
wireless.cypress.com
memory.cypress.com
image.cypress.com
psoc.cypress.com/solutions
psoc.cypress.com/low-power
psoc.cypress.com/precision-analog
psoc.cypress.com/lcd-drive
psoc.cypress.com/can
Clocks & Buffers
Wireless
Low Power/Low Voltage
Precision Analog
LCD Drive
Memories
Image Sensors
CAN 2.0b
USB
psoc.cypress.com/usb
© Cypress Semiconductor Corporation, 2001-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-07296 Rev. *D
Revised October 22, 2008
Page 9 of 9
Pentium is a registered trademark of Intel Corporation. Spread Aware is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the
trademarks of their respective holders.
[+] Feedback
相关型号：
©2020 ICPDF网 联系我们和版权申明