CY2283PVC-1_技术文档

PRELIMINARY

CY2283

Pentium®/II, K6, 6x86 100-MHz Clock Synthesizer/Driver for

Desktop PCs with ALI or VIA Chipsets, AGP and 3 DIMMs

SDRAM outputs in place of the CY2283 and can be placed in

Features

close proximity to the SDRAM modules.

• Mixed 2.5V and 3.3V operation

The CY2283 possesses power-down, CPU stop, and PCI stop

pins for power management control. These inputs are multi-

plexed with SDRAM clock outputs, and are selected when the

MODE pin is driven LOW. Additionally, the signals are synchro-

nized on-chip, and ensure glitch-free transitions on the out-

puts. When the CPU_STOP input is asserted, the CPU clock

outputs are driven LOW. When the PCI_STOP input is assert-

ed, the PCI clock outputs (except the free-running PCI clock)

are driven LOW. When the PWR_DWN pin is asserted, the

reference oscillator and PLLs are shut down, and all outputs

are driven LOW.

• Complete clock solution for Pentium® /II, Cyrix 6x86,

and AMD K6 processor-based motherboards

— Four CPU clocks at 2.5V or 3.3V

[1]

— Twelve 3.3V SDRAM clocks

— Five synchronous PCI clocks, one free-running

— One 3.3V 48 MHz USB clock

— One 3.3V Ref. clock at 14.318 MHz

— Two AGP clocks at 3.3V

• Support for ALI (-1 option) and VIA (-2 option)

2

• I C™ Serial Configuration Interface

• Full EMI control with factory-EPROM programmable

output drive and slew rate

• Factory-EPROM programmable CPU clock frequencies

for custom configurations

The CY2283 outputs are designed for low EMI emissions.

Controlled rise and fall times, unique output driver circuits and

factory-EPROM programmable output drive and slew-rate en-

able optimal configurations for EMI control.

• Power-down, CPU stop, and PCI stop pins

• Available in space-saving 48-pin SSOP package

CY2283 Selector Guide

Functional Description

The CY2283 is a clock Synthesizer/Driver for Pentium, Cyrix,

or AMD processor-based PCs using the ALI Aladdin V (-1 op-

tion) or VIA MVP3 (-2 option) chipset.

Clock Outputs

CPU (66.6, 75, 83.3, 100MHz)

SDRAM

-1 (ALI V) -2 (VIA MVP3)

4

[1]

12

[2]

The CY2283 outputs four CPU clocks at 2.5V or 3.3V. There

are five PCI clocks, running at 30 or 33.3 MHz. One of the PCI

clocks is free-running. Additionally, the part outputs twelve

3.3V SDRAM clocks , one 3.3V USB clock at 48 MHz, and

one 3.3V reference clock at 14.318 MHz. Finally, the part out-

puts two AGP clocks running at 66.66 MHz or 60 MHz.

PCI (30, 33.3 MHz)

USB (48MHz)

5

1

[1]

AGP (66.6, 60MHz)

Ref. (14.318 MHz)

CPU-PCI delay

2

1

2

1

2.5−5.5 ns

The CY2283 has the flexibility to work as either a one-chip or

as part of a two-chip clocking solution. In 100-MHz board de-

signs based on the ALI Aladdin V chipset, it is recommended

that the CY2283 be used with an external SDRAM buffer so-

lution such as the CY2318NZ or CY2314NZ. In this configura-

tion the SDRAM outputs on the CY2283 must be either turned

AGP clock

In phase

with PCI

In phase

with CPU

Notes:

1. SDRAM clocks available up to 83.3MHz. In 100-MHz designs based on the

ALI V chipset, an external CY231xNZ buffer should be used.

2. One free-running PCI clock

2

off using I C or left floating. The CY231xNZ family provides the

Pin Configuration (48 SSOP)

Logic Block Diagram

REF0 (14.318 MHz)

XTALIN

AV

DD

V

1

2

3

4

48

47

46

14.318

DDQ3

MHz

REF0

USBCLK

SEL1

OSC.

XTALOUT

V

SS

STOP

CPU

PLL

CPUCLK [0-3]

V_DDCPU

LOGIC

XTALIN

45

44

43

42

41

V

SS

5

6

7

XTALOUT

CPUCLK0

CPUCLK1

V

DDQ3

PCICLK_F

PCICLK0

DDCPU

SEL0

SEL1

SDRAM5/PWR_DWN

SDRAM [0-4],[8-11]

EPROM

CPUCLK2

CPUCLK3

8

V

SS

9

40

39

38

10

11

12

PCICLK1

PCICLK2

PCICLK3

SDRAM6/CPU_STOP

V

SS

MODE

SDRAM0

SDRAM1

V

37

36

35

34

Delay (-2 option)

13

AGP0

DDQ3

SDRAM7/PCI_STOP

AGP

SYS PLL

V

DDQ3

14

15

16

17

18

SDRAM2

SDRAM3

/1, /1.25, /1.5

Delay (-1 option)

/2

AGP1

V

33

32

31

30

29

28

27

26

25

SS

V

SS

SDRAM11

SDRAM10

SDRAM4

SDRAM5/PWR_DWN

STOP

LOGIC

PCI [0-3]

PCICLK_F

USBCLK

V

19

20

21

22

23

24

DDQ3

V

DDQ3

SDRAM9

SDRAM6/CPU_STOP

SDRAM7/PCI_STOP

SDRAM8

SERIAL

SCLK

V

SS

V

INTERFACE

CONTROL

LOGIC

SS

SDATA

SCLK

SEL0

SDATA

MODE

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

October 12, 1998

PRELIMINARY

CY2283

Pin Summary

Name

Pins

Description

V

6, 14, 19, 30, 36, 48 3.3V Digital voltage supply

DDQ3

42

1

CPU Digital voltage supply, 2.5V or 3.3V

Analog voltage supply, 3.3V

DDCPU

AV

DD

V

3, 9, 16, 22, 27, 33, Ground

39, 45

SS

[3]

XTALIN

XTALOUT

4

5

Reference crystal input

Reference crystal feedback

[3]

SDRAM7/ PCI_STOP 28

SDRAM6/CPU_STOP 29

SDRAM5/ PWR_DWN 31

SDRAM clock output. Also, active LOW control input to stop PCI clocks, enabled

when MODE is LOW.

SDRAM clock output. Also, active LOWcontrol input to stop CPU clocks, enabled

when MODE is LOW.

SDRAM clock output. Also, active LOW control input to power down device,

enabled when MODE is LOW.

SDRAM[0:4],[8:11]

38, 37, 35, 34, 32, SDRAM clock outputs

21, 20, 18, 17

SEL0

26

CPU frequency select input, bit 0 (see table below)

CPU clock outputs

SEL1

46

CPUCLK[0:3]

PCICLK[0:3]

PCICLK_F

AGP[0:1]

REF0

44, 43, 41, 40

8, 10, 11, 12

PCI clock outputs, at one-half the CPU frequency.

Free-running PCI clock output

7

13, 15

2

AGP clock outputs

3.3V Reference clock output

USBCLK

SDATA

47

23

24

25

USB Clock output

Serial data input for serial configuration port

Serial clock input for serial configuration port

Mode Select pin for enabling power management features

SCLK

MODE

Note:

3. For best accuracy, use a parallel-resonant crystal, C_LOAD= 18 pF.

Function Table

CPU/PCI

Ratio

CPUCLK[0:3]

SDRAM[0:11]

PCICLK[0:3]

PCICLK_F

SEL1 SEL0

AGP[0:1]

66.66 MHz

60.0 MHz

REF0

14.318 MHz

USBCLK

48 MHz

0

1

0

1

0

1

2.5

83.33 MHz

66.67 MHz

100.0 MHz

75.0 MHz

33.33 MHz

30.0 MHz

2

48 MHz

3.0

2.5

2

PRELIMINARY

CY2283

Actual Clock Frequency Values

CPU and PCI Clock Driver Strengths

Target

Frequency

(MHz)

Actual

Frequency

(MHz)

• Matched impedances on both rising and falling edges on

the output drivers

• Output impedance: 25Ω (typical) measured at 1.5V

Clock Output

CPUCLK

USBCLK

PPM

–2346

66.67

75.0

66.51

75.0

0

83.33

100.0

48.0

83.14

99.77

48.01

-2346

167

Power Management Logic^[4]- Active when MODE pin is held ‘LOW’

Other

PCICLK_F Clocks

CPU_STOP PCI_STOP PWR_DWN

CPUCLK

PCICLK

Low

Osc.

Stopped Off

PLLs

Off

X

0

1

X

0

1

0

1

0

1

Low

Stopped

Running

Low

Running Running Running

33/30 MHz

Low

66/75/83/100MHz

30/33.3 MHz

Serial Configuration Map

Byte 0: Functional and Frequency Select Clock

Register (1 = Enable, 0 = Disable)

• The Serial bits will be read by the clock driverin the following

order:

Bit Pin #

Bit 7 --

Bit 6 --

Bit 5 --

Bit 4 --

Bit 3 --

Bit 2 --

Description

(Reserved) drive to ‘0’

Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0

Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0

(Reserved) drive to ‘0’

Bit 1 Bit 0

.

Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0

• Reserved and unused bits should be programmed to “0”.

2

• I C Address for the CY2283 is:

Bit 1 --

Bit 0

A6

A5

A4

A3

A2

A1

A0

R/W

1

0

1 - Three-State

0 - N/A

1

0

1

0

1

----

1 - Testmode

0 - Normal Operation

Select Functions

Outputs

SDRAM

Functional Description

CPU

PCI, PCI_F

Hi-Z

TCLK/4

Ref

IOAPIC

Hi-Z

TCLK

USBCLK

Hi-Z

TCLK/2

AGP

Hi-Z

TCLK/2

Three-State

Hi-Z

[6]

[5]

Test Mode

TCLK/2

TCLK

Notes:

4. AGP clocks are free-running and stop only when the PWR_DWN pin is asserted. The frequency of the AGP clocks is as shown in the Function Table.

5. TCLK supplied on the XTALIN pin in Test Mode.

6. Valid only for SEL1=0.

3

PRELIMINARY

CY2283

Byte 1: CPU Active/Inactive Register

(1 = Active, 0 = Inactive), Default = Active

Byte 2: PCI Active/Inactive Register

(1 = Active, 0 = Inactive), Default = Active

Bit

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Pin #

47

Description

Bit

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Pin #

Description

(Reserved) drive to ‘0’

USBCLK

--

7

N/A

40

(Reserved) drive to ‘0’

PCICLK_F (Active/Inactive)

AGP1 (Active/Inactive)

(Reserved) drive to ‘0’

15

14

12

11

10

8

Not used - drive to ‘0’

AGP0 (Active/Inactive)

CPUCLK3 (Active/Inactive)

CPUCLK2 (Active/Inactive)

CPUCLK1 (Active/Inactive)

CPUCLK0 (Active/Inactive)

PCICLK3 (Active/Inactive)

PCICLK2 (Active/Inactive)

PCICLK1 (Active/Inactive)

PCICLK0 (Active/Inactive)

41

43

44

Byte 3: SDRAM Active/Inactive Register

(1 = Active, 0 = Inactive), Default = Active

Byte 4: SDRAM Active/Inactive Register

(1 = Active, 0 = Inactive), Default = Active

Bit Pin #

Bit 7 28

Bit 6 29

Bit 5 31

Bit 4 32

Bit 3 34

Bit 2 35

Bit 1 37

Bit 0 38

Description

SDRAM7 (Active/Inactive)

SDRAM6 (Active/Inactive)

SDRAM5 (Active/Inactive)

SDRAM4 (Active/Inactive)

SDRAM3 (Active/Inactive)

SDRAM2 (Active/Inactive)

SDRAM1 (Active/Inactive)

SDRAM0 (Active/Inactive)

Bit

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Pin #

N/A

Description

Not used - drive to ‘0’

N/A

17

Not used - drive to ‘0’

SDRAM11

18

SDRAM10

20

SDRAM9

21

SDRAM8

Byte 5: Peripheral Active/Inactive Register

(1 = Active, 0 = Inactive), Default = Active

Byte 6: Reserved, for future use

Bit

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Pin #

N/A

Description

(Reserved) drive to ‘0’

(Reserved), drive to ‘0’

(Reserved) drive to ‘0’

REF0 (Active/Inactive)

N/A

2

4

PRELIMINARY

CY2283

Storage Temperature (Non-Condensing) ... –65°C to +150°C

Max. Soldering Temperature (10 sec) ...................... +260°C

Junction Temperature............................................... +150°C

Package Power Dissipation .............................................. 1W

Static Discharge Voltage ........................................... >2000V

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Supply Voltage..................................................–0.5 to +7.0V

Input Voltage.............................................. –0.5V to V +0.5

DD

(per MIL-STD-883, Method 3015, like V pins tied together)

DD

Operating Conditions^[7]

Parameter

AV , V

Description

Analog and Digital Supply Voltage

Min.

Max.

Unit

V

3.135

3.465

DD DDQ3

V

CPU Supply Voltage

2.375

3.135

2.9

3.465

V

DDCPU

T

Operating Temperature, Ambient

0

70

°C

A

C

Max. Capacitive Load on

CPUCLK, USBCLK, IOAPIC

PCICLK, AGP, SDRAM

REF0

pF

L

10

20

30

45

f

Reference Frequency, Oscillator Nominal Value

14.318

MHz

(REF)

Electrical Characteristics Over the Operating Range

Parameter

Description

Test Conditions

Min. Max. Unit

V

High-level Input Voltage

Low-level Input Voltage

High-level Output Voltage

Except Crystal Inputs

2.0

V

IH

V

0.8

0.7

IL

2

I C inputs only

ILiic

OH

V

= V

= 2.375V

I

= 16 mA CPUCLK 2.0

= 18 mA IOAPIC

= 27 mA CPUCLK

= 29 mA IOAPIC

= 16 mA CPUCLK 2.4

= 36 mA SDRAM

= 32 mA PCICLK

= 26 mA USBCLK

= 36 mA REF0

DDCPU

DDQ2

OH

OL

OH

OL

V

Low-level Output Voltage

High-level Output Voltage

= V

= 2.375V

0.4

V

OL

V

, AV , V = 3.135V

DD DDCPU

OH

DDQ3

V

Low-level Output Voltage

V

, AV , V

= 3.135V

= 27 mA CPUCLK

= 29 mA SDRAM

= 26 mA PCICLK

= 21 mA USBCLK

= 29 mA REF0

0.4V

V

OL

DD DDCPU

I

Input High Current

Input Low Current

V

= V

DD

–10 +10 µA

10 µA

IH

IL

= 0V

IL

Output Leakage Current

Three-state

= 3.465V, V = 0 or V , Loaded Outputs,

–10 +10 µA

OZ

DD

[8]

Power Supply Current

V

300 mA

DD

IN

DD

CPU clocks = 66.67 MHz

[8]

I

Power Supply Current

V

= 3.465V, V = 0 or V , Unloaded Outputs

120 mA

DD

IN

DD

Power-down Current

Current draw in power-down state

500 µA

DDS

Notes:

7. Electrical parameters are guaranteed with these operating conditions.

8. Power supply current will vary with number of outputs that are running.

5

PRELIMINARY

CY2283

Switching Characteristics for CY2283-1^{[9, 10]}

Parameter

Output

All

Description

Test Conditions

Min. Typ. Max. Unit

[11]

t

Output Duty Cycle

t = t ÷ t

1B

45

50

55

%

1

2

1

1A

t

CPUCLK

CPU Clock Rising and

Falling Edge Rate

Between 0.4V and 2.0V, V

Between 0.4V and 2.4V, V

= 2.5V 0.75

= 3.3V

4.0

V/ns

DDCPU

AGP,

REF0

AGP, REF0 Clock Rising

and Falling Edge Rate

Between 0.4V and 2.4V

0.85

4.0

V/ns

ns

2

PCI

PCI Rising and Falling

Edge Rate

Between 0.4V and 2.4V

0.85

2

CPUCLK

CPU Clock Rise Time

CPU Clock Fall Time

CPU-CPU Clock Skew

Between 0.4V and 2.0V, V

Between 0.4V and 2.4V, V

= 2.5V 0.4

= 3.3V 0.5

2.13

2.67

3

DDCPU

Between 2.0V and 0.4V, V

Between 2.4V and 0.4V, V

= 2.5V 0.4

= 3.3V 0.5

2.13

2.67

ns

4

DDCPU

Measured at 1.25V, V

= 2.5V

100

3.5

500

ps

5

DDCPU

Measured at 1.5V, V

= 3.3V

DDCPU

CPUCLK, CPU-PCI Clock Skew

PCICLK

Measured at 1.25V for 2.5V clocks, and

at 1.5V for 3.3V clocks

2.5

5.5

ns

6

PCICLK,

PCICLK

PCI-PCI Clock Skew

PCI-AGP Clock Skew

Cycle-Cycle Clock Jitter

Measured at 1.5V

500

ps

8

PCICLK,

AGP

Measured at 1.5V

1,200

500

ps

9

CPUCLK

Measured at 1.25V for 2.5V clocks, and

at 1.5V for 3.3V clocks

ps

10

t

PCICLK

AGP

Cycle-Cycle Clock Jitter

Measured at 1.5V

750

800

3

ps

10

11

CPUCLK, Power-up Time

PCICLK,

AGP

CPU, PCI, AGP clock stabilization from

power-up

ms

Notes:

9. Guaranteed by Design and Characterization, not 100% tested in production.

10. Device characterized and parameters guaranteed with SDRAM outputs turned off. All other outputs at maximum load.

11. Duty cycle is measured at 1.5V when V_DD= 3.3V. When V_DDCPU= 2.5V, CPUCLK duty cycle is measured at 1.25V.

6

PRELIMINARY

CY2283

Switching Characteristics for CY2283-2

Parameter

Output

Description

Test Conditions

Min. Typ. Max. Unit

t

All

Output Duty Cycle

t = t ÷ t

1B

TBD TBD TBD

%

1

2

1

1A

CPUCLK

CPU Clock Rising and

Falling Edge Rate

Between 0.4V and 2.0V, V

Between 0.4V and 2.4V, V

= 2.5V TBD TBD TBD V/ns

= 3.3V

DDCPU

t

SDRAM,

SDRAM, AGP, REF0 Clock Between 0.4V and 2.4V

TBD TBD TBD V/ns

2

AGP, REF0

Rising and Falling Edge

Rate

t

PCI

PCI Rising and Falling

Edge Rate

Between 0.4V and 2.4V

TBD TBD TBD V/ns

2

CPUCLK

CPU Clock Rise Time

CPU Clock Fall Time

CPU-CPU Clock Skew

CPU-PCI Clock Skew

Between 0.4V and 2.0V, V

Between 0.4V and 2.4V, V

= 2.5V TBD TBD TBD

= 3.3V

ns

ps

ns

ps

3

DDCPU

Between 2.0V and 0.4V, V

Between 2.4V and 0.4V, V

= 2.5V TBD TBD TBD

= 3.3V

4

DDCPU

Measured at 1.25V, V

= 2.5V

DDCPU

TBD TBD TBD

5

Measured at 1.5V, V

= 3.3V

DDCPU

CPUCLK,

PCICLK

Measured at 1.25V for 2.5V clocks, and TBD TBD TBD

at 1.5V for 3.3V clocks

6

CPUCLK,

SDRAM

CPU-SDRAM Clock Skew Measured at 1.25V for 2.5V clocks, and TBD TBD TBD

at 1.5V for 3.3V clocks

7

PCICLK,

PCICLK

PCI-PCI Clock Skew

PCI-AGP Clock Skew

Cycle-Cycle Clock Jitter

Measured at 1.5V

TBD TBD TBD

8

PCICLK,

AGP

Measured at 1.5V

TBD TBD TBD

9

CPUCLK,

SDRAM

Measured at 1.25V for 2.5V clocks, and TBD TBD TBD

at 1.5V for 3.3V clocks

10

t

PCICLK

AGP

Cycle-Cycle Clock Jitter

Power-up Time

Measured at 1.5V

TBD TBD TBD

ps

10

11

CPUCLK,

PCICLK,

CPU, PCI, AGP, and SDRAM clock sta- TBD TBD TBD

bilization from power-up

ms

AGP,SDRAM

2

Timing Requirement for the I C Bus

Parameter

Description

Min.

0

Max.

Unit

t

SCLK Clock Frequency

100

kHz

µs

12

13

14

15

16

17

18

Time the bus must be free before a new transmission can start

Hold time start condition. After this period the first clock pulse is generated.

The LOW period of the clock

4.7

4

4.7

4

The HIGH period of the clock

Set-up time for start condition. (Only relevant for a repeated start condition.)

4.7

Hold time DATA

for CBUS compatible masters

for I C devices

5

0

2

t

DATA input set-up time

250

ns

µs

ns

µs

19

20

21

22

Rise time of both SDATA and SCLK inputs

Fall time of both SDATA and SCLK inputs

Set-up time for stop condition

1

300

4.0

7

PRELIMINARY

CY2283

Switching Waveforms

Duty Cycle Timing

t

1B

t

1A

OUTPUT

All Outputs Rise/Fall Time

V_DD

0V

OUTPUT

t

2

t

3

t

2

t

4

CPU-CPU Clock Skew

CPUCLK

t

5

CPU-SDRAM Clock Skew

CPUCLK

SDRAM

t

7

CPU-PCI Clock Skew

CPUCLK

PCICLK

t₆

PCI-PCI Clock Skew

PCICLK

t

8

PRELIMINARY

CY2283

Switching Waveforms (continued)

AGP-PCI Clock Skew

AGPCLK

PCICLK

t₉

[12, 13]

CPU_STOP

CPUCLK

(Internal)

PCICLK

(Internal)

PCICLK

(Free-Running)

CPU_STOP

CPUCLK

(External)

[14, 15]

PCI_STOP

CPUCLK

(Internal)

PCICLK

(Internal)

PCICLK

(Free-Running)

PCI_STOP

PCICLK

(External)

PWR_DOWN

CPUCLK

(Internal)

PCICLK

(Internal)

PWR_DWN

CPUCLK

(External)

PCICLK

(External)

VCO

Crystal

Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock.

2

Timing Requirements for the I C Bus

SDA

t

21

13

t

14

20

SCL

t

14

t

17

22

t

19

t

16

15

18

Notes:

12. CPUCLK on and CPUCLK off latency is 2 or 3 CPUCLK cycles.

13. CPU_STOP may be applied asynchronously. It is synchronized internally.

14. PCICLK on and PCICLK off latency is 1 rising edge of the external PCICLK.

15. PCI_STOP may be applied asynchronously. It is synchronized internally.

9

PRELIMINARY

CY2283

Application Circuit

Clock traces must be terminated with either series or parallel termination, as they are normally done

Summary

• A parallel-resonant crystal should be used as the reference to the clock generator. The operating frequency and C

of

LOAD

this crystal should be as specified in the data sheet. Optional trimming capacitors may be needed if a crystal with a different

is used. Footprints must be laid out for flexibility.

C

LOAD

• Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1 µF.

In some cases, smaller value capacitors may be required.

• The value ofthe series terminating resistor satisfies the following equation, where R

is the loaded characteristic impedance

trace

ofthe trace, R is theoutputimpedanceofthe clockgenerator(specified in the datasheet), and R

is theseries terminating

out

series

resistor.

R

> R

– R

trace out

series

• Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor

as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF.

• A Ferrite Bead may be used to isolate the Board V from the clock generator V island. Ensure that the Ferrite Bead offers

DD

greater than 50Ω impedance at the clock frequency, under loaded DC conditions. Please refer to the application note “Layout

and Termination Techniques for Cypress Clock Generators” for more details.

• If a Ferrite Bead is used, a 10 µF– 22 µF tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor

prevents power supply droop during current surges.

10

PRELIMINARY

CY2283

Test Circuit

V

DDQ3

1

48

0.1 µF

3

6

45

42

V

DDCPU

9

39

36

14

0.1 µF

16

19

33

30

0.1 µF

22

27

OUTPUTS

C

LOAD

Note: All Capacitors must be placed as close to the pins as is possible

Ordering Information

Package

Operating

Range

Ordering Code

CY2283PVC–1

CY2283PVC–2

Name

Package Type

48-Pin SSOP

O48

Commercial

O48

Document #: 38–00685–A

2

Intel and Pentium are registered trademarks of Intel Corporation. I C is a trademark of Philips Corporation.

11

PRELIMINARY

CY2283

Package Diagram

48-Lead Shrunk Small Outline Package O48

51-85061-B

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.


型号：	CY2283PVC-1
厂家：	CYPRESS
描述：	PentiumII, K6, 6x86 100-MHz Clock Synthesizer/Driver for Desktop PCs with ALI or VIA Chipsets, AGP and 3 DIMMs PentiumII ， K6 ， 6X86 100 MHz的时钟合成器/驱动器，用于台式电脑与ALI或VIA芯片组， AGP和3个DIMM内存模块晶体驱动器时钟发生器微控制器和处理器外围集成电路光电二极管电脑 PC
文件：	总12页 (文件大小：221K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY2283PVC-1 [CYPRESS]

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