CY2287_技术文档

CY2287

100-MHz Spread Spectrum Clock Synthesizer/Driver with

USB, Hublink, and SDRAM Support

Features

Benefits

• Mixed 2.5V and 3.3V Operation

Usable with Pentium II, K6, and 6x86 Processors

• Multiple output clocks at different frequencies

— Three CPU clocks at 2.5V, up to 100 MHz

— Nine 3.3V SDRAM clocks at 100 MHz

Single-chip main motherboard clock generator

— High-Speed Processor Support

— Supports Two 4-Clock SDRAM DIMMs

— Support for Six PCI Slots

— Eight synchronous PCI clocks at 33 MHz

— Two synchronous APIC clocks at 16.67 MHz or 33

MHz

— Synchronous to the CPU Clock

— Hublink Support

— Two 3V66 clocks at 66 MHz

— Two USB clocks at 48 MHz

— One reference clock at 14.318 MHz

— Universal Serial Bus Support

— Also used as an input strap to determine APIC frequency

• Spread Spectrum clocking

Enables reduction of EMI

— 31 kHz modulation frequency

— EPROM programmable percentage of spreading

— Default is –0.6%, which is recommended by Intel®

— Additional options of –0.25% and –0.4% available

• Power-down features

Supports mobile systems

2

• I C™ Interface

Dynamic output control

• Low skew and low jitter outputs

• Test Mode

Meets tight system timing requirements at high frequency

Enables ATE and “bed of nails” testing

Widely available, standard package enables lower cost

• 56-pin SSOP package

SSOP

Top View

Logic Block Diagram

V

SSAPIC

1

2

3

4

5

6

56

55

54

53

52

51

50

REF0/SEL33

REF0/SEL33 (14.318 MHz)

APIC0

APIC1

V

DDREF

XTAL_IN

XTAL_OUT

V

DDAPIC

CPU0

V

SSREF

CPU [0–2] (66/100 MHz)

SDRAM [0-8] (100 MHz)

V

SS3V66

DDCPU

CPU1

CPU2

3V66_0

3V66_1

7

49

48

47

46

45

44

43

8

XTALIN

14.318

MHz

OSC.

CPU

PLL

V

DD3V66

9

V

SSCPU

EPROM

Configurable

Logic

V

DDPCI

SSSDRAM

10

11

XTALOUT

PCI0

PCI1

SDRAM0

SDRAM1

12

13

PCI [0–7] (33MHz)

SEL0

SEL1

V

PCI2

DDSDRAM

EPROM

SDRAM2

SDRAM3

14

15

16

17

18

V

SSPCI

42

41

PCI3

APIC [0–1] (16.67/33MHz)

PCI4

V

SSSDRAM

SDRAM4

SDRAM5

40

39

38

37

36

35

34

V

SSPCI

PCI5

3V66 [0–1] (66MHz)

USB [0–1] (48MHz)

PWR_DWN

PCI6

PCI7

19

20

21

V

DDSDRAM

SDRAM6

SYS

PLL

SDRAM7

DDPCI

AV

DD

22

23

24

25

V

SSSDRAM

AV

SS

SDRAM8

V

33

32

31

SSUSB

USB0

USB1

DDUSB

DDSDRAM

SCLK

SERIAL INTERFACE

CONTROL LOGIC

PWRDWN

SCLK

SDATA

26

27

28

V

SDATA

SEL1

30

29

SEL0

Intel and Pentium are registered trademarks of Intel Corporation.

I²C is a trademark of Philips Corporation.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

June 23, 1999

CY2287

Pin Summary

Name

Pins

Description

REF/SEL33

1

3.3V 14.31818-MHz clock output and power-on external select strap op-

tion for APIC clock frequency.

Strap LOW: APIC = PCI/2

Strap HIGH: APIC = 33.3 MHz

[1]

XTAL_IN

3

14.31818-MHz crystal input

[1]

XTAL_OUT

4

14.31818-MHz crystal output

PCI [0–7]

3V66 [0–1]

USB [0–1]

SEL [0–1]

PWRDWN

11, 12, 13, 15, 16, 18, 19, 20

3.3V PCI clock outputs

7, 8

3.3V Fixed 66.67-MHz clock outputs

3.3V Fixed 48-MHz clock outputs

3.3V LVTTL compatible inputs for logic selection

25, 26

28, 29

32

3.3V LVTTL compatible input. Device enters powerdown mode when held

LOW

CPU [0–2]

49, 50, 52

2.5V 66.67-MHz or 100-MHz (selectable) host bus clock output

SDRAM [0–8]

APIC [0–1]

35, 36, 37, 39, 40, 42, 43, 45, 46 3.3V SDRAM clock outputs running 100 MHz

54, 55

2.5V APIC clock outputs running synchronous with PCI clock frequency.

Selectable 16.67 MHz or 33.3 MHz

2

SDATA

SCLK

30

I C compatible SDATA input

2

31

I C compatible SCLK input

V

2

3.3V Power supply for REF output

REF ground

DDREF

SSREF

SS3V66

DD3V66

DDPCI

SSPCI

5

6

3V66 Ground

9

3.3V Power supply for 3V66 outputs

3.3V Power supply for PCI outputs

PCI ground

10, 21

14, 17

AV

22

3.3V Analog power supply

Analog ground

DD

23

SS

V

24

USB ground

SSUSB

DDUSB

DDSDRAM

SSSDRAM

SSCPU

DDCPU

DDAPIC

SSAPIC

27

3.3V Power supply for USB outputs

3.3V Power supply for SDRAM outputs

SDRAM ground

33, 38, 44

35, 41, 47

48

51

53

56

CPU ground

2.5V Power supply for CPU outputs

2.5V Power supply for APIC outputs

APIC ground

Note:

1. For best accuracy, use a parallel-resonant crystal, C_LOAD= 18 pF. For crystals with different C_LOAD, please refer to the application note, “Crystal Oscillator

Topics.”

2

CY2287

Function Table

[4]

[5]

CPU

(MHz)

SDRAM

(MHz)

3V66

(MHz)

PCI

(MHz)

USB

(MHz)

REF

(MHz)

APIC

(MHz)

APIC

[2]

SEL2

SEL1 SEL0

(MHz)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Hi-Z

TCLK /2 TCLK/2

Hi-Z

[3]

TCLK/3

66.67

TCLK/8

33.33

TCLK/2

48

TCLK

TCLK/16

16.67

TCLK/8

33.33

66.67

100

14.318

48

66.67

100

48

66.67

100

48

[2]

Spread Spectrum

SEL2

SEL1

SEL0

Spread Spectrum Margin

X

0

1

0

X

0

1

0

X

1

0

1

0

1

X

0

1

0

1

0

1

N/A

–0.6%

–0.25%

–0.4%

Actual Clock Frequency Values

Target

Actual

Clock Output

CPUCLK

Frequency (MHz)

PPM

–5230

–5680

+167

66.67

100.0

48.0

66.288

CPUCLK

99.432

USBCLK

48.008

Notes:

2. Not a dedicated input pin. This selection must be addressed via I²C interface.

3. TCLK supplied on the XTALIN pin in Test Mode.

4. SEL33 = LOW (power-on latch input).

5. SEL33 = HIGH (power-on latch input).

3

CY2287

Serial Configuration Map

Byte 2: PCI Control Register

(1 = Enable, 0 = Disable)

Default = Enable (for Bit [1:7])

Default = Disable (for Bit 0)

• The Serial bits will be read by the clock driverin the following

order:

Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0

Bit Pin #

Bit 7 20

Bit 6 19

Bit 5 18

Bit 4 16

Bit 3 15

Bit 2 13

Bit 1 12

Bit 0 11

Description

Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0

.

PCI7

.

PCI6

Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0

PCI5

• Reserved and unused bits must be programmed to “0”.

• I C Address for the CY2287 is:

PCI4

2

PCI3

PCI2

A6

A5

A4

A3

A2

A1

A0

R/W

PCI1

1

0

1

0

1

0

Reserved

Byte 0: Spread Spectrum, USB, SDRAM8

Control Register

(1 = Enable, 0 = Disable)

Default = Enable (for Bit [0:2])

Default = Disable (for Bit [3:7])

Byte 3: Peripheral Control Register

(0 = Enable, 1 = Disable)

Default = Enable

Bit

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Pin #

Description

Bit Pin #

Bit 7 --

Bit 6 --

Bit 5 --

Bit4 --

Bit3 --

Bit2 26

Bit1 25

Bit0 49

Description

8

7

3V66_1

3V66_0

PCI0

Reserved

SEL2

11

34

54

55

50

52

SDRAM8

APIC1

APIC0

CPU1

Spread Spectrum (Default = Disable)

USB1

USB0

CPU2

CPU0

Byte 4: Reserved Register

(0 = Enable, 1 = Disable)

Default = Disable

Byte 1: SDRAM Control Register

(1 = Enable, 0 = Disable)

Default = Enable

Bit Pin #

Bit 7 --

Bit 6 --

Bit 5 --

Bit 4 --

Bit 3 --

Bit 2 --

Bit 1 --

Bit 0 --

Description

Reserved

Bit

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Pin #

36

Description

SDRAM7

SDRAM6

SDRAM5

SDRAM4

SDRAM3

SDRAM2

SDRAM1

SDRAM0

37

39

40

42

43

45

46

4

CY2287

Storage Temperature (Non-Condensing) ... –65°C to +150°C

Max. Soldering Temperature (10 sec) ...................... +260°C

Junction Temperature............................................... +150°C

Package Power Dissipation .............................................. 1W

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Supply Voltage..................................................–0.5 to +7.0V

Static Discharge Voltage

(per MIL-STD-883, Method 3015) ............................. >2000V

Input Voltage.............................................. –0.5V to V +0.5

DD

Operating Conditions Over Which Electrical Parameters are Guaranteed

Parameter Description

3.3V Supply Voltages

Min.

3.135

2.375

0

Max.

3.465

2.625

70

Unit

V

DD3.3V

DD2.5V

2.5V Supply Voltages

V

T

Operating Temperature, Ambient

°C

pF

A

C

Max. Capacitive Load on

CPU, USB, REF, APIC

SDRAM, PCI, 3V66

L

20

30

f

Reference Frequency, Oscillator Nominal Value

14.318

MHz

(REF)

Electrical Characteristics Over the Operating Range

Parameter

Description

Test Conditions

All inputs except SCLK/SDATA and crystal inputs

SCLK/SDATA

Min. Typ Max. Unit

[6]

V

High-level Input Voltage

2.0

0.7

V

IH

IL

V

DD

[6]

V

Low-level Input Voltage

All inputs except SCLK/SDATA and crystal inputs

SCLK/SDATA

0.8

0.3

+10

-60

–51

–100

-60

49

V

DD

I

Input High Current

0 < V < V

–10

–16

–15

–30

–16

19

µA

IH

IN

DD

Input Low Current

0 < V < V

µA

IL

IN

High-level Output Current

CPU

V

= 2.0V

= 2.4V

= 2.0V

= 0.4V

mA

OH

OL

USB, REF

SDRAM

PCI, 3V66

APIC

I

Low-level Output Current

CPU

mA

OL

USB, REF

SDRAM

PCI, 3V66

APIC

10

24

20

49

20

49

19

49

I

Output Leakage Current

Three-state

10

µA

OZ

2.5V Power Supply Current AV /V

= 3.465V, V

DD DD33

= 2.625V, F

= 100 MHz

100 mA

280 mA

DD2

DD DD33

DD25

CPU

3.3V Power Supply Current AV /V

DD3

DD DD33

CPU

[7]

2.5V Shutdown Current

3.3V Shutdown Current

AV /V

= 2.625V

<1

<9

500

µA

DDPD2

DDPD3

[7]

AV /V

= 3.465V, V

= 2.625V

DD25

DD DDQ3

Notes:

6. Crystal inputs have CMOS thresholds, nominally V_DD/2.

7. Tested @ 500 µA. Actual performance is much better. Call Cypress if tighter spec is required.

5

CY2287

CY2287 Switching Characteristics^[8]Over the Operating Range

Parameter

Output

Description

Test Conditions

Min.

45

Max.

Unit

%

[9]

t

All

Output Duty Cycle

Rising Edge Rate

Falling Edge Rate

CPU-CPU Skew

t

/(t + t )

1B

55

4.0

2.0

4.0

2.0

4.0

175

250

500

175

4.0

500

8.0

500

3.0

5.5

250

500

1000

3

1

1A 1A

CPU, APIC

USB, REF

PCI, 3V66

SDRAM

CPU, APIC

USB, REF

PCI, 3V66

SDRAM

CPU

Between 0.4V and 2.0V

Between 0.4V and 2.4V

Between 2.0V and 0.4V

Between 2.4V and 0.4V

Measured at 1.25V

1.0

0.5

1.0

0.5

1.0

V/ns

ps

2

3

4

SDRAM

APIC

SDRAM-SDRAM Skew

APIC-APIC Skew

PCI-PCI Skew

Measured at 1.5V

ps

4

Measured at 1.25V

ps

4

PCI

Measured at 1.5V

ps

4

3V66

3V66-3V66 Skew

3V66-PCI Clock Skew

APIC-PCI Clock Skew

Measured at 1.5V

ps

4

[10]

3V66, PCI

APIC, PCI

3V66 leads

1.5

7.0

ns

4

[10, 11]

Coincident every edge

ps

4

[10]

SDRAM, 3V66 SDRAM-3V66 Clock Skew Coincident every other 3V66 edge

ps

5

[10]

CPU, 3V66

CPU-3V66 Clock Skew

CPU leads

ns

6_66

Coincident every other 3V66 edge

ps

6_100

[10, 12]

CPU, SDRAM CPU-SDRAM Clock Skew

SDRAM leads

2.0

4.5

ns

7_66

[10]

CPU leads, measured every edge

ns

7_100

CPU

Cycle-Cycle Clock Jitter

Settle Time

Measured at 1.25V, t – t

ps

8

8A

8B

SDRAM

APIC

Measured at 1.5V, t – t

ps

8

8A

8B

Measured at 1.25V, t – t

ps

8

8A

8B

USB

Measured at 1.5V, t – t

8B

ps

8

8A

3V66

Measured at 1.5V, t – t

ps

8

8A

8B

REF

Measured at 1.5V, t – t

ps

8

8A

All Outputs

All clock stabilization from power-up

ms

STABLE

Notes:

8. All parameters specified with loaded outputs as follows: CPU, APIC, REF, USB = 12.5 pF: SDRAM, 3V66, PCI=20 pF.

9. Duty cycle is measured at 1.5V when V_DD= 3.3V. When V_DD= 2.5V, duty cycle is measured at 1.25V.

10. Measured at 1.25V for 2.5V clocks and 1.5V for 3.3V clocks.

11. Coincident every other APIC edge if APIC running at 16 MHz.

12. Measured every third CPU edge.

6

CY2287

Switching Waveforms

Duty Cycle Timing

t

1B

t

1A

All Outputs Rise/Fall Time

V_DD

0V

OUTPUT

t

2

t

3

CLK-CLK Output Skew

CLKA

CLKB

t

4

Cycle-Cycle Clock Jitter

t_8A

t_8B

CLK

[13, 14, 15]

PWR_DOWN

CPUCLK

Peripheral

Clocks

PWR_DWN

VCO

Crystal

Notes:

13. Once the PWR_DWN signal is sampled LOW for two consecutive rising edges of CPU clock, clocks of interest will be held LOW on the next HIGH-to-LOW

transition.

14. Waveforms are not to scale.

15. Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock.

7

CY2287

Switching Waveforms (continued)

CLK-CLK Output Skew (CPU @ 66 MHz)

10 ns

20 ns

30 ns

40 ns

0 ns

CPU 66 MHz

SDRAM 100 MHz

3V66 66 MHz

t₅

SDRAM to 3V66 Skew, SDRAM leads 3V66 by 0.0 ns (500-ps window)

CLK-CLK Output Skew (CPU @ 66 MHz)

10 ns

20 ns

30 ns

40 ns

0 ns

CPU 66 MHz

t_{6_66}

3V66 66 MHz

SDRAM 100 MHz

CPU to 3V66 Skew, CPU leads 3V66 by 7.5ns (500-ps window)

CLK-CLK Output Skew (CPU @ 66 MHz)

10 ns

20 ns

30 ns

40 ns

0 ns

CPU 66 MHz

t_{7_66}

SDRAM 100 MHz

3V66 66 MHz

CPU to SDRAM Skew, SDRAM leads CPU by 2.5 ns (500-ps window)

8

CY2287

Switching Waveforms (continued)

CLK-CLK Output Skew (CPU @ 100 MHz)

10 ns

20 ns

30 ns

40 ns

0 ns

CPU 100 MHz

SDRAM 100 MHz

3V66 66 MHz

t₅

SDRAM to 3V66 Skew, SDRAM leads 3V66 by 0.0 ns (500-ps window)

CLK-CLK Output Skew (CPU @ 100 MHz)

10 ns

20 ns

30 ns

40 ns

0 ns

t_{6_100}

CPU 100 MHz

3V66 66 MHz

SDRAM 100 MHz

CPU to 3V66 Skew, CPU leads 3V66 by 0.0 ns (500-ps window)

CLK-CLK Output Skew (CPU @ 100 MHz)

10 ns

20 ns

30 ns

40 ns

0 ns

t_{7_100}

CPU 100 MHz

SDRAM 100 MHz

3V66 66 MHz

CPU to SRAM Skew, CPU leads SDRAM by 5.0 ns (500-ps window)

9

CY2287

Switching Waveforms (continued)

Window Measurement Clarification

500-ps window

Earliest of Group A

1.5V

Group A

1.5V

Group B

Latest of Group B

Example of SDRAM to 3V66 Skew Measurement (CPU @ 66 or 100 MHz)

SDRAM leads 3V66 by 0.0 ns (500-ps window)

Window Measurement Clarification

8.0-ns window (max)

7.0-ns window (min)

Latest of CPU Group

Earliest of CPU Group

1.25V

Earliest of 3V66 Group

CPU Group

1.5V

3V66 Group

Latest of 3V66 Group

Example of CPU to 3V66 Skew Measurement (CPU @ 66 MHz)

CPU leads 3V66 by 7.5 ns (500-ps window)

10

CY2287

Switching Waveforms (continued)

SPREAD SPECTRUM CLOCKING

Min. Max. Unit

Description

Output

Modulation Frequency

Down Spread Margin at the Fundamental Frequency

CPU, PCI, SDRAM, APIC, 3V66

kHz

%

30.0

33.0

CPU, PCI, SDRAM, APIC, 3V66

–0.25

–0.6

Spread Spectrum Disabled

Spread Spectrum Enabled

Selectable Downspread Margins

–0.25%

–0.4%

–0.6%

Frequency (MHz)

11

CY2287

Application Information

Clock traces must be terminated with either series or parallel termination, as they are normally done.

Application Circuit

XTALIN

XTALOUT

Cx

Rs

SEL0

SEL1

SEL0

SEL1

CPU

SDRAM

PCI

CPU

SDRAM

PCI

3V66

PWR_DWN

HUBLINK

APIC

REF

USB

REF

USB

3.3V VDD

2.5V VDD

VDD3.3V

Cd

Ct

VDD2.5V

VSS

CY2287-1 56 Pin SSOP

Cd = Decoupling Capacitors (NOTE: May use 0.1µF, but value will vary with frequency of operation and output current)

Ct = Optional EMI-Reducing Capacitors

Cx = Optional Load Matching Capacitors

Rs = Termination Resistor

Summary

• A parallel-resonant crystal should be used as the reference to the clock generator. The operating frequency and C

of

LOAD

this crystal should be as specified in the data sheet. Optional trimming capacitors may be needed if a crystal with a different

is used. Footprints must be laid out for flexibility.

C

LOAD

• Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 2.2 nF.

In some cases, smaller value capacitors may be required.

• The value ofthe series terminating resistor satisfies the following equation, where R

is the loaded characteristic impedance

trace

of the trace, R is the output impedance of the clock generator (CPU/APIC = 29 Ohm, USB/REF = 40 Ohm, SDRAM (3.3V)=

out

16 Ohm, PCI/3V66 = 30 Ohm - all nominal driver output impedances), and R

is the series terminating resistor.

series

R

> R

– R

series

trace out

• Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor

as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF.

• A Ferrite Bead may be used to isolate the Board V from the clock generator V island. Ensure that the Ferrite Bead offers

DD

greater than 50Ω impedance at the clock frequency, under loaded DC conditions. Please refer to the application note “Layout

and Termination Techniques for Cypress Clock Generators” for more details.

• If a Ferrite Bead is used, a 10 µF– 22 µF tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor

prevents power supply droop during current surges.

12

cy2287: May 26, 1998

Revision: June 23, 1999

CY2287

Test Circuit

V

DD3.3V

5, 6, 14, 17, 23, 24, 34, 41, 47, 48, 56

2, 9, 10, 21, 22, 27, 32, 38, 44

CY2287

V

DD2.5V

OUTPUTS

C

LOAD

51, 53

Note: Each supply pin must have an individual decoupling capacitor.

Note: All capacitors must be placed as close to the pins as is physically possible.

Ordering Information

Package

Name

Operating

Range

Ordering Code

Package Type

56-Pin SSOP

CY2287PVC–1

O56

Commercial

Document #: 38–00711–A

Package Diagram

56-Lead Shrunk Small Outline Package O56

51-85062-B

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.


型号：	CY2287
厂家：	CYPRESS
描述：	100-MHz Spread Spectrum Clock Synthesizer/Driver with USB, Hublink, and SDRAM Support 100 - MHz的扩频时钟合成器/驱动器，带有USB ， Hublink和SDRAM支持驱动器动态存储器时钟
文件：	总13页 (文件大小：151K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY2287 [CYPRESS]

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