CY2285PVC-2T [CYPRESS]
Processor Specific Clock Generator, 100MHz, CMOS, PDSO28, 0.210 INCH, SSOP-28;
| 型号： | CY2285PVC-2T |
| 厂家： | 
CYPRESS |
| 描述： | Processor Specific Clock Generator, 100MHz, CMOS, PDSO28, 0.210 INCH, SSOP-28 光电二极管 |
| 文件： | 总9页 (文件大小：120K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY2285
100-MHz Pentium®II Clock Synthesizer/Driver
with Spread Spectrum for Mobile PCs
The CY2285 possesses power-down, CPU stop, and PCI stop
pins for power management control. The signals are synchro-
nized on-chip, and ensure glitch-free transitions on the out-
Features
Mixed 2.5V and 3.3V operation
•
•
puts. When the CPU_STOP input is asserted, the CPU clock
outputs are driven LOW. When the PCI_STOP input is assert-
ed, the PCI clock outputs (except the free-running PCI clock)
are driven LOW. When the PWR_DWN pin is asserted, the
reference oscillator and PLLs are shut down, and all outputs
are driven LOW.
Complete clock solution for Pentium® II, and other sim-
ilar processor-based motherboards
— Two CPU clocks at 2.5V up to 100 MHz
— Six synchronous PCI clocks, one free-running
— Two 3.3V Reference clocks at 14.318 MHz
— One 3.3V USB clock running at 48 MHz
— One 3.3V USB/IO clock running at 48 MHz/24 MHz
The CY2285-2 features an early PCI clock which leads the
other PCI clocks by 1–4 ns. The CY2285-2 also features a
DIV4 pin which allows for dynamic shifting of CPU and PCI
clocks from the default frequency to the default/4.
• Spread Spectrum clocking for EMI control
• 1.5–4.0 ns delay between CPU and PCI clocks
Power-down, CPU stop and PCI stop pins
CY2285 Selector Guide
•
•
Clock Outputs
CY2285-1
CY2285-2
CY2285-3
Low skew outputs, 175 ps between CPU clocks
≤
• Early PCI clock leads PCI by 1–4 ns (-2 option)
• DIV4 allows dynamic shifting of CPU and PCI clocks
from the default frequency to default/4 (-2 option)
CPU (66,
100 MHz)
2
2
2
[1]
[1, 2]
[1]
PCI (CPU/2,
CPU/3 MHz)
6
7
6
Factory-EPROM programmable output drive and slew
rate for EMI customization
•
Ref. (14.318 MHz)
USB (48 MHz)
2
1
1
2
1
1
1
1
• Available in space-saving 28-pin SSOP package
Functional Description
USB/IO (48
MHz/24 MHz se-
lectable)
N/A
The CY2285 is a clock synthesizer/driver for Pentium II, or
other similar processor-based mobile PCs requiring up to
100-MHz support. The CY2285 outputs two CPU clocks at
2.5V. There are six PCI clocks, running at one-half or one-third
the CPU clock frequency of 66.6 MHz and 100 MHz respec-
tively. One of the PCI clocks is free-running. Additionally, the
part outputs two 3.3V reference clocks at 14.318 MHz.
CPU-PCI delay
EPCI-PCI delay
Spread Spectrum
1.5–4.0 ns
N/A
1.5–4.0 ns
1.0–4.0 ns
–0.6%
1.5–4.0 ns
N/A
–0.6%
–0.6%
Downspread Downspread Downspread
The CY2285 provides incorporates the Intel®-defined spread
spectrum features. It provides a –0.6% downspread on the
CPU and PCI clocks, which can help reduce EMI in certain
high-speed systems.
Notes:
1. One free-running PCI clock.
2. One early PCI clock.
SPREAD (-2,-3 option)
Logic Block Diagram
REF0/SPREAD
REF0 (-2 option)
DIV4
REF1/SEL48
REF1 (-2,-3 option)
XTALIN
14.318
MHz
OSC.
VDDREF
XTALOUT
STOP
LOGIC
CPU
PLL
/4
CPUCLK [0–1]
VDDCPU
Divider
Delay
PWR_DWN
EPCICLK (-2 option)
VDDPCI
EPROM
STOP
LOGIC
PCICLK [1-5]
VDDPCI
CPU_STOP
PCI_STOP
PCICLK_F
VDDPCI
SYS
PLL
USBCLK
VDD48
USB_IOCLK/TS (-1 option)
USBCLK/SEL100/66 (-2 option)
VDD48
Intel and Pentium are registered trademarks of Intel Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
May 18, 2000
CY2285
Pin Configurations
SSOP
Top View
SSOP
Top View
SSOP
Top View
REF0
V
DDREF
V
V
1
2
3
4
28
27
26
25
24
23
22
21
V
SSREF
1
2
3
4
5
6
28
DDREF
V
DDREF
SSREF
1
2
3
4
28
XTAL_IN
XTAL_IN
REF1
27
26
25
24
23
22
21
REF1/SEL48
XTAL_IN
27
26
25
24
23
22
21
REF1/SEL48
SPREAD
SPREAD
XTAL_OUT
PCICLK_F
XTAL_OUT
PCICLK_F
XTAL_OUT
PCICLK_F
REF0/SPREAD
V
V
DDCPU
DDCPU
V
DDCPU
PCICLK1
PCICLK2
PCICLK1
PCICLK2
5
6
7
8
9
CPUCLK0
CPUCLK1
CPUCLK0
CPUCLK1
PCICLK1
PCICLK2
5
6
CPUCLK0
CPUCLK1
V
V
SSPCI
V
SSPCI
V
7
V
SSCPU
SSPCI
7
SSCPU
V
V
SSCPU
V
V
DDPCI
V
DDPCI
V
8
V
SSCORE
DDPCI
8
SSCORE
SSCORE
PCICLK3
PCICLK3
PCICLK4
PCICLK5
20
PCI_STOP
9
20
19
18
PCICLK3
PCICLK4
PCICLK5
PCI_STOP
9
20
19
18
PCI_STOP
PCICLK4
PCICLK5
EPCICLK
10
11
12
19
18
10
11
12
V
10
11
12
V
DDCORE
V
DDCORE
DDCORE
CPU_STOP
PWRDWN
DIV4
CPU_STOP
PWRDWN
SEL100
CPU_STOP
PWRDWN
SEL100
V
V
DD48
17
16
15
DD48
17
16
15
17
16
15
13
14
V
13
14
USBCLK
DD48
13
14
USBCLK
USB_IOCLK/TS
USBCLK/SEL100/66
V
USB_IOCLK/TS
V
SS48
V
SS48
SS48
Pin Summary: CY2285-1, CY2285-3
Name
Pins
Description
3.3V Power supply voltage
V
8, 12, 19, 28
DD
V
V
25
2.5V Power supply for CPU clocks
Ground
DDCPU
1, 7, 15, 21, 22
SS
[3]
XTALIN
2
Reference crystal input
Reference crystal feedback
[3]
XTALOUT
3
PCI_STOP
CPU_STOP
PWR_DWN
SEL100
20
18
17
16
Active LOW control input to stop PCI clocks
Active LOW control input to stop CPU clocks
Active LOW control input to power down device
Select for enabling 100-MHz or 66-MHz CPU clock
HIGH = 100 MHz, LOW = 66 MHz
CPUCLK[0:1]
PCICLK[1:5]
PCICLK_F
23, 24
2.5V CPU clock outputs
5, 6, 9, 10, 11
4
3.3V PCI clock outputs
3.3V Free-running PCI clock output
REF0/SPREAD
26 (-1 option)
3.3V 14.318-MHz reference clock output and power-on spread spectrum
enable strap option.
Strap LOW = Spread Spectrum enable
Strap HIGH = Spread Spectrum disable
SPREAD
26 (-3 option)
27
Active LOW control input to enable spread spectrum
REF1/SEL48
3.3V 14.318-MHz reference clock output and power-on 48-/24-MHz se-
lect strap option.
Strap LOW = 48 MHz on pin14
Strap HIGH = 24 MHz on pin14
USBCLK
13
14
3.3V 48-MHz USB clock output
USB_IOCLK/TS
3.3V 48-MHz or 24-MHz output and three-state strapping option.
Strap LOW = Enter three-state mode for testing
Strap HIGH = Normal Operation
Note:
3. For best accuracy, use a parallel-resonant crystal, CLOAD = 18 pF.
2
CY2285
Pin Summary: CY2285-2
Name
Pins
Description
V
V
V
8, 13, 19, 28
3.3V Power supply
DD
25
2.5V Power supply
DDCPU
SS
7, 15, 21, 22
Ground
[3]
XTALIN
XTALOUT
2
Reference crystal input
[3]
3
Reference crystal feedback
Active LOW control input to stop PCI clocks
Active LOW control input to stop CPU clocks
Active LOW control input to power down device
PCI_STOP
CPU_STOP
PWR_DWN
DIV4
20
18
17
16
Active LOW control input to enable divide-by-four option on
CPU and PCI clocks
CPUCLK[0:1]
PCICLK[1:5]
PCICLK_F
EPCICLK
23, 24
2.5V CPU clock outputs
5, 6, 9, 10, 11
3.3V PCI clock outputs
4
3.3V Free-running PCI clock output
3.3V Early PCI clock output (Not Free-running)
3.3V 14.318-MHz reference clock output
3.3V 14.318-MHz reference clock output
12
1
REF0
REF1
27
14
USBCLK/SEL100/66
3.3V 48-MHz USB clock output or select input and frequency
select strap option (use 10-kΩ external strap resistor)
Strap LOW = 66.6-MHz CPU Frequency
Strap HIGH = 100-MHz CPU Frequency
SPREAD
26
Active LOW control input to enable Spread Spectrum
Actual Clock Frequency Values
Target Frequency Actual Frequency
(MHz) (MHz)
Clock Output
CPUCLK
PPM
–240
66.67
100
48
66.654
CPUCLK
99.77
–2300
+167
USB 48-MHz
48.008
Power Management Logic
Other
CPU_STOP PCI_STOP
PWR_DWN
CPUCLK
Low
PCICLK
Low
PCICLK_F Clocks
Osc.
Off
PLLs
Off
X
X
0
1
0
1
0
1
1
1
1
Low
Low
0
0
1
1
Low
Low
Running
Running
Running
Running
Running Running Running
Running Running Running
Running Running Running
Running Running Running
Low
Running
Low
Running
Running
Running
3
CY2285
Function Table: CY2285-1
PCICLK[1:5],
[4]
[4]
[4]
SEL100 SEL48
TS
0
SPREAD
CPUCLK[0:1] PCICLK_F
USB_IOCLK USBCLK REFCLK [0-1]
X
0
0
X
1
0
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
1
1 (no spread)
66.6 MHz
66.6 MHz
33.3 MHz
33.3 MHz
24 MHz
48 MHz
48 MHz
48 MHz
14.318 MHz
14.318 MHz
1
0 (–0.6%
downspread)
1
1
1
0
1
1
1 (no spread)
100 MHz
100 MHz
33.3 MHz
33.3 MHz
24 MHz
48 MHz
48 MHz
48 MHz
14.318 MHz
14.318 MHz
0 (–0.6%
downspread)
Function Table: CY2285-2
PCICLK[1:5],
PCICLK_F,
EPCICLK
[4]
SEL100/66
SPREAD
DIV4
CPUCLK [0:1]
USBCLK
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
REFCLK[0:1]
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
0
0
1
1
0
0
1
1
0 (–0.6% downspread)
1 (no spread)
1
1
1
1
0
0
0
0
66.67 MHz
66.67 MHz
100 MHz
33.3 MHz
33.3 MHz
33.3 MHz
33.3 MHz
8.33 MHz
8.33 MHz
8.33 MHz
8.33 MHz
0 (–0.6% downspread)
1 (no spread)
100 MHz
0 (–0.6% downspread)
1 (no spread)
16.67 MHz
16.67 MHz
25.0 MHz
25.0 MHz
0 (–0.6% downspread)
1 (no spread)
Function Table: CY2285-3
PCICLK[1:5],
CPUCLK[0:1] PCICLK_F
[4]
[4]
[4]
SEL100 SEL48
TS
0
SPREAD
USB_IOCLK USBCLK REFCLK1
X
0
0
X
1
0
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
1
1 (no spread)
66.6 MHz
66.6 MHz
33.3 MHz
33.3 MHz
24 MHz
48 MHz
48 MHz
48 MHz
14.318 MHz
14.318 MHz
1
0 (–0.6%
downspread)
1
1
1
0
1
1
1 (no spread)
100 MHz
100 MHz
33.3 MHz
33.3 MHz
24 MHz
48 MHz
48 MHz
48 MHz
14.318 MHz
14.318 MHz
0 (–0.6%
downspread)
Note:
4. Power-on strap option.
4
CY2285
Storage Temperature (Non-Condensing) ... –65°C to +150°C
Max. Soldering Temperature (10 sec) ...................... +260°C
Junction Temperature............................................... +150°C
Static Discharge Voltage ........................................... >2000V
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Supply Voltage..................................................–0.5 to +7.0V
(per MIL-STD-883, Method 3015, like V pins tied together)
DD
Input Voltage.............................................. –0.5V to V +0.5
DD
Operating Conditions[5]
Parameter
Description
Analog and Digital 3.3V Supply Voltage
CPU Supply Voltage
Min.
3.135
2.375
0
Max.
3.465
2.625
70
Unit
V
V
V
DD
DDCPU
V
T
Operating Temperature, Ambient
°C
pF
A
C
Max. Capacitive Load on
L
CPUCLK
PCICLK
REF
20
30
35
f
Reference Frequency, Oscillator Nominal Value
14.318
14.318
MHz
(REF)
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min. Max. Unit
[6]
[6]
V
High-level Input Voltage
Low-level Input Voltage
High-level Output Voltage
Low-level Output Voltage
High-level Output Voltage
Except Crystal Inputs
Except Crystal Inputs
2.0
V
V
V
V
V
IH
V
V
V
V
0.8
0.4
IL
V
V
V
= 2.375V
= 2.375V
I
I
I
I
I
I
I
= 12 mA
= 12 mA
CPUCLK 2.0
CPUCLK
OH
OL
OH
DDCPU
DDCPU
OH
OL
OH
OH
OH
OL
OL
, AV , V
= 3.135V
= 14.5 mA PCICLK
2.4
DDPCI
DD DDREF
= 16 mA
= 36 mA
REF
REF
[7]
V
Low-level Output Voltage
V
, AV , V
= 3.135V
= 9.4 mA PCICLK
0.4V
V
OL
DDPCI
DD DDREF
= 9 mA
REF
REF
[7]
I
= 29 mA
OL
I
I
I
I
Input High Current
Input Low Current
V
V
= V
–10 +10 µA
10 µA
–10 +10 µA
= 2.625V, V = 0 or V , Loaded Outputs, CPU = 66.6 MHz 70 mA
IN DD
IH
IH
IL
DD
= 0V
IL
Output Leakage Current Three-state
OZ
Power Supply Current for
2.5V clocks
V
V
V
DD25
DDCPU
I
I
I
Power Supply Current for
2.5V clocks
= 2.625V, V = 0 or V , Loaded Outputs, CPU = 100 MHz
100 mA
170 mA
500 µA
DD25
DD33
DDS
DDCPU
IN
DD
Power Supply Current for
3.3V clocks
= 3.465V, V = 0 or V , Loaded Outputs
IN DD
DD
Powerdown Current
Current draw in powerdown state
Notes:
5. Electrical parameters are guaranteed with these operating conditions.
6. Crystal Inputs have CMOS thresholds, nominally VDD/2.
7. CY2285-2 option only.
5
CY2285
Switching Characteristics[8] Over the Operating Range
Parameter
Output
All
Description
Test Conditions
Min. Typ. Max.
Unit
%
[9]
t
Output Duty Cycle
t = t ÷ t
1B
45
50
55
1
2
1
1A
t
t
t
CPUCLK
PCICLK
REF
CPU Clock Rising and
Falling Edge Rate
Between 0.4V and 2.0V
Between 0.4V and 2.4V
Between 0.4V and 2.4V
1.0
4.0
V/ns
PCI Clock Rising and
Falling Edge Rate
1.0
0.5
4.0
2.0
V/ns
V/ns
2
2
REF Clock Rising and
Falling Edge Rate
t
t
t
t
CPUCLK
CPUCLK
CPUCLK
CPU Clock Rise Time
CPU Clock Fall Time
CPU-CPU Clock Skew
Between 0.4V and 2.0V
Between 2.0V and 0.4V
Measured at 1.25V
0.4
0.4
1.6
1.6
175
4.0
ns
ns
ps
ns
3
4
5
6
100
CPUCLK, CPU-PCI Clock Skew
PCICLK
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
1.5
1.0
t
t
PCICLK,
PCICLK
PCI-PCI Clock Skew
Measured at 1.5V
250
4.0
ps
ns
7
7
[7]
EPCICLK, EPCI-PCI Clock Skew
PCICLK
Measured at 1.5V
t
t
t
CPUCLK
PCICLK
Cycle-Cycle Clock Jitter Measured at 1.25V
Cycle-Cycle Clock Jitter Measured at 1.5V
700
500
3
ps
ps
10
11
12
CPUCLK, Power-up Time
PCICLK
CPU and PCI clock stabilization from
power-up
ms
t
CPUCLK, /4 Frequency Slew
Time for CPU, EPCI, and PCI clock
frequency to change from f to f/4 after
select input change
10
25
cycles
13
[7]
PCICLK
Time
Notes:
8. All parameters specified with loaded outputs.
9. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V.
6
CY2285
Switching Waveforms
Duty Cycle Timing
t
1B
t
1A
OUTPUT
All Outputs Rise/Fall Time
VDD
0V
OUTPUT
t
2
t
3
t
2
t
4
CPU-CPU Clock Skew
CPUCLK
CPUCLK
t
5
CPU-PCI Clock Skew
CPUCLK
PCICLK
t6
PCI/EPCI-PCI Clock Skew
PCI/EPCICLK
PCICLK
t
7
CPU_STOP
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK
(Free-Running)
CPU_STOP
CPUCLK
(External)
7
CY2285
Switching Waveforms (continued)
PCI_STOP
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK
(Free-Running)
PCI_STOP
PCICLK
(External)
PWR_DOWN
CPUCLK
(Internal)
PCICLK
(Internal)
PWR_DWN
CPUCLK
(External)
PCICLK
(External)
VCO
Crystal
Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock.
Ordering Information
Package
Operating
Range
Ordering Code
CY2285PVC-1
CY2285PVC-2
CY2285PVC-3
Name
Package Type
28-Pin SSOP
O28
Commercial
Commercial
Commercial
O28
28-Pin SSOP
28-Pin SSOP
O28
Document #: 38-00732-C
8
CY2285
Package Diagram
28-Lead (210-Mil) Shrunk Small Outline Package O28
51-85079-B
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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