CY2282SC-11ST [CYPRESS]
Processor Specific Clock Generator, 100MHz, CMOS, PDSO28, 0.300 INCH, PLASTIC, SOIC-28;
| 型号： | CY2282SC-11ST |
| 厂家： | 
CYPRESS |
| 描述： | Processor Specific Clock Generator, 100MHz, CMOS, PDSO28, 0.300 INCH, PLASTIC, SOIC-28 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总7页 (文件大小：111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY2282-1
CY2282-11S
PRELIMINARY
100-MHz Pentium® II Clock Synthesizer/Driver with
Spread Spectrum and USB for Desktop PCs
3.3V USB clocks at 48 MHz, one 3.3V reference clock at
14.318 MHz, and one 2.5V APIC clock at 14.318 MHz.
Features
• Mixed 2.5V and 3.3V operation
• Clock Generator for Pentium® II, and other similar pro-
cessor-based motherboards
The CY2282-11S provides the same outputs as the CY2282-1
but also incorporates the Intel®-defined spread spectrum fea-
tures. It provides a 0.5% downspread on the CPU and PCI
clocks, which can improve EMI in certain high-speed systems.
A summary of clock outputs for both devices is shown below.
— Two 2.5V CPU clocks at 66.6 or 100 MHz
— Seven 3.3V synch. PCI clocks, one free-running
— Two 3.3V 48 MHz USB clocks
— One 3.3V REF clock at 14.318 MHz
— One 2.5V APIC clock at 14.318 MHz or PCI/2
• Spread spectrum clocking for EMI control (CY2282-11S
only)
• Factory-EPROM programmable output drive and slew
rate for EMI optimization
The CY2282 outputs are designed for low EMI emissions.
Controlled rise and fall times, unique output driver circuits, and
factory-EPROM programmable output drive and slew-rate en-
able optimal configurations for EMI control.
CY2282 Selector Guide
Clock Outputs
CPU (66.6, 100 MHz)
PCI (CPU/2, CPU/3 MHz)
USB (48 MHz)
CY2282-1
CY2282-11S
2
2
Low skew outputs, 175 ps between CPU clocks
•
≤
[1]
[1]
• Available in space-saving 28-pin SOIC package
7
7
2
2
Functional Description
APIC (14.318 MHz)
REF (14.318 MHz)
CPU-PCI delay
1
1
1
1
The CY2282 is a clock synthesizer/driver for a Pentium II, or
other similar processor-based PC requiring 100-MHz support.
The CY2282-1 outputs two CPU clocks at 2.5V. There are sev-
en PCI clocks, running at one-half or one-third the CPU clock
frequency of 66.6 MHz and 100 MHz respectively. One of the
PCI clocks is free-running. Additionally, the part outputs two
1.5–4.0 ns
None
1.5–4.0 ns
–0.5%
Spread Spectrum
Note:
1. One free-running PCI clock.
Logic Block Diagram
APIC
Pin Configuration
VDDAPIC
REF
SOIC
Top View
XTALIN
14.318
MHz
OSC.
XTALIN
1
2
3
28
27
26
25
24
V
SS
VDDREF
XTALOUT
REF
XTALOUT
STOP
LOGIC
CPU
PLL
V
SS
CPUCLK [0-1]
VDDCPU
V
V
DDREF
PCICLK_F
4
5
6
7
8
9
DDAPIC
Divider
Delay
PCICLK1
PCICLK2
PCICLK3
PCICLK4
APIC
V
23
22
21
PCICLK_F
VDDPCI
DDCPU
CPUCLK0
CPUCLK1
SEL100
EPROM
SYS PLL
V
DDPCI
20
19
18
17
STOP
LOGIC
AV
DD
PCI [1-6]
VDDPCI
10
PCICLK5
PCICLK6
V
SS
11
12
13
14
NC
V
DDUSB
NC
16
15
USBCLK0
USBCLK1
SEL100
V
SS
USBCLK [0:1]
VDDUSB
Intel and Pentium are registered trademarks of Intel Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
October 12, 1998
CY2282-1
PRELIMINARY
CY2282-11S
Pin Summary
Name
Pins
Description
V
V
V
V
V
9
3.3V Digital voltage supply for PCI clocks
3.3V Digital voltage supply for USB clocks
3.3V Digital voltage supply for REF clocks
2.5V Digital voltage supply for APIC clocks
2.5V Digital voltage supply for CPU clocks
3.3V Analog voltage supply
DDPCI
12
DDUSB
DDREF
DDAPIC
DDCPU
26
25
23
AV
20
DD
V
3, 15, 19, 28
Ground
SS
[2]
XTALIN
1
Reference crystal input
[2]
XTALOUT
N/C
2
Reference crystal feedback
17, 18
16
No Connect. Can be driven HIGH or LOW.
SEL100
CPU frequency select input, selects between 100 MHz and 66.6 MHz (see table below)
Internal pull-up to V
DD
CPUCLK[0:1]
PCICLK[1:6]
21, 22
CPU clock outputs
5, 6, 7, 8, 10, 11
PCI clock outputs, at one-half or one-third the CPU frequency of 66.6 MHz or 100 MHz
respectively
PCICLK_F
APIC
4
Free-running PCI clock output
APIC clock outputs
24
REF
27
3.3V Reference clock outputs
USB clock outputs
USBCLK[0:1]
13, 14
Function Table
CPU/PCI
Ratio
PCICLK_F
SEL100
CPUCLK
66.66 MHz
100 MHz
PCICLK
33.33 MHz
33.33 MHz
REF
14.318 MHz
14.318 MHz
APIC
14.318 MHz
14.318 MHz
USBCLK
48 MHz
48 MHz
0
1
2
3
Actual Clock Frequency Values
Target Frequency Actual Frequency
(MHz) (MHz)
Clock Output
CPUCLK
PPM
66.67
100
66.654
–195
CPUCLK
99.77
–2346
167
USBCLK
48.0
48.008
Note:
2. For best accuracy, use a parallel-resonant crystal, CLOAD = 18 pF.
2
CY2282-1
PRELIMINARY
CY2282-11S
Storage Temperature (Non-Condensing) ... –65°C to +150°C
Max. Soldering Temperature (10 sec) ...................... +260°C
Junction Temperature............................................... +150°C
Package Power Dissipation .............................................. 1W
Static Discharge Voltage ........................................... >2000V
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Supply Voltage..................................................–0.5 to +7.0V
Input Voltage.............................................. –0.5V to V +0.5
DD
(per MIL-STD-883, Method 3015, like V pins tied together)
DD
Operating Conditions[3]
Parameter
Description
Analog and Digital Supply Voltage
Min.
Max.
Unit
AV , V
,
3.135
3.465
V
DD DDPCI
V
V
V
, V
DDUSB
DDREF
CPU Supply Voltage
2.375
2.375
0
2.625
2.625
70
V
V
DDCPU
APIC Supply Voltage
DDAPIC
T
Operating Temperature, Ambient
°C
pF
A
C
Max. Capacitive Load on
CPUCLK
L
20
30
20
20
PCICLK
APIC, REF
USB
f
Reference Frequency, Oscillator Nominal Value
14.318
14.318
MHz
(REF)
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min. Max. Unit
[4]
[4]
V
High-level Input Voltage
Low-level Input Voltage
High-level Output Voltage
Except Crystal Inputs
Except Crystal Inputs
2.0
V
V
V
IH
IL
V
V
0.8
0.4
V
V
V
= V
= 2.375V
I
I
I
I
= 12 mA CPUCLK 2.0
= 18 mA APIC
OH
DDCPU
DDAPIC
OH
OH
OL
OL
V
V
Low-level Output Voltage
High-level Output Voltage
= V
= 2.375V
= 12 mA CPUCLK
= 18 mA APIC
V
V
OL
DDCPU
DDAPIC
, AV , V
V
= 3.135V I = 14.5 mA PCICLK
2.4
OH
DDPCI
DD DDREF, DDUSB
OH
I
I
I
I
I
= 16 mA USBCLK
= 16 mA REF
OH
OH
OL
OL
OL
V
Low-level Output Voltage
V
, AV , V
V = 3.135V
= 9.4 mA PCICLK
0.4V
V
OL
DDPCI
DD DDREF, DDUSB
= 9 mA
= 9 mA
USBCLK
REF
I
I
I
I
Input High Current
Input Low Current
V
V
= V
–10 +10 µA
10 µA
–10 +10 µA
= 2.625V, V = 0 or V , Loaded Outputs, CPU = 66.6 MHz 70 mA
IN DD
IH
IH
IL
DD
= 0V
IL
Output Leakage Current Three-state
OZ
Power Supply Current for
2.5V clocks
V
V
V
DD25
DDCPU
I
I
Power Supply Current for
2.5V clocks
= 2.625V, V = 0 or V , Loaded Outputs, CPU = 100 MHz
100 mA
170 mA
DD25
DD33
DDCPU
IN
DD
Power Supply Current for
3.3V clocks
= 3.465V, V = 0 or V , Loaded Outputs
IN DD
DD
Notes:
3. Electrical parameters are guaranteed with these operating conditions.
4. Crystal Inputs have CMOS thresholds.
3
CY2282-1
PRELIMINARY
CY2282-11S
Switching Characteristics[5] Over the Operating Range
Parameter
Output
All
Description
Test Conditions
t = t ÷ t
Min.
45
Typ.
Max.
55
Unit
%
[6]
t
t
Output Duty Cycle
50
1
2
1
1A
1B
CPUCLK,
APIC
CPU and APIC Clock Rising Between 0.4V and 2.0V
and Falling Edge Rate
1.0
4.0
V/ns
t
t
PCICLK
PCI Clock Rising and Falling Between 0.4V and 2.4V
Edge Rate
1.0
0.5
0.4
4.0
2.0
V/ns
V/ns
2
2
USBCLK,
REF
USB, REF Rising andFalling Between 0.4V and 2.4V
Edge Rate
t
t
t
CPUCLK
CPUCLK
CPU Clock Fall Time
CPU-CPU Clock Skew
Between 2.0V and 0.4V
Measured at 1.25V
1.8
175
4.0
ns
ps
ns
4
5
6
100
[7]
CPUCLK,
PCICLK
CPU-PCI Clock Skew
Measured at 1.25V for 2.5V
clocks, and at 1.5V for 3.3V
clocks
1.5
t
PCICLK,
PCICLK
PCI-PCI Clock Skew
Measured at 1.5V
250
ps
7
t
t
t
CPUCLK
PCICLK
Cycle-Cycle Clock Jitter
Cycle-Cycle Clock Jitter
Power-up Time
Measured at 1.25V
Measured at 1.5V
200
250
250
500
3
ps
ps
8
9
CPUCLK,
PCICLK
CPU, PCI clock stabilization
from power-up
ms
10
Notes:
5. All parameters specified with loaded outputs.
6. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V.
7. PCI lags CPU.
Switching Waveforms
Duty Cycle Timing
t
1B
t
1A
All Outputs Rise/Fall Time
VDD
0V
OUTPUT
t
2
t
3
t
2
t
4
CPU-CPU Clock Skew
1.25V
CPUCLK
1.25V
CPUCLK
t
5
4
CY2282-1
PRELIMINARY
CY2282-11S
Switching Waveforms (continued)
CPU-PCI Clock Skew
1.25V
CPUCLK
PCICLK
1.5V
t6
PCI-PCI Clock Skew
1.5V
PCICLK
1.5V
PCICLK
t
7
5
CY2282-1
PRELIMINARY
CY2282-11S
Application Information
Clock traces must be terminated with either series or parallel termination, as they are normally done.
Application Circuit
XTALIN
XTALOUT
Cx
Rs
APIC
APIC
CPUCLK
PCICLK_F
PCICLK
CPUCLK
PCICLK_F
PCICLK
REF
REF
SEL100
SEL100
USBCLK
USBCLK
VDDPCI
VDDREF
VDDUSB
AVDD
Cd
0.1 F
µ
VDDAPIC
VDDCPU
Cd
0.1 F
µ
Ct
VSS
CY2282-1,-11S 28 PIN SOIC
Cd = DECOUPLING CAPACITORS
Ct = OPTIONAL EM-REDUCING CAPACITORS
Cx = OPTIONAL LOAD MATCHING CAPACITOR
Rs = SERIES TERMINATING RESISTORS
Summary
• A parallel-resonant crystal should be used as the reference to the clock generator. The operating frequency and CLOAD of
this crystal should be as specified in the data sheet. Optional trimming capacitors may be needed if a crystal with a different
CLOAD is used. Footprints must be laid out for flexibility.
• Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1 µF.
In some cases, smaller value capacitors may be required.
• The value of the series terminating resistor satisfies the following equation, where Rtrace is the loaded characteristic imped-
ance of the trace, Rout is the output impedance of the clock generator (specified in the data sheet), and Rseries is the series
terminating resistor.
Rseries > Rtrace – Rout
• Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor
as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF.
• A Ferrite Bead may be used to isolate the Board VDD from the clock generator VDD island. Ensure that the Ferrite Bead
offers greater than 50Ω impedance at the clock frequency, under loaded DC conditions. Please refer to the application note
“Layout and Termination Techniques for Cypress Clock Generators” for more details.
• If a Ferrite Bead is used, a 10 µF–22 µF tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor
prevents power supply droop during current surges.
6
CY2282-1
PRELIMINARY
CY2282-11S
Test Circuit
V
V
, AV
,
DD
DDPCI
, V
DDUSB
DDREF
3, 15, 19, 28
9, 12, 20, 26
0.1 µF
CY2282-1, -11S
V
, V
DDAPIC
DDCPU
OUTPUTS
C
LOAD
23, 25
0.1 µF
Notes:
Each supply pin must have an individual decoupling capacitor
All capacitors must be placed as close to the pins as is possible.
Ordering Information
Ordering Code
CY2282SC–1
Package Name Package Type Operating Range
S21
S21
28-Pin SOIC
28-Pin SOIC
Commercial
Commercial
CY2282SC–11S
Document #: 38–00693–A
Package Diagram
28-Lead (300-Mil) Molded SOIC S21
51-85026-A
© Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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