CY2281PVC-2S [CYPRESS]

Processor Specific Clock Generator, 100MHz, CMOS, PDSO28, 0.210 INCH, SSOP-28;


型号：	CY2281PVC-2S
厂家：	CYPRESS
描述：	Processor Specific Clock Generator, 100MHz, CMOS, PDSO28, 0.210 INCH, SSOP-28 时钟光电二极管外围集成电路晶体
文件：	总9页 (文件大小：151K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PRELIMINARY

CY2281

100MHz Pentium^®II Clock Synthesizer/Driver

with Spread Spectrum for Mobile PCs

duce EMI in certain high-speed systems. A summary of clock

outputs for both devices is shown below.

Features

Mixed 2.5V and 3.3V operation

Complete clock solution for Pentium® II, and other sim-

ilar processor-based motherboards

•

The part possesses power-down, CPU stop, and PCI stop pins

for power management control. The signals are synchronized

on-chip, and ensure glitch-free transitions on the outputs.

When the CPU_STOP input is asserted, the CPU clock out-

puts are driven LOW. When the PCI_STOP input is asserted,

the PCI clock outputs (except the free-running PCI clock) are

driven LOW. When the PWR_DWN pin is asserted, the refer-

ence oscillator and PLLs are shut down, and all outputs are

driven LOW.

— Two CPU clocks at 2.5V up to 100 MHz

— Six synchronous PCI clocks, one free-running

— One 3.3V Ref. clock at 14.318 MHz

— One 3.3V USB clock at 48 MHz (-2S only)

• Spread Spectrum clocking for EMI control (-11S, -2S)

• 1.5–4.0 ns delay between CPU and PCI clocks

Power-down, CPU stop and PCI stop pins

The CY2281 clock outputs are designed for low EMI emis-

sions. Controlled rise and fall times, unique output driver cir-

cuits, and innovative circuit layout techniques enable the

CY2281 to have lower EMI than clock devices from other man-

ufacturers. Additionally, factory-EPROM programmable output

drive and slew-rate control enable optimal configurations.

•

Low skew outputs, 175 ps between CPU clocks

≤

Factory-EPROM programmable output drive and slew

rate for EMI customization

• Available in space-saving 28-pin SSOP package

CY2281 Selector Guide

Functional Description

Clock Outputs

CPU (66, 100 MHz)

PCI (CPU/2, CPU/3)

REF (14.318 MHz)

USB (48 MHz)

-1

-11S

-2S

The CY2281 is a clock synthesizer/driver for Pentium II, or

other similar processor-based mobile PCs requiring up to 100

MHz support. The CY2281 outputs two CPU clocks at 2.5V.

There are six PCI clocks, running at one-half or one-third the

CPU clock frequency of 66.6 MHz and 100 MHz respectively.

One of the PCI clocks is free-running. Additionally, the part

outputs one 3.3V reference clock at 14.318 MHz. The

CY2281-2S also provides one 3.3V USB clock at 48 MHz.

[1]

N/A

CPU-PCI delay

1.5–4.0 ns 1.5–4.0 ns 1.5–4.0 ns

None –0.6% –0.6%

Spread Spectrum

The CY2281-11S and CY2281-2S incorporate the Intel®-de-

fined spread spectrum feature. They provide a –0.6%

downspread on the CPU and PCI clocks, which can help re-

Note:

1. One free-running PCI clock.

Pin Configuration

Logic Block Diagram

28-Pin SSOP

Top View

CPU_STOP

XTALIN

REF

XTALOUT

DDREF

XTALIN

14.318

MHz

OSC.

REF

V_DDREF

PCICLK_F

PCICLK1

XTALOUT

DDCPU

STOP

LOGIC

CPU

PLL

CPUCLK0

CPUCLK1

CPUCLK [0–1]

V_DDCPU

DDPCI

Divider

Delay

PCICLK2

PCICLK3

PWR_DWN

PCICLK_F

V_DDPCI

DDPCI

SEL

(-1/-11S only)

PCICLK4

PCICLK5

PCI_STOP

EPROM

CPU_STOP

STOP

LOGIC

PCI [1-5]

V_DDPCI

SEL100

PWR_DWN

SEE CHART BELOW

DDUSB

SEL100

SYS

PLL

USBCLK (-2S only)

V_DDUSB

Option

Pin 16

-1,-11S

SEL

PCI_STOP

-2S

USBCLK

Intel and Pentium are registered trademarks of Intel Corporation.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

October 12, 1998

PRELIMINARY

CY2281

Pin Summary

Name

Pins

Description

6, 9

3.3V Digital voltage supply for PCI clocks

DDPCI

DDREF

DDCPU

DDUSB

3.3V Digital voltage supply for REF clocks

2.5V Digital voltage supply for CPU clocks

3.3V Digital voltage supply for USB clock

Analog voltage supply, 3.3V

3, 12, 14, 20, 22, 28

Ground

[2]

XTALIN

XTALOUT

Reference crystal input

[2]

Reference crystal feedback

PCI_STOP

CPU_STOP

PWR_DWN

SEL

Active LOW control input to stop PCI clocks

Active LOW control input to stop CPU clocks

Active LOW control input to power down device

CPU frequency select input (-1 and -11S options only)

USB clock output, 48 MHz fixed (-2S option only)

USBCLK

SEL100

CPU frequency select input, selects between 100 MHz and 66.6 MHz

(see table below)

CPUCLK[0:1]

PCICLK[1:5]

23, 24

CPU clock outputs

5, 7, 8, 10, 11

PCI clock outputs, at one-half or one-third the CPU frequency of 66.6 MHz

or 100 MHz respectively

PCICLK_F

REF

Free-running PCI clock output

3.3V Reference clock output

Function Table

CPU/PCI

PCICLK_F

PCICLK

[4]

[5]

SEL100 SEL

Ratio

CPUCLK

Hi-Z

USBCLK

REF

Hi-Z

66.66 MHz 33.33 MHz 48 MHz

14.318 MHz

[3]

TCLK/2

TCLK/6

TCLK

100 MHz

33.33 MHz 48 MHz

14.318 MHz

Notes:

2. For best accuracy, use a parallel-resonant crystal, C_LOAD= 18 pF.

3. TCLK supplied on the XTALIN pin in Test Mode.

4. SEL available on options -1 and -11S only. SEL tied HIGH internally on option -2S

5. USBCLK available on option -2S only.

PRELIMINARY

CY2281

Actual Clock Frequency Values

Target Frequency Actual Frequency

(MHz) (MHz)

Clock Output

CPUCLK

USB

PPM

–195

66.67

100

66.654

99.77

–2346

167

48.008

Power Management Logic

Other

CPU_STOP PCI_STOP

PWR_DWN

CPUCLK

Low

PCICLK

PCICLK_F Clocks

Osc.

Off

PLLs

Low

Off

Low

Running

Running Running Running

Low

Running

Low

Running

PRELIMINARY

CY2281

Storage Temperature (Non-Condensing) ... –65°C to +150°C

Max. Soldering Temperature (10 sec) ...................... +260°C

Junction Temperature............................................... +150°C

Static Discharge Voltage ........................................... >2000V

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Supply Voltage............................................... –0.5V to +7.0V

(per MIL-STD-883, Method 3015, like V pins tied together)

Input Voltage.............................................. –0.5V to V +0.5

Operating Conditions^[6]

Parameter

AV , V

Description

Analog and Digital Supply Voltage

Min.

Max.

Unit

3.135

3.465

DD DDPCI

DDREF, DDUSB

CPU Supply Voltage

2.375

2.625

DDCPU

Operating Temperature, Ambient

°C

Max. Capacitive Load on

CPUCLK

PCICLK

REF

Reference Frequency, Oscillator Nominal Value

14.318

MHz

(REF)

Electrical Characteristics Over the Operating Range

Parameter

Description

Test Conditions

Min. Max. Unit

[7]

High-level Input Voltage

Low-level Input Voltage

High-level Output Voltage

Low-level Output Voltage

High-level Output Voltage

Except Crystal Inputs

2.0

0.8

0.4

= 2.375V

= 12 mA

CPUCLK 2.0

CPUCLK

DDCPU

, AV , V

= 3.135V

= 14.5 mA PCICLK

= 16 mA REF, USB

= 9.4 mA PCICLK

= 9 mA REF, USB

2.4

DDPCI

DD DDREF

Low-level Output Voltage

, AV , V

= 3.135V

0.4V

DDPCI

DD DDREF

Input High Current

Input Low Current

= V

–10 +10 µA

10 µA

–10 +10 µA

= 2.625V, V = 0 or V , Loaded Outputs, CPU = 66.6 MHz 70 mA

IN DD

= 0V

Output Leakage Current Three-state

Power Supply Current for

2.5V Clocks

DD25

DDCPU

Power Supply Current for

2.5V Clocks

= 2.625V, V = 0 or V , Loaded Outputs, CPU = 100 MHz

100 mA

170 mA

500 µA

DD25

DD33

DDS

DDCPU

Power Supply Current for

3.3V Clocks

= 3.465V, V = 0 or V , Loaded Outputs

IN DD

Powerdown Current

Current draw in powerdown state

Notes:

6. Electrical parameters are guaranteed with these operating conditions.

7. Crystal Inputs have CMOS thresholds.

PRELIMINARY

CY2281

Switching Characteristics^[8]Over the Operating Range

Parameter

Output

All

Description

Test Conditions

Min. Typ. Max.

Unit

[9]

Output Duty Cycle

t = t ÷ t

CPUCLK

CPU Clock Rising and

Falling Edge Rate

Between 0.4V and 2.0V

Between 0.4V and 2.4V

1.0

4.0

V/ns

PCICLK

PCI Clock Rising and

Falling Edge Rate

1.0

0.5

4.0

2.0

V/ns

REF, USB REF Clock Rising and

Falling Edge Rate

CPUCLK

CPU Clock Rise Time

CPU Clock Fall Time

CPU-CPU Clock Skew

Between 0.4V and 2.0V

Between 2.0V and 0.4V

Measured at 1.25V

0.4

1.6

175

4.0

100

CPUCLK, CPU-PCI Clock Skew

PCICLK

Measured at 1.25V for 2.5V clocks, and

at 1.5V for 3.3V clocks

1.5

PCICLK,

PCICLK

PCI-PCI Clock Skew

Measured at 1.5V

250

CPUCLK

PCICLK

Cycle-Cycle Clock Jitter Measured at 1.25V

Cycle-Cycle Clock Jitter Measured at 1.5V

250

500

CPUCLK, Power-up Time

PCICLK

CPU and PCI clock stabilization from

power-up

Notes:

8. All parameters specified with loaded outputs.

9. Duty cycle is measured at 1.5V when V_DD= 3.3V. When V_DD= 2.5V, duty cycle is measured at 1.25V.

Switching Waveforms

Duty Cycle Timing

OUTPUT

All Outputs Rise/Fall Time

V_DD

OUTPUT

CPU-CPU Clock Skew

CPUCLK

PRELIMINARY

CY2281

Switching Waveforms (continued)

CPU-PCI Clock Skew

CPUCLK

PCICLK

t₆

PCI-PCI Clock Skew

PCICLK

CPU_STOP

CPUCLK

(Internal)

PCICLK

(Internal)

PCICLK

(Free-Running)

CPU_STOP

CPUCLK

(External)

PCI_STOP

CPUCLK

(Internal)

PCICLK

(Internal)

PCICLK

(Free-Running)

PCI_STOP

PCICLK

(External)

PWR_DOWN

CPUCLK

(Internal)

PCICLK

(Internal)

PWR_DWN

CPUCLK

(External)

PCICLK

(External)

VCO

Crystal

Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock.

PRELIMINARY

CY2281

Application Information

Clock traces must be terminated with either series or parallel termination, as they are normally done.

Application Circuit

XTALIN

XTALOUT

PWR_DWN#

CPU_STOP#

PCI_STOP#

SEL

PWR_DWN#

CPU_STOP#

PCI_STOP#

SEL

REF

CPUCLK

PCICLK

REF

CPUCLK

PCICLK

PCICLK_F

SEL100

VDD 3.3V

VDDPCI/VDDREF

AVDD/VDDUSB

0.1µF

VDD 2.5V

VDDCPU

0.1µF

VSS

CY2281 28-PIN SSOP

Cd = DECOUPLING CAPACITORS

Ct = OPTIONAL EMI-REDUCING CAPACITORS

Cx = OPTIONAL LOAD MATCHING CAPACITOR

Rs = SERIES TERMINATING RESISTORS

Summary

• A parallel-resonant crystal should be used as the reference to the clock generator. The operating frequency and C

LOAD

this crystal should be as specified in the data sheet. Optional trimming capacitors may be needed if a crystal with a different

is used. Footprints must be laid out for flexibility.

LOAD

• Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1 µF.

In some cases, smaller value capacitors may be required.

• The value of the series terminating resistor satisfies the following equation, where Rtrace is the loaded characteristic imped-

ance of the trace, Rout is the output impedance of the clock generator (specified in the data sheet), and Rseries is the series

terminating resistor.

Rseries > Rtrace – Rout

• Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor

as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF.

• A Ferrite Bead may be used to isolate the Board VDD from the clock generator VDD island. Ensure that the Ferrite Bead

offers greater than 50Ω impedance at the clock frequency, under loaded DC conditions. Please refer to the application note

“Layout and Termination Techniques for Cypress Clock Generators” for more details.

• If a Ferrite Bead is used, a 10 µF–22 µF tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor

prevents power supply droop during current surges.

PRELIMINARY

CY2281

Test Circuit

, AV

DDPCI

DDREF

3, 12, 14, 20, 22, 28

6, 9, 13, 21, 27

0.1 µF

CY2281-1,-11S, -2S

DDCPU

OUTPUTS

LOAD

0.1 µF

Notes:

Each supply pin must have an individual decoupling capacitor

All capacitors must be placed as close to the pins as is possible.

Ordering Information

Package

Name

Operating

Ordering Code

CY2281PVC-1

Package Type

28-Pin SSOP

Range

Commercial

O28

CY2281PVC-11S

CY2281PVC-2S

28-Pin SSOP

Document #: 38-00660-C

PRELIMINARY

CY2281

Package Diagram

28-Lead (210-Mil) Shrunk Small Outline Package O28

51-85079-B

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

CY2281PVC-2S [CYPRESS]

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