CY2260SC-3 [CYPRESS]
Processor Specific Clock Generator, 66.66MHz, MOS, PDSO28, 0.300 INCH, PLASTIC, SOIC-28;
| 型号： | CY2260SC-3 |
| 厂家： | 
CYPRESS |
| 描述： | Processor Specific Clock Generator, 66.66MHz, MOS, PDSO28, 0.300 INCH, PLASTIC, SOIC-28 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总7页 (文件大小：113K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1CY2260
fax id: 3520
CY2260
Clock Synthesizer/Driver for
Pentium™ and Pentium Pro™ Processors
• 3.3V or 5V operation
Features
• Internal pull-up resistors on S0, S1, and OE inputs
• Multiple clock outputs to meet requirements of most
motherboards using Pentium™, Pentium Pro™, or
Cyrix™ processors
Functional Description
The CY2260 is a Clock Synthesizer/Driver chip for an Intel®
Pentium or Pentium Pro processor based PC. The part outputs
multiple clocks to serve the requirements of most mother-
boards. The CY2260 has low-skew outputs (< 250 ps between
the CPU Clocks, < 250 ps between the PCI Clocks). In addi-
tion, the CY2260 CPU clock outputs have less than 200 ps
cycle-to-cycle jitter. Finally, both the PCI and CPU clock out-
puts meet the 1V/ns slew rate requirement of the Pentium- and
Pentium Pro-based processor system.
— Four CPU clocks (CPUCLK) @ 66.66 MHz, 60.0 MHz,
or 50.0 MHz, pin selectable (plus 55.0 MHz on –2, –3,
and –3H options)
— Six PCI clocks (PCICLK) @ (CPUCLK/2) MHz
— One USB clock @ 48.0 MHz
— Three Ref. clocks @ 14.318 MHz (Two on –2, –3, and
–3H options)
— I/O clock @ 24MHz (–2, –3, and –3H options only)
— Ref. 14.318 MHz Xtal oscillator input
• CPU clock jitter < 200 ps cycle-to-cycle
• Low skew outputs
The CY2260 accepts a 14.318 MHz reference signal as its
input. The CY2260 has two PLLs, one of which generates the
CPU and PCI clocks, and the other generates the Universal
Serial Bus (USB) and I/O clocks. The CY2260 runs off a 3.3V
or 5V supply.
— < 250 ps between CPU clocks
The CY2260 is available in five options. The −1 and –1H op-
tions provide three buffered reference clocks. The −2 and −3
options provide two buffered reference clocks and a 24 MHz
I/O clock. The −2 and −3 options also support Cyrix proces-
sors. Finally, the −3H configuration is the same as the −3, ex-
cept that it has high drive USB and I/O clocks to drive multiple
outputs.
— < 250 ps between PCI clocks (PCICLK)
— +1 ns min. to +4 ns max. skew between CPU and PCI
clocks (CPU leads PCI)
• Output duty cycle 45% min. to 55% max.
• Available in 28-pin SOIC and SSOP packages
• Test mode support (–1 option)
Logic Block Diagram
Pin Configuration
REF0(14.318MHz)
Top View
SOIC/SSOP
REF1(14.318MHz)
REF2(14.318MHz)
V
DD
REF0
REF1
1
2
3
4
28
27
26
25
XTALIN
XTALIN
14.318
MHz
OSC.
XTALOUT
V
DD
SYS
PLL
USBCLK(48MHz)
V
SEEBELOW
SEEBELOW
SS
XTALOUT
/2
OE
5
24
23
22
21
20
19
18
17
IOCLK(24MHz)
CPUCLK0
CPUCLK1
CPUCLK2
CPUCLK3
CPUCLK0
6
V
SS
CPU
PLL
CPUCLK1
7
PCICLK5
PCICLK4
V
DD
8
CPUCLK2
CPUCLK3
V
DD
9
PCICLK3
PCICLK2
10
11
12
ROM
V
SS
S1
S0
V
SS
PCICLK1
PCICLK0
13
14
16
15
S0
S1
/2
V
DD
Note:
DELAY
2260–2
CPUCLK= CPU Clock
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK= PCI Bus Clock
OPTION
PIN 24
PIN 25
REF2
USBCLK
48 MHz
−1
–1H
14.318 MHz
IOCLK
−2
USBCLK
48 MHz
24 MHz
PCICLK4
−3
−3H
IOCLK
USBCLK
48 MHz
24 MHz
PCICLK5
2260–1
OE
Intel is a registered trademark of Intel Corporation. Cyrix is a registered trademark of Cyrix Corporation. Pentium and Pentium Pro are trademarks of Intel Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
August 30, 1995 – Revised May 15, 1997
CY2260
Pin Summary
Name
–1
1
–2
1
–3, -3H Description
V
1
Voltage supply
DD
[1]
XTALIN
XTALOUT
2
2
2
Reference crystal input
Reference crystal feedback
Ground
[1]
3
3
3
V
4
4
4
SS
OE
5
5
5
Output Enable, Active HIGH (internal pull-up resistor to V
CPU clock output
)
DD
CPUCLK0
CPUCLK1
6
6
6
7
7
7
CPU clock output
V
8
8
8
Voltage supply
DD
CPUCLK2
CPUCLK3
9
9
9
CPU clock output
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
10
11
12
13
14
15
16
17
18
19
20
21
22
23
25
CPU clock output
V
Ground
SS
S1
S0
CPU clock select input, bit 1 (internal pull-up resistor to V
CPU clock select input, bit 0 (internal pull-up resistor to V
Voltage supply
)
DD
)
DD
V
DD
PCICLK0
PCICLK1
PCI clock output
PCI clock output
V
Ground
SS
PCICLK2
PCICLK3
PCI clock output
PCI clock output
V
Voltage supply
DD
PCICLK4
PCICLK5
PCI clock output
PCI clock output
V
Ground
SS
USBCLK
REF2
Universal Serial Bus clock output (48 MHz)
Reference clock output (14.318 MHz)
I/O clock output (24 MHz)
Voltage supply
IOCLK
25
26
27
28
24
26
27
28
V
26
27
28
DD
REF1
REF0
Reference clock output (14.318 MHz)
Reference clock output (14.318 MHz) for ISA slots, drives 45 pF loads
Function Table
IOCLK
XTALIN
Input
REF0,REF1,
REF2
–2,–3,–3H
only
Option
OE S0 S1
CPUCLK
PCICLK
High-Z
USBCLK
High-Z
−1,–1H,−2,−3,−3H
−1,–1H,−2,−3,−3H
−1,–1H,−2,−3,−3H
−1,−2,−3,−3H
−1,–1H
0
1
1
1
1
1
X
0
0
1
1
1
X
0
1
0
1
1
14.318 MHz High-Z
14.318 MHz 50.0 MHz
14.318 MHz 60.0 MHz
High-Z
High-Z
25.0 MHz
30.0 MHz
33.33 MHz
TCLK/4
14.318 MHz 48 MHz
14.318 MHz 48 MHz
14.318 MHz 48 MHz
24 MHz
24 MHz
24 MHz
14.318 MHz 66.66 MHz
[2]
TCLK
TCLK/2
TCLK
TCLK/2
−2,−3,−3H
14.318 MHz 55 MHz
27.5 MHz
14.318 MHz 48 MHz
24 MHz
Notes:
1. For best accuracy, use a parallel-resonant crystal, CLOAD = 18 pF.
2. TCLK is a test clock on the XTALIN input during test mode.
2
CY2260
Maximum Ratings
Actual Frequency Values
Clock
Target
Actual
49.802
60.0
PPM
–3960
0
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Supply Voltage ................................................. –0.5 to +7.0V
CPUCLK
50
60
CPUCLK
Input Voltage ..............................................–0.5V to V +0.5
DD
CPUCLK
66.667
55.0
48.0
48.0
24.0
24.0
66.316
54.98
–5265
–331
167
Storage Temperature (Non-Condensing) ... –65°C to +150°C
Max. Soldering Temperature (10 sec) ...................... +260°C
Junction Temperature............................................... +150°C
Package Power Dissipation.............................................. 1W
CPUCLK
USBCLK (H version)
USBCLK (non-H)
IOCLK (H version)
IOCLK (non-H)
48.008
48.109
24.004
24.055
2271
167
Static Discharge Voltage ........................................... >2000V
(per MIL–STD–883, Method 3015)
2271
Operating Conditions[3]
Parameter
Description
Min.
3.135 (4.5)
0
Max.
3.6 (5.5)
70
Unit
V
°C
pF
V
T
Supply Voltage, 3.3V (5V)
Operating Temperature, Ambient
Max. Capacitive Load on
DD
A
C
L
CPUCLK / PCICLK (−1, –1H option)
CPUCLK / PCICLK (−2,−3, 3H options)
USBCLK / IOCLK
REF0
REF1
30
20
20
45
30
25
REF2
f
Reference Frequency, Oscillator Nominal Value
14.318
14.318
MHz
(REF)
Electrical Characteristics V = 3.135V to 3.6V, or 4.5V to 5.5V, T = 0°C to +70°C
DD
A
Parameter
Description
Test Conditions
Min.
Max.
Unit
V
[4]
V
V
V
High-level Input Voltage
Low-level Input Voltage
Except Crystal Inputs
Except Crystal Inputs
2.0
IH
0.8
V
IL
High-level Output Voltage
CPUCLK / PCICLK
V
= V Min.
I
= −23 mA −1, –1H
2.4
V
OH
DD
DD
OH
options
V
High-level Output Voltage
CPUCLK / PCICLK
V
= V Min.
I
= −15 mA −2,−3,−3H
V
OH
DD
DD
OH
options
V
V
V
V
V
V
V
USBCLK
USBCLK, IOCLK
IOCLK
V
V
V
V
V
V
V
= V Min.
I
I
I
I
I
I
I
= −4 mA
−1,−2,−3 options
V
V
V
V
V
V
V
OH
OH
OH
OH
OH
OH
OL
DD
DD
DD
DD
DD
DD
DD
DD
OH
OH
OH
OH
OH
OH
OL
= V Min.
= −15 mA –1H,−3H options
DD
= V Min.
= −4 mA
−2,−3 options
DD
REF0
= V Min.
= −15 mA All options
= −11 mA All options
DD
REF1
= V Min.
DD
REF2
= V Min.
= −8 mA
−1 option
−1 option
DD
Low-level Output Voltage
CPUCLK / PCICLK
= V Min.
= 16 mA
0.4
DD
V
Low-level Output Voltage
CPUCLK / PCICLK
V
= V Min.
I
= 12 mA
−2, −3,−3H
options
V
OL
DD
DD
OL
V
V
V
V
V
V
USBCLK
V
V
V
V
V
V
V
V
= V Min.
I
I
I
I
I
I
= 4 mA
= 15 mA
= 4 mA
= 12 mA
= 8 mA
= 6 mA
−1,−2,−3 options
–1H,−3H options
−2,−3 options
All options
V
V
OL
OL
OL
OL
OL
OL
DD
DD
DD
DD
DD
DD
DD
OL
OL
OL
OL
OL
OL
USBCLK
= V Min.
DD
IOCLK
= V Min.
V
DD
REF0
= V Min.
V
DD
REF1
= V Min.
All options
V
DD
REF2
= V Min.
−1,–1H options
V
DD
I
I
I
I
Input High Current
Input Low Current
Output Leakage Current
Power Supply Current
= V = 3.3V (5V)
5 (10)
100 (250)
+10
µA
µA
µA
IH
IH
IL
DD
= 0V, V = 3.3V (5V)
IL
DD
Three-state
−10
OZ
DD
V
V
= 3.6V, V = 0 or V
90
150
mA
mA
DD
DD
IN
DD
DD
= 5.5V, V = 0 or V
IN
Notes:
3. Electrical parameters are guaranteed with these operating conditions.
4. VIH = 3.0V when VDD = 5V.
3
CY2260
Switching Characteristics[5]
Parameter
Output
Description
Test Conditions
t = t ÷ t
Min.
45%
5.0
Max.
Unit
[6, 7]
t
All
Output Duty Cycle
55%
1
1
1A
1B
t
t
t
t
t
CPUCLK
PCICLK
CPUCLK
PCICLK
CPUCLK
CPU Clock HIGH Time
Measured at 2.4V
Measured at 2.4V
Measured at 0.4V
Measured at 0.4V
ns
ns
1C
1C
1D
1D
2
[8]
PCI Clock HIGH Time
12.0
5.0
CPU Clock LOW Time
ns
[8]
PCI Clock LOW Time
12.0
1
ns
CPU Clock Rising and Fall- Measured between 0.4V and 2.4V
ing Edge Rate
4.0
V/ns
t
t
t
CPUCLK
CPUCLK
PCICLK
CPU Clock Rise Time
CPU Clock Fall Time
Measured between 0.4V and 2.4V
Measured between 2.4V and 0.4V
0.5
0.5
1
2.0
2.0
4
ns
ns
3
4
2
PCI Clock Rising and Fall- Measured between 0.4V and 2.4V
ing Edge Rate
V/ns
t
t
t
REF[0:2]
Reference Clock Rising
and Falling Edge Rate
Measured between 0.4V and 2.4V
0.5
0.5
1.0
V/ns
V/ns
V/ns
2
2
2
USBCLK, IOCLK
USBCLK, IOCLK
USB and I/O Clock Rising Measured between 0.4V and 2.4V
and Falling Edge Rate
USB and I/O Clock Rising Measured between 0.4V and 2.4V
(–3H,–1H Options) and Falling Edge Rate
t
t
t
CPUCLK
PCICLK
CPU-CPU Clock Skew
PCI-PCI Clock Skew
Measured at 1.5V
Measured at 1.5V
Measured at 1.5V
250
250
4
ps
ps
ns
5
6
7
CPUCLK
PCICLK
CPU-PCI Clock Skew
(CPU leads)
1
t
t
t
t
CPUCLK
CPUCLK
PCICLK
CPUCLK
Cycle-Cycle Clock Jitter
Pk-Pk Period Clock Jitter
Pk-Pk Period Clock Jitter
Power-up Time
CPU Clock jitter
Measured at 1.5V
Measured at 1.5V
200
250
250
3
ps
ps
ps
ms
8
9
10
11
CPU clock stabilization from
power-up
t
PCICLK
Power-up Time
PCI clock stabilization from
power-up
3
ms
12
Output I-V Characteristics at 3.3V
I
vsV
(typical)[9]
I
vsV (typical)[9]
OL OL
OH
OH
75.00
50.00
120.00
100.00
80.00
60.00
40.00
20.00
0.00
25.00
0.00
−25.00
−50.00
−75.00
−100.00
−20.00
−40.00
−0.50 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
−0.50 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
V
OH
(V)
V
OL
(V)
Notes:
5. All parameters specified with outputs fully loaded.
6. Duty cycle is measured at 1.5V for 3.3V operation
7. Duty cycle is measured at 2.5V for 5V operation.
8. A LOW and HIGH time of 12 ns corresponds to a PCICLK frequency of 33.33 MHz. For PCICLK frequencies of 30 MHz, 27.5 MHz, and 25 MHz, the LOW
and HIGH times are each respectively 13.33 ns, 15 ns, and 16 ns.
9. This information is for modeling purposes only for -1 option and is not guaranteed. Typical output impedance on CPU and PCI clocks is 25 ohms on the -1
device, 40 ohms on the -2, -3, and -3H devices. Output impedance is measured at 1.5V.
4
CY2260
Switching Waveform
Duty CycleTiming
t
1B
t
1A
1.5V
1.5V
1.5V
All Outputs Rise/Fall Time
t
1C
VDD
0V
2.4V
0.4V
2.4V
0.4V
OUTPUT
0.4V
t
2
t
3
t
2
t
4
t
1D
Clock Skew
1.5V
CPUCLK-CPUCLK
or
1.5V
PCICLK-PCICLK
t
5
t
6
CPU–PCI Clock Skew
1.5V
CPUCLK
PCICLK
1.5V
t
7
5
CY2260
Test Circuit
V
DD
1
26
0.1 µF
0.1 µF
0.1 µF
0.1 µF
4
8
23
20
V
DD
17
11
14 OUTPUTS
C
LOAD
0.1 µF
Note: All capacitors should be placed as close to each pin as possible.
Ordering Information
Package
Operating
Range
Ordering Code
CY2260SC-1
Name
S21
S21
S21
S21
S21
O28
O28
O28
Package Type
28-Pin SOIC
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
CY2260SC-1H
CY2260SC-2
28-Pin SOIC
28-Pin SOIC
28-Pin SOIC
28-Pin SOIC
28-Pin SSOP
28-Pin SSOP
28-Pin SSOP
CY2260SC-3
CY2260SC-3H
CY2260PVC-1
CY2260PVC-2
CY2260PVC-3
Document #: 38-00476-E
6
CY2260
Package Diagram
28-Lead (300-Mil) Molded SOIC S21
28-Lead Shrunk Small Outline Package O28
© Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of anycircuitry other than circuitry embodied in a CypressSemiconductor product. Nor does it conveyor imply any license under patent or other rights. CypressSemiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
相关型号：
CY2260SC-3H
Processor Specific Clock Generator, 66.66MHz, MOS, PDSO28, 0.300 INCH, PLASTIC, SOIC-28
CYPRESS
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