CY2267PVC-1 [CYPRESS]
Processor Specific Clock Generator, 66.56MHz, MOS, PDSO34, SSOP-34;
| 型号： | CY2267PVC-1 |
| 厂家： | 
CYPRESS |
| 描述： | Processor Specific Clock Generator, 66.56MHz, MOS, PDSO34, SSOP-34 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总9页 (文件大小：103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY2267
Pentium , Pentium Pro, and Cyrix 6x86
Compatible Clock Synthesizer/Driver
Functional Description
Features
• Complete clock solution to meet requirements of Pen-
tium®, Pentium® Pro, or Cyrix® 6x86 motherboards in-
cluding dual-processor and SDRAM designs
The CY2267 is a low-cost Clock Synthesizer/Driver chip for a
Pentium, Pentium Pro, or Cyrix 6x86-based motherboard.
The CY2267 outputs sixteen CPU clocks, twelve of which can
be used to support up to three SDRAM modules. The PCI
clock output can be buffered with an external, low-cost Zero
Delay Buffer (CY2305/9), thus providing a complete solution
for 82430TX desktop systems.
— Sixteen CPU clock outputs, up to 66.66 MHz (see
Function Table)
— One synchronous PCI clock output
— One USB clock at 48 MHz, meets Intel’s accuracy,
jitter, as well as rise and fall time requirements
The CPU clocks of the CY2267 have less than 200 ps cy-
cle-to-cycle jitter. Both the CPU and PCI clocks have a slew
rate of greater than 1V/ns. The USB clock meets Intel’s accu-
racy, jitter, and rise and fall time requirements.
— One I/O clock at 24 MHz
— One Ref. clock at 14.318 MHz
• Two dedicated, independent Frequency Select inputs
(internalpull-up)easesystemdesign,enable in-system
frequency changes, and support OE control
All CPU clocks support fast clock stabilization on power-up
(< 2 ms). Additionally, two dedicated Frequency Select inputs
are used for Output Enable control and setting the CPU clock
output frequencies.
• Low CPU clock jitter 200 ps cycle-to-cycle
≤
• Low skew outputs
The CY2267 clock outputs are designed for low EMI emis-
sions. Controlled rise and fall times, unique output driver cir-
cuits, and innovative circuit layout techniques enable the
CY2267 to have lower EMI than clock devices from other man-
ufacturers. Please refer to the application note “Layout and
Termination Techniques for Cypress Clock Generators” for
more information on recommended system layout techniques.
—
250 ps between CPU clocks
≤
— 1ns 3ns skew between CPU and PCI clocks for com-
−
patibility with SiS 55XX as well as Intel 82430TX,
82430HX, and 82430VX chipsets (CY2267–1)
• Improved output drivers are designed for low EMI
• Meets Pentium and Pentium Pro power-up stabilization
requirements
• 3.3V operation, 5V tolerant inputs
• Available in space-saving 34-pin SSOP package
The CY2267 accepts a 14.318 MHz reference crystal or clock
as its input and runs off a 3.3V supply. The CY2267 is available
in a space-saving, low-cost 34-pin SSOP package and is
pin-compatible with the CY2264 and CY2265.
Pin Configuration
Logic Block Diagram
Top View
REFCLK (14.318MHz)
SSOP
V
DD
S2
1
2
3
4
34
33
32
31
XTALIN
14.318
MHz
OSC.
CPU
PLL
CPUCLK [1–16]
XTALIN
REFCLK
XTALOUT
XTALOUT
V
DD
/2
V
SS
IOCLK
ROM
CPUCLK16
CPUCLK1
USBCLK
5
30
29
28
27
26
25
24
23
Delay
(–1only)
V
SS
6
PCICLK
7
CPUCLK2
S1
S2
/2
CPUCLK13
8
V
DD
IOCLK (24MHz)
V
DD
CPUCLK3
CPUCLK4
9
CPUCLK12
CPUCLK11
10
11
12
SYS
PLL
V
SS
/2
USBCLK (48MHz)
CPUCLK5
CPUCLK6
V
SS
CPUCLK10
CPUCLK9
13
14
22
21
20
19
18
V
DD
V
SS
S1
15
16
17
PCICLK
CPUCLK14
CPUCLK8
CPUCLK15
CPUCLK7
2267–a
2267–b
Intel and Pentium are registered trademarks of Intel Corporation.
Cyrix is a registered trademark of Cyrix Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
September 1996 - Revised June 12, 1997
CY2267
Pin Summary
Name
Pin
1
Description
V
Voltage supply
DD
[1]
XTALIN
XTALOUT
2
Reference crystal input
Reference crystal feedback
Ground
[1]
3
V
4
SS
CPUCLK16
CPUCLK1
CPUCLK2
5
CPU clock output
CPU clock output
CPU clock output
Voltage supply
6
7
V
8
DD
CPUCLK3
CPUCLK4
9
CPU clock output
CPU clock output
Ground
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
V
SS
CPUCLK5
CPUCLK6
CPU clock output
CPU clock output
Voltage supply
V
DD
S1
CPU clock select input, bit 1 (internal pull-up resistor to V
CPU clock output
CPU clock output
CPU clock output
CPU clock output
Ground
)
DD
CPUCLK15
CPUCLK7
CPUCLK8
CPUCLK14
V
SS
CPUCLK9
CPU clock output
CPU clock output
Ground
CPUCLK10
V
SS
CPUCLK11
CPUCLK12
CPU clock output
CPU clock output
Voltage supply
V
DD
CPUCLK13
PCICLK
CPU clock output
PCI clock output
Ground
V
SS
USBCLK
IOCLK
USB clock output, 48 MHz
I/O clock output, 24 MHz
Voltage supply
V
DD
REFCLK
Reference clock output (14.318 MHz) for ISA slots (drives C
= 45 pF)
LOAD
S2
CPU clock select input, bit 2 (internal pull-up resistor to V
)
DD
Notes:
1. For best accuracy, use a parallel-resonant crystal, CLOAD = 17 pF.
2
CY2267
Function Table
S2
S1
XTALIN
CPUCLK[1-16]
PCICLK
Hi-Z
REFCLK
Hi-Z
USBCLK
Hi-Z
IOCLK
0
0
1
1
0
1
0
1
14.318 MHz Hi-Z
Hi-Z
14.318 MHz 66.67 MHz
14.318 MHz 50.0 MHz
14.318 MHz 60.0 MHz
33.33 MHz
25.0 MHz
30.0 MHz
14.318 MHz 48 MHz
14.318 MHz 48 MHz
14.318 MHz 48 MHz
24 MHz
24 MHz
24 MHz
Actual Clock Frequency Values
Target Frequency
Actual Frequency
(MHz)
Clock Output
CPUCLK
(MHz)
PPM
50.0
66.67
60.0
48.0
24.0
49.93
66.56
60.0
–1399
–1597
0
CPUCLK
CPUCLK
[2]
USBCLK
48.008
24.004
167
IOCLK
167
Notes:
2. Meets Intel USB clock requirements.
CPU and PCI Clock Driver Strengths
Maximum Ratings
• Matched impedances on both rising and falling edges on
the output drivers
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
• Output impedance: 25Ω (typical) measured at 1.5V.
Supply Voltage ................................................. –0.5 to +7.0V
Input Voltage ..............................................–0.5V to V +0.5
DD
Storage Temperature (Non-Condensing)... –65°C to +150°C
Max. Soldering Temperature (10 sec)...................... +260°C
Junction Temperature .............................................. +150°C
Package Power Dissipation.............................................. 1W
Static Discharge Voltage........................................... >2000V
(per MIL-STD-883, Method 3015)
Operating Conditions[3]
Parameter
Description
Min.
3.135
0
Max.
3.6
Unit
V
V
Supply Voltage
DD
T
Operating Temperature, Ambient
70
°C
pF
A
C
Max. Capacitive Load on
CPUCLK
L
30
30
20
20
45
PCICLK
USBCLK
IOCLK
REFCLK
f
Reference Frequency, Oscillator Nominal Value
14.318
14.318
MHz
(REF)
Note:
3. Electrical parameters are guaranteed with these operating conditions.
3
CY2267
Electrical Characteristics V = 3.135V to 3.6V, T = 0°C to +70°C
DD
A
Parameter
Description
Test Conditions
Min.
Max.
Unit
V
V
V
V
High-level Input Voltage
Low-level Input Voltage
High-level Output Voltage
Except Crystal Inputs
Except Crystal Inputs
2.0
IH
0.8
V
IL
V
= V Min.
I
I
I
I
I
I
I
I
I
I
= 12 mA
= 12 mA
= 8 mA
CPUCLK
PCICLK
USBCLK
IOCLK
2.4
V
OH
DD
DD
OH
OH
OH
OH
OH
OL
OL
OL
OL
OL
= 8 mA
= 12 mA
= 12 mA
= 12 mA
= 8 mA
REFCLK
CPUCLK
PCICLK
USBCLK
IOCLK
V
Low-level Output Voltage
V
= V Min.
0.4
V
OL
DD
DD
= 8 mA
= 12 mA
REFCLK
I
I
I
I
Input High Current
V
V
= V
DD
10
µA
µA
µA
mA
IH
IH
IL
Input Low Current
= 0V
100
+10
180
IL
Output Leakage Current
Power Supply Current
Three-state
–10
OZ
DD
V
= 3.6V, V = 0 or V , Loaded Outputs,
DD
IN
DD
CPU clocks = 66.67 MHz
I
Power Supply Current
V
= 3.6V, V = 0 or V , Unloaded Outputs
120
mA
DD
DD
IN
DD
4
CY2267
Switching Characteristics[4]
Parameter
Output
All
Description
Test Conditions
t = t ÷ t
Min.
45
Typ.
Max.
Unit
%
[5]
t
Output Duty Cycle
50
55
1
1
1A
1B
t
t
t
t
t
CPUCLK
PCICLK
CPUCLK
PCICLK
CPUCLK
CPU Clock HIGH Time
Measured at 2.4V, 66.67 MHz
Measured at 2.4V, 33.33 MHz
Measured at 0.4V, 66.67 MHz
Measured at 0.4V, 33.33 MHz
Measured between 0.8V and 2.0V
5.0
ns
1C
1C
1D
1D
2
[6]
PCI Clock HIGH Time
CPU Clock LOW Time
12.0
5.0
ns
ns
[6]
PCI Clock LOW Time
12.0
1.0
ns
CPU Clock Rising and
Falling Edge Rate
4.0
4.0
V/ns
t
t
PCICLK
REFCLK
CPUCLK
PCI Clock Rising and
Falling Edge Rate
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
1.0
0.5
0.3
V/ns
V/ns
2
2
Reference Clock Rising
and Falling Edge Rate
t
t
CPU Clock Rise Time
1.2
1.2
ns
ns
3
USBCLK,
IOCLK
USB Clock and I/O Clock Measured between 0.8V and 2.0V
Rise Time
3
t
t
CPUCLK
CPU Clock Fall Time
Measured between 2.0V and 0.8V
0.3
1.0
1.2
1.2
ns
ns
4
USBCLK,
IOCLK
USB Clock and I/O Clock Measured between 2.0V and 0.8V
Fall Time
4
t
t
CPUCLK
CPU-CPU Clock Skew
Measured at 1.5V
Measured at 1.5V
100
2.0
250
3.0
ps
ns
5
CPUCLK, CPU-PCI Clock Skew
6
PCICLK
(CY2267–1)
t
t
CPUCLK
Cycle-Cycle Clock Jitter CPU Clock jitter
200
500
ps
ps
7
USBCLK,
IOCLK,
Cycle-Cycle Clock Jitter USB Clock, I/O Clock, and PCI
Clock jitter
7
PCICLK
t
t
CPUCLK
Power-up Time
Power-up Time
CPU clock stabilization from
power-up
2
2
ms
ms
8
PCICLK
PCI clock stabilization from
power-up
8
Notes:
4. All parameters specified with loaded outputs.
5. Duty cycle is measured at 1.5V.
6. A LOW and HIGH time of 12 ns corresponds to a PCICLK frequency of 33.33 MHz. For PCICLK frequencies of 30 MHz and 25 MHz, the LOW and HIGH
times are each respectively 13.33 ns and 16 ns.
Switching Waveforms
Duty Cycle Timing
t
1B
t
1A
1.5V
1.5V
1.5V
2267–c
5
CY2267
Switching Waveforms (continued)
CPUCLK Outputs HIGH/LOW Time
t
1C
3.3V
0V
2.4V
2.4V
0.4V
OUTPUT
0.4V
2267–d
t
1D
All Outputs Rise/Fall Time
3.3V
0V
2.0V
0.8V
2.0V
0.8V
OUTPUT
t
2
t
3
t
2
t
4
2267–e
Clock Skew
1.5V
CPUCLK–CPUCLK
1.5V
2267–f
t
5
CPU-PCI Clock Skew
1.5V
CPUCLK
PCICLK
1.5V
2267–g
t
6
6
CY2267
Application Information
Clock traces must be terminated with either series or parallel termination, as they are normally done.
The Application Circuit is shown below.
Application Circuit
Summary
• A parallel-resonant crystal should be used as the reference to the clock generator. The operating frequency and C
of
LOAD
this crystal should be as specified in the data sheet. Optional trimming capacitors may be needed if a crystal with a different
is used. Footprints must be laid out for flexibility.
C
LOAD
• Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1 µF.
In some cases, smaller value capacitors may be required.
• The value of the series terminating resistor satisfiesthe following equation, where R
is the loaded characteristic impedance
trace
ofthe trace, R is theoutputimpedanceofthe clock generator(specified in the datasheet), and R
isthe seriesterminating
out
series
resistor.
R
> R
– R
series
trace out
• Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor
as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF.
• A Ferrite Bead may be used to isolate the Board V from the clock generator V island. Ensure that the Ferrite Bead offers
DD
DD
greater than 50Ω impedance at the clock frequency, under loaded DC conditions. Please refer to the application note “Layout
and Termination Techniques for Cypress Clock Generators” for more details.
• If a Ferrite Bead is used, a 10 µF– 22 µF tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor
prevents power supply droop during current surges.
7
CY2267
Test Circuit
V
DD
1
32
0.1 µF
0.1 µF
0.1 µF
4
8
29
26
V
DD
0.1 µF
23
20
11
14
0.1 µF
OUTPUTS
C
LOAD
Note: All capacitors should be placed as close to each pin as possible.
Ordering Information
Package
Operating
Range
Ordering Code
Name
Package Type
34-Pin SSOP
CY2267PVC–1
O34
Commercial
Document #: 38–00534–A
8
CY2267
Package Diagram
34-Pin Shrunk Small Outline Package O34
© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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