CY2264PVC-2 [CYPRESS]
Processor Specific Clock Generator, 75MHz, MOS, PDSO34, SSOP-34;
| 型号： | CY2264PVC-2 |
| 厂家： | 
CYPRESS |
| 描述： | Processor Specific Clock Generator, 75MHz, MOS, PDSO34, SSOP-34 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总10页 (文件大小：134K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1CY2264
fax id: 3524
PRELIMINARY
CY2264
Pentium™, Pentium Pro™, and Cyrix 6x86
Compatible Clock Synthesizer/Driver
• Smooth slewing in-system frequency changes (2
MHz/ms typical)
Features
• Complete clock solution to meet requirements of Pen-
tium™, Pentium Pro™, or Cyrix 6x86 motherboards in-
cluding dual-processor and SDRAM designs
• Doze Mode support, CPUCLK = 33.33 MHz
• 3.3V operation, 5V tolerant inputs
• Available in space-saving 34-pin SSOP package
— Eight CPU clock outputs, up to 75 MHz (seeFunction
Table)
Functional Description
— Six PCI clock outputs, synchronous or asynchro-
nous mode, pin-selectable by Bus Select input
The CY2264 is a low-cost Clock Synthesizer/Driver chip for a
Pentium, Pentium Pro, or Cyrix 6x86-based motherboard.
— One USB clock at 48 MHz, meets Intel’s accuracy,
jitter, as well as rise and fall time requirements
The CPU clocks of the CY2264 have less than 200 ps cy-
cle-to-cycle jitter. Both the CPU and PCI clocks have a slew
rate of greater than 1V/ns. The USB clock meets Intel’s accu-
racy, jitter, and rise and fall time requirements.
— One I/O clock at 24 MHz
— Two Ref. clocks at 14.318 MHz
• Three dedicated, independent Frequency Select inputs
(internal pull-up)easesystem design, enable in-system
frequency changes, and support OE control and Test
Mode
• Low CPU clock jitter ≤ 200 ps cycle-to-cycle
• Low skew outputs
All CPU clocks have a unique dual-speed frequency change
logic to support fast clock stabilization on power-up (< 2 ms)
and slow frequency changes during operation (2 MHz/ms typ-
ical). Three dedicated Frequency Select inputs facilitate the
latter, and support OE, Test Mode, and Doze Mode functional-
ity.
— ≤ 250 ps between CPU clocks
The CY2264 clock outputs are designed for low EMI emis-
sions. Controlled rise and fall times, unique output driver cir-
cuits, and innovative circuit layout techniques enable the
CY2264 to have lower EMI than clock devices from other man-
ufacturers. Please refer to the application note “Layout and
Termination Techniques for Cypress Clock Generators” for
more information on recommended system layout techniques.
— ≤ 250 ps between PCI clocks
— 1ns−4ns skew between CPU and PCI clocks (in syn-
chronousmode) for compatibility with SiS 55XX and
Intel 82430HX and 82430VX chipsets (CY2264–1)
— 500 ps typ. skew between CPU and PCI clocks (in
synchronous mode) for compatibility with ALI Alad-
din III and other chipsets (CY2264–2)
The CY2264 accepts a 14.318 MHz reference crystal or clock
as its input and runs off a 3.3V supply. The CY2264 is available
in a space-saving, low-cost 34-pin SSOP package and is
pin-compatible with the CY2265 for designs requiring addition-
al SDRAM support.
• Improved output drivers are designed for low EMI
• Meets Pentium and Pentium Pro power-upstabilization
requirements
Pin Configuration
Logic Block Diagram
Top View
REF0(14.318MHz)
SSOP
REF1(14.318MHz)
V
DD
REF0
REF1
1
2
3
4
34
33
32
31
XTALIN
14.318
MHz
OSC.
CPU
PLL
XTALIN
MUX
CPUCLK[1–8]
XTALOUT
XTALOUT
AV
DD
/2
/2
V
SS
IOCLK
ROM
S2
USBCLK
5
30
29
28
27
26
25
24
23
Delay
(–1only)
CPUCLK1
V
SS
6
S0
S1
S2
PCICLK6
PCICLK5
7
CPUCLK2
/2
8
V
DD
IOCLK(24MHz)
V
DD
CPUCLK3
CPUCLK4
9
SYS
PLL
PCICLK4
PCICLK3
10
11
12
MUX
V
SS
/2
USBCLK(48MHz)
CPUCLK5
CPUCLK6
V
SS
/3
PCICLK2
PCICLK1
13
14
22
21
20
19
18
V
DD
MUX
BSEL
V
SS
S1
S0
15
16
17
PCICLK[1–6]
BSEL
CPUCLK7
CPUCLK8
Intel is a registered trademark of Intel Corporation.
Cyrix is a registered trademark of Cyrix Corporation.
Pentium and Pentium Pro are trademarks of Intel Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
August 1996 - Revised May 27, 1997
PRELIMINARY
CY2264
Pin Summary
Name
Pin
1
Description
V
Voltage supply
DD
[1, 2]
[1]
XTALIN
2
Reference crystal input
XTALOUT
3
Reference crystal feedback
V
4
Ground
SS
S2
5
CPU clock select input, bit 2 (internal pull-up resistor to V
)
DD
CPUCLK1
CPUCLK2
6
CPU clock output
7
CPU clock output
V
8
Voltage supply
DD
CPUCLK3
CPUCLK4
9
CPU clock output
10
11
12
13
14
15
16
17
18
19
CPU clock output
V
Ground
SS
CPUCLK5
CPUCLK6
CPU clock output
CPU clock output
V
Voltage supply
DD
S1
CPU clock select input, bit 1 (internal pull-up resistor to V
CPU clock select input, bit 0 (internal pull-up resistor to V
CPU clock output
)
)
DD
DD
S0
CPUCLK7
CPUCLK8
BSEL
CPU clock output
Bus Select Input, selects asynchronous or synchronous PCI clocks. See Function Table.
(internal pull-up resistor to V
)
DD
V
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Ground
SS
PCICLK1
PCICLK2
PCI clock output
PCI clock output
Ground
V
SS
PCICLK3
PCICLK4
PCI clock output
PCI clock output
Voltage supply
V
DD
PCICLK5
PCICLK6
PCI clock output
PCI clock output
Ground
V
SS
USBCLK
IOCLK
USB clock output, 48 MHz
I/O clock output, 24 MHz
Analog voltage supply
AV
DD
REF1
Reference clock output (14.318 MHz)
REF0
Reference clock output (14.318 MHz) for ISA slots (drives C
= 45 pF)
LOAD
Notes:
1. For best accuracy, use a parallel-resonant crystal, CLOAD = 12 pF.
2. TCLK is a test clock on the XTALIN input during test mode.
2
PRELIMINARY
CY2264
Function Table
PCICLK[1-6] PCICLK[1:6]
S2
S1
S0
XTALIN
CPUCLK[1-8]
BSEL = 1
16.67 MHz
37.5 MHz
27.5 MHz
Hi-Z
BSEL = 0
32 MHz
32 MHz
32 MHz
Hi-Z
REF[0-1]
14.318 MHz
14.318 MHz
14.318 MHz
Hi-Z
USBCLK
48 MHz
48 MHz
48 MHz
Hi-Z
IOCLK
24 MHz
24 MHz
24 MHz
Hi-Z
0
0
0
14.318 MHz 33.33 MHz
14.318 MHz 75.0 MHz
14.318 MHz 55.0 MHz
14.318 MHz Hi-Z
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
14.318 MHz 50.0 MHz
14.318 MHz 66.67 MHz
25.0 MHz
33.33 MHz
30.0 MHz
TCLK/4
32 MHz
32 MHz
32 MHz
TCLK/3
14.318 MHz
14.318 MHz
14.318 MHz
TCLK
48 MHz
48 MHz
48 MHz
TCLK/2
24 MHz
24 MHz
24 MHz
TCLK/4
14.318 MHz 60.0 MHz
[3]
TCLK
TCLK/2
Actual Clock Frequency Values
Target Frequency
Actual Frequency
(MHz)
Clock Output
CPUCLK
(MHz)
PPM
33.33
75.0
55.0
50.0
66.67
60.0
32.0
48.0
24.0
33.28
75.0
–1597
0
CPUCLK
CPUCLK
CPUCLK
CPUCLK
CPUCLK
54.98
49.93
66.56
60.0
–331
–1399
–1597
0
[4]
PCICLK
32.005
48.008
24.004
167
[5]
USBCLK
167
IOCLK
167
Notes:
3. TCLK is supplied on XTALIN pin.
4. If BSEL = 1, the PPM on PCICLK will be the same as on CPUCLK.
5. Meets Intel USB clock requirements.
CPU and PCI Clock Driver Strengths
Maximum Ratings
• Matched impedances on both rising and falling edges on
the output drivers
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
• Output impedance: 25Ω (typical) measured at 1.5V.
Supply Voltage ................................................. –0.5 to +7.0V
Input Voltage ..............................................–0.5V to V +0.5
DD
Storage Temperature (Non-Condensing) ... –65°C to +150°C
Max. Soldering Temperature (10 sec) ...................... +260°C
Junction Temperature............................................... +150°C
Package Power Dissipation.............................................. 1W
Static Discharge Voltage ........................................... >2000V
(per MIL-STD-883, Method 3015)
3
PRELIMINARY
CY2264
Operating Conditions[6]
Parameter
Description
Min.
3.135
0
Max.
3.6
Unit
V
V
Supply Voltage
DD
T
Operating Temperature, Ambient
70
°C
pF
A
C
Max. Capacitive Load on
CPUCLK
PCICLK
L
30
30
20
20
45
15
USBCLK
IOCLK
REF0
REF1
f
Reference Frequency, Oscillator Nominal Value
14.318
14.318
MHz
(REF)
Electrical Characteristics V = 3.135V to 3.6V, T = 0°C to +70°C
DD
A
Parameter
Description
Test Conditions
Min.
Max.
Unit
V
V
V
High-level Input Voltage
Low-level Input Voltage
High-level Output Voltage
Except Crystal Inputs
Except Crystal Inputs
2.0
V
V
V
IH
0.8
IL
V
= V Min.
I
I
I
I
I
I
I
I
I
I
I
I
= 12 mA
= 12 mA
= 8 mA
= 8 mA
= 12 mA
= 8 mA
= 12 mA
= 12 mA
= 8 mA
= 8 mA
= 12 mA
= 8 mA
CPUCLK
PCICLK
USBCLK
IOCLK
REF0
2.4
OH
DD
DD
OH
OH
OH
OH
OH
OH
OL
OL
OL
OL
OL
OL
REF1
V
Low-level Output Voltage
V
= V Min.
CPUCLK
PCICLK
USBCLK
IOCLK
REF0
0.4
V
OL
DD
DD
REF1
I
I
I
I
Input High Current
V
V
= V
DD
5
µA
µA
µA
mA
IH
IH
IL
Input Low Current
= 0V
100
+10
140
IL
Output Leakage Current
Power Supply Current
Three-state
–10
OZ
DD
V
= 3.6V, V = 0 or V , Loaded Outputs,
DD
IN
DD
CPU clocks = 66.67 MHz
I
Power Supply Current
V
= 3.6V, V = 0 or V , Unloaded Outputs
90
mA
DD
DD
IN
DD
Note:
6. Electrical parameters are guaranteed with these operating conditions.
4
PRELIMINARY
CY2264
Switching Characteristics (CY2264-1) [7]
Parameter
Output
All
Description
Test Conditions
t = t ÷ t
Min.
45
Typ.
Max.
Unit
%
[8]
t
Output Duty Cycle
CPU Clock HIGH Time
50
55
1
1
1A
1B
t
t
t
t
t
CPUCLK
PCICLK
CPUCLK
PCICLK
CPUCLK
Measured at 2.4V, 66.67 MHz
Measured at 2.4V, 33.33 MHz
Measured at 0.4V, 66.67 MHz
Measured at 0.4V, 33.33 MHz
Measured between 0.8V and 2.0V
5.0
ns
1C
1C
1D
1D
2
[9]
PCI Clock HIGH Time
CPU Clock LOW Time
12.0
5.0
ns
ns
[9]
PCI Clock LOW Time
12.0
1.0
ns
CPU Clock Rising and
Falling Edge Rate
4.0
4.0
V/ns
t
t
PCICLK
PCI Clock Rising and
Falling Edge Rate
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
1.0
0.5
0.3
V/ns
V/ns
2
2
REF0,
REF1
Reference Clock Rising
and Falling Edge Rate
t
t
CPUCLK
CPU Clock Rise Time
1.2
1.2
ns
ns
3
3
USBCLK,
IOCLK
USB Clock and I/O Clock Measured between 0.8V and 2.0V
Rise Time
t
t
CPUCLK
CPU Clock Fall Time
Measured between 2.0V and 0.8V
0.3
1.0
1.2
1.2
ns
ns
4
4
USBCLK,
IOCLK
USB Clock and I/O Clock Measured between 2.0V and 0.8V
Fall Time
t
t
t
CPUCLK
PCICLK
CPU-CPU Clock Skew
PCI-PCI Clock Skew
Measured at 1.5V
Measured at 1.5V
Measured at 1.5V
100
100
2.5
250
250
4.0
ps
ps
ns
5
6
7
[10]
CPUCLK, CPU-PCI Clock Skew
PCICLK
(CY2264–1)
t
t
CPUCLK
Cycle-Cycle Clock Jitter CPU Clock jitter
200
500
ps
ps
8
8
USBCLK,
IOCLK,
Cycle-Cycle Clock Jitter USB Clock, I/O Clock, and PCI
Clock jitter
PCICLK
t
t
t
CPUCLK
PCICLK
CPUCLK
Power-up Time
CPU clock stabilization from
power-up
2
2
ms
ms
9
Power-up Time
PCI clock stabilization from
power-up
10
11
Frequency Slew Rate
Rate of change of frequency
0.1
2
10
MHz/
ms
Notes:
7. All parameters specified with loaded outputs.
8. Duty cycle is measured at 1.5V.
9. A LOW and HIGH time of 12 ns corresponds to a PCICLK frequency of 33.33 MHz. For PCICLK frequencies of 30 MHz and 25 MHz, the LOW and HIGH
times are each respectively 13.33 ns and 16 ns.
10. Synchronous PCI Mode only.
5
PRELIMINARY
CY2264
Switching Characteristics (CY2264-2) [7]
Parameter
Output
All
Description
Test Conditions
t = t ÷ t
Min.
45
Typ.
Max.
Unit
%
[8]
t
Output Duty Cycle
CPU Clock HIGH Time
50
55
1
1
1A
1B
t
t
t
t
t
CPUCLK
PCICLK
CPUCLK
PCICLK
CPUCLK
Measured at 2.4V, 66.67 MHz
Measured at 2.4V, 33.33 MHz
Measured at 0.4V, 66.67 MHz
Measured at 0.4V, 33.33 MHz
Measured between 0.8V and 2.0V
5.0
ns
1C
1C
1D
1D
2
[9]
PCI Clock HIGH Time
CPU Clock LOW Time
12.0
5.0
ns
ns
[9]
PCI Clock LOW Time
12.0
1.0
ns
CPU Clock Rising and
Falling Edge Rate
4.0
4.0
V/ns
t
t
PCICLK
PCI Clock Rising and
Falling Edge Rate
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
1.0
0.5
0.3
V/ns
V/ns
2
2
REF0,
REF1
Reference Clock Rising
and Falling Edge Rate
t
t
CPUCLK
CPU Clock Rise Time
1.2
1.2
ns
ns
3
3
USBCLK,
IOCLK
USB Clock and I/O Clock Measured between 0.8V and 2.0V
Rise Time
t
t
CPUCLK
CPU Clock Fall Time
Measured between 2.0V and 0.8V
0.3
1.2
1.2
ns
ns
4
4
USBCLK,
IOCLK
USB Clock and I/O Clock Measured between 2.0V and 0.8V
Fall Time
t
t
t
CPU-
CLK[1:6]
CPU-CPU Clock Skew
Measured at 1.5V
Measured at 1.5V
Measured at 1.5V
100
200
150
100
300
ps
ps
ps
5
5
5
CPU-
CLK[7:8]
CPU-CPU Clock Skew
CPUCLK
CPU[1:6] - CPU[7:8]
Clock Skew
100
100
t
t
PCICLK
PCI-PCI Clock Skew
Measured at 1.5V
Measured at 1.5V
100
500
250
900
ps
ps
6
7
[10]
CPUCLK, CPU-PCI Clock Skew
PCICLK
t
t
CPUCLK
Cycle-Cycle Clock Jitter CPU Clock jitter
200
500
ps
ps
8
8
USBCLK,
IOCLK,
Cycle-Cycle Clock Jitter USB Clock, I/O Clock, and PCI
Clock jitter
PCICLK
t
t
t
CPUCLK
PCICLK
CPUCLK
Power-up Time
CPU clock stabilization from
power-up
2
2
ms
ms
9
Power-up Time
PCI clock stabilization from
power-up
10
11
Frequency Slew Rate
Rate of change of frequency
0.1
2
10
MHz/
ms
6
PRELIMINARY
CY2264
Switching Waveforms
Duty Cycle Timing
t
1B
t
1A
1.5V
1.5V
1.5V
CPUCLK Outputs HIGH/LOW Time
t
1C
3.3V
0V
2.4V
2.4V
0.4V
OUTPUT
0.4V
t
1D
All Outputs Rise/Fall Time
3.3V
0V
2.0V
2.0V
0.8V
OUTPUT
0.8V
t
2
t
3
t
2
t
4
Clock Skew
1.5V
CPUCLK–CPUCLK
OR
PCICLK–PCICLK
1.5V
t
5
t
6
CPU-PCI Clock Skew
1.5V
CPUCLK
PCICLK
1.5V
t
7
7
PRELIMINARY
CY2264
The Application Circuit is shown below.
Application Information
Clock traces must be terminated with either series or parallel
termination, as they are normally done.
Application Circuit
Summary
• A parallel-resonant crystal should be used as the reference to the clock generator. The operating frequency and C
of
LOAD
this crystal should be as specified in the data sheet. Optional trimming capacitors may be needed if a crystal with a different
is used. Footprints must be laid out for flexibility.
C
LOAD
• Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1 µF.
In some cases, smaller value capacitors may be required.
• The valueof the series terminating resistor satisfies thefollowingequation, where R
is the loaded characteristic impedance
trace
of the trace, R istheoutput impedance of the clock generator (specified in thedatasheet), and R
isthe seriesterminating
out
series
resistor.
R
> R
– R
trace out
series
• Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor
as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF.
• A Ferrite Bead may be used to isolate the Board V from the clock generator V island. Ensure that the Ferrite Bead offers
DD
DD
greater than 50Ω impedance at the clock frequency, under loaded DC conditions. Please refer to the application note “Layout
and Termination Techniques for Cypress Clock Generators” for more details.
• If a Ferrite Bead is used, a 10 µF– 22 µF tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor
prevents power supply droop during current surges.
8
PRELIMINARY
CY2264
Test Circuit
V
DD
22Ω
1
32
22 µF
0.1 µF
0.1 µF
4
8
29
26
V
DD
0.1 µF
0.1 µF
23
20
11
14
0.1 µF
OUTPUTS
C
LOAD
Note: All capacitorsshould be placed as close to each pin as possible.
Ordering Information
Package
Operating
Range
Ordering Code
CY2264PVC–1
CY2264PVC–2
Name
Package Type
34-Pin SSOP
34-Pin SSOP
O34
Commercial
Commercial
O34
Document #: 38–00520–A
9
PRELIMINARY
CY2264
Package Diagram
34-Pin Shrunk Small Outline Package
© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of anycircuitry other than circuitry embodied in a CypressSemiconductor product. Nor does it conveyor imply any license under patent or other rights. CypressSemiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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