CY2220-2_技术文档

0

CY2220

133-MHz Spread Spectrum Clock Synthesizer/Driver

with Differential CPU Outputs

Features

Benefits

• Compliant to Intel^®CK00 Clock Synthesizer/Driver

Supports next generation Pentium^®processors using differen-

Specifications

tial clock drivers

• Multiple output clocks at different frequencies

—Four pairs of differential CPU outputs, up to 133 MHz

—Ten synchronous PCI clocks

Motherboard clock generator

—Support Multiple CPUs and a chipset

—Support for PCI slots and chipset

—Two Memory Reference clocks, 180 degrees out of

—Drives up to two Direct Rambus^™Clock Generators

phase

(DRCG)

—Four AGP and Hub Link clocks at 66 MHz

—Two 48-MHz clocks

—Supports USB host controller and SuperI/O chip

—Supports ISA slots and I/O chip

—Two reference clocks at 14.318 MHz

• Spread Spectrum clocking

Enables reduction of EMI and overall system cost

—31 kHz modulation frequency

—Default is –0.6%, which is recommended by Intel

• Power-down features

Enables ACPI compliant designs

• Three Select inputs

Supports up to eight CPU clock frequencies

Meets tight system timing requirements at high frequency

Enables ATE and “bed of nails” testing

• Low-skew and low-jitter outputs

• OE and Test Mode support

• 56-pin SSOP package

Widely available, standard package enables lower cost

Pin Configuration

Logic Block Diagram

SSOP

Top View

V

DDMEM

1

2

3

4

5

6

56

55

54

V

SSREF

REFCLK [0–1]

CPUCLK [0–3]

MemRef

REFCLK0/MultSel_0

REFCLK1/MultSel_1

MemRefB

V

53

52

51

50

SSMEM

DDREF

MultSel0

MultSel1

SPREAD

XTALIN

XTALOUT

V

CPUCLK_3

CPUCLK_3B

SSPCI

7

V

PCICLK_0

PCICLK_1

49

48

47

46

45

44

43

42

41

DDCPU

8

CPUCLKB [0–3]

XTALIN

14.318

MHz

OSC.

Divider

and

Stop Logic

CPU

PLL

9

CPUCLK_2

CPUCLK_2B

V

DDPCI

10

11

XTALOUT

MemRef, MemRefB

V

PCICLK_2

PCICLK_3

SSCPU

CPUCLK_1

12

13

SELA

SELB

SEL133

V

CPUCLK_1B

SSPCI

PCICLK [0–9] (33.33 MHz)

EPROM

V

14

15

16

17

18

PCICLK_4

PCICLK_5

DDCPU

CPUCLK_0

V

DDPCI

CPUCLK_0B

SPREAD

PWR_DWN

V

40

39

38

37

36

35

34

PCICLK_6

PCICLK_7

SSCPU

3V66 [0–3] (66.67 MHz)

I

REF

V

SSPCI

19

20

AV

DD

SS

PCICLK_8

PCICLK_9

SYS

PLL

USBCLK [0-1] (48 MHz)

V

21

22

23

24

25

DD3V66

3V66_3

3V66_2

V

DDPCI

Sel133

V

33

32

31

30

29

SSUSB

SS3V66

USBCLK0/SelA

USBCLK1/SelB

V

SS3V66

3V66_1

3V66_0

26

27

28

V

DDUSB

PWR_DWN

V

DD3V66

Intel and Pentium are registered trademarks of Intel Corporation.

Direct Rambus is a trademark of Rambus, Inc.

Cypress Semiconductor Corporation

Document #: 38-07206 Rev. *A

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Revised December 30, 2002

CY2220

Pin Summary

Name

Pins

Description

V_SSREF

1

3.3V Reference ground

V_DDREF

4

3.3V Reference voltage supply

3.3V PCI ground

V_SSPCI

7, 13, 19

V_DDPCI

10, 16, 22

3.3V PCI voltage supply

3.3V AGP and Hub Link ground

3.3V AGP and Hub Link voltage supply

3.3V USB ground

V_SS3V66

V_DD3V66

V_SSUSB

32, 33

29, 36

24

V_DDUSB

27

3.3V USB voltage supply

3.3V CPU ground

V_SSCPU

40, 46

V_DDCPU

V_SSMEM

V_DDMEM

AV_SS

43, 49

3.3V CPU voltage supply

3.3V Memory ground

53

56

3.3V Memory voltage supply

Analog ground for PLL and Core

Analog voltage supply to PLL and Core

Reference current for external biasing

Reference crystal input

37

AV_DD

38

I_REF

39

XTALIN^[1]

XTALOUT^[1]

CPUCLK [0–3]

CPUCLK [0–3]B

PCICLK [0–9]

5

6

Reference crystal feedback

CPU clock outputs

42, 45, 48, 51

41, 44, 47, 50

Inverse CPU clock outputs

8, 9, 11, 12, 14, 15, 17,

18, 20, 21

PCI clock outputs, synchronously running at 33.33 MHz

MemRef

55

MemRef clock output, drives memory clock generator

MemRefB clock output 180 degrees out of phase with MemRef

AGP and Hub Link clock outputs, running at 66 MHz

MemRefB

54

3V66_ [0–3]

30, 31, 34, 35

25, 26

USBCLK [0–1]/Sel[A–B]

Sel [A–B] inputs are sensed then internally latched on power-up be-

fore the pins are used for 48-MHz USB clock outputs

REFCLK[0–1]/MultSel[0–1] 2, 3

MultSel[0–1] inputs are sensed then internally latched on power-up

before the pins are Reference clock outputs, 14.318 MHz

PWR_DWN

SPREAD^[2]

28

52

23

Active LOW input, powers down part when asserted

Active LOW input, enables spread spectrum when asserted

CPU frequency select input (See Function Table)

SEL133

Notes:

1. For best accuracy, use a parallel-resonant crystal, C_LOAD= 18 pF. For crystals with different C_LOAD, please refer to the application note, “Crystal Oscillator

Topics.”

2. Input is static HIGH or LOW. Frequency of toggling cannot exceed 30 MHz.

Document #: 38-07206 Rev. *A

Page 2 of 11

CY2220

Function Table^[3]

CPUCLK

(MHz)

MemRef

(MHz)

3V66CLK

(MHz)

PCICLK

(MHz)

USBCLK

(MHz)

REFCLK

(MHz)

SEL133

SELA

SELB

0

1

0

1

0

1

0

1

0

1

0

1

0

1

100

N/A

50

N/A

66

N/A

33

N/A

48

N/A

14.318

N/A

Hi-Z

133

Hi-Z

66

Hi-Z

66

Hi-Z

33

Hi-Z

48

Hi-Z

14.318

N/A

TCLK/2

TCLK/4

TCLK/8

TCLK/2

TCLK

Actual Clock Frequency Values

CY2220-1

CY2220-2

Target

Frequency

(MHz)

Clock

Actual Frequency

(MHz)

Actual Frequency

(MHz)

Output

PPM

+2270

+2022

167

CPUCLK

USBCLK

100

133

48

99.126

132.769

48.008

–8741

–1740

167

100.227

133.269

48.008

Swing Select Functions

Output

Current

V_OH@ Z,

Iref = 2.32 mA

MultSel0

MultSel1

Board Target

Reference R, I_{REF =}

0

1

0

1

60Ω

Rr = 475 ± 1%,

Iref = 2.32 mA

I_OH= 5*Iref

I_OH= 6*Iref

I_OH= 4*Iref

I_OH= 7*Iref

0.71 @ 60

0.59 @ 50

0.85 @ 60

0.71 @ 50

0.56 @ 60

0.47 @ 50

0.99 @ 60

0.82 @ 50

0

1

50Ω

60Ω

50Ω

60Ω

50Ω

60Ω

50Ω

Rr = 475 ± 1%,

Iref = 2.32 mA

Rr = 475 ± 1%,

Iref = 2.32 mA

Rr = 475 ± 1%,

Iref = 2.32 mA

Rr = 475 ± 1%,

Iref = 2.32 mA

Rr = 475 ± 1%,

Iref = 2.32 mA

Rr = 475 ± 1%,

Iref = 2.32 mA

Rr = 475 ± 1%,

Iref = 2.32 mA

Clock Driver Impedances

Impedance

Minimum

Typical

Maximum

Buffer Name

CPUCLK, CPUCLKB

USB, REF

V

_DDRange

Buffer Type

Type X1

Type 3

Ω

3.135–3.465

20

12

40

30

60

55

PCI, 3V66

Type 5

MemRef, MemRefB

Type 5

Note:

3. TCLK is a test clock driven in on the XTALIN input in test mode.

Document #: 38-07206 Rev. *A

Page 3 of 11

CY2220

Storage Temperature (Non-Condensing).......–65°C to +150°C

Maximum Ratings

Junction Temperature..................................................

+150°C

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Package Power Dissipation................................................1W

Supply Voltage....................................................–0.5 to +7.0V

Input Voltage...............................................–0.5V to V_DD+ 0.5

Static Discharge Voltage

(per JEDEC EIA/JESD22-A114-A)................................2000V

Operating Conditions Over which Electrical Parameters are Guaranteed

Parameter

Description

3.3V Supply Voltages

Min.

Max.

Unit

V

_DDREF, V_DDPCI, AV_DD

,

3.135

3.465

V

V_DD3V66, V_DDUSB,V_DDCPU,

V_DDMEM

T_A

Operating Temperature, Ambient

Input Pin Capacitance Nominal Value

XTAL Pin Capacitance

0

70

°C

pF

C_in

18 pF

22.5

C_XTAL

C_L

Max. Capacitive Load on

MemRef, USBCLK, REF

PCICLK, 3V66

20

30

f_(REF)

t_PU

Reference Frequency, Oscillator Nominal Value

14.318

0.05

14.318

MHz

ms

Power-up time for all VDD's to reach minimum

specified voltage (power ramps must be monotonic)

50

Electrical Characteristics Over the Operating Range

Parameter

V_IH

Description

Test Conditions

Min. Max. Unit

High-level Input Voltage

Low-level Input Voltage

Except Crystal Pads. Threshold voltage for crystal pads = V_DD/2

Except Crystal Pads

2.0

V

V_IL

0.8

V_OH

High-level Output Voltage MemRef, USB, REF, 3V66

I_OH= –1 mA

_OH= –1 mA

I_OL= 1 mA

_OL= 1 mA

2.4

V

PCI

I

V

V_OL

Low-level Output Voltage MemRef, USB, REF, 3V66

PCI

0.4

0.55

5

V

I

V

I_IH

I_IL

Input High Current

Input Low Current

0 < V_IN< V_DD

–5

µA

5

I_OH

High-level Output Current CPU

For I_OH=6*IRef Configuration

Type X1, V_OH= 0.65V –12.9 –14.9 mA

USB, REF

Type 3, V_OH= 2.4V

Type 5, V_OH= 2.4V

Type 3, V_OL= 0.4V

Type 5, V_OL=0.4 V

–15 –51

–30 –100

3V66, PCI, MemRef, MemRefB

I_OL

Low-level Output Current USB, REF

10

20

24

49

10

mA

3V66, PCI, MemRef, MemRefB

Three-state

I_OZ

Output Leakage Current

µA

I_DD3

3.3V Power Supply Current AV_DD/V_DD33= 3.465V, F_CPU= 133 MHz

3.3V Shutdown Current AV_DD/V_DDQ3= 3.465V

250 mA

60 mA

I_DDPD3

Document #: 38-07206 Rev. *A

Page 4 of 11

CY2220

-

Switching Characteristics^[4]Over the Operating Range

Parameter

t₁

Output

Description

Output Duty Cycle^[5]

Rise Time

Test Conditions

Min.

45

Max.

55

Unit

%

All

t_1A/(t_1B)

t₂

CPU

Measured at 20% to 80% of V_OH

Between 0.4V and 2.4V

175

0.5

1.0

700

2.0

ps

USB, REF

Rising Edge Rate

V/ns

PCI, 3V66,

MemRef

Between 0.4V and 2.4V

4.0

t₃

CPU

Fall Time

Measured at 80% to 20% of V_OH

Between 2.4V and 0.4V

175

0.5

1.0

700

2.0

4.0

ps

USB, REF

Falling Edge Rate

V/ns

PCI, 3V66,

MemRef

Between 2.4V and 0.4V

t₄

t₅

t₆

t₇

t₈

CPU

CPU-CPU Skew

Measured at Crossover

Measured at 1.5V

150

250

500

3.5

ps

ns

ps

3V66

PCI

3V66-3V66 Skew

PCI-PCI Skew

Measured at 1.5V

3V66,PCI

CPU

3V66-PCI Clock Skew

Cycle-Cycle Clock Jitter

3V66 leads. Measured at 1.5V

1.5

Measured at Crossover t₈= t_8A– t_8B

With all outputs running

200

t₉

Mref

Cycle-Cycle Clock Jitter

Settle Time

Measured at 1.5V t₉= t_9A– t_9B

250

300

350

500

1000

3

ps

ms

3V66

USB

PCI

REF

CPU, PCI

CPU and PCI clock stabilization from

power-up

CPU

Rise/Fall Matching

Overshoot

Measured with test loads^{[6, 7]}

Measured with test loads^[7]

20%

V_OH

0.2

+

V

CPU

Undershoot

Measured with test loads^[7]

–0.2

0.65

0.0

V

V_oh

High-level Output Voltage

Low-level Output Voltage

Crossover Voltage

0.74

0.05

V_ol

V_crossover

45%

of

55%

of

V_OH

Notes:

4. All parameters specified with loaded outputs. Parameters not tested in production, but are guaranteed by design characterization.

5. Duty cycle is measured at 1.5V with V_DDat 3.3V on all output except CPU. Duty Cycle on CPU is measured at V_Crossover

.

6. Determined as a fraction of 2*(t_RP– t_RN)/(t_RP+ t_RN)Where t_RPis a rising edge and t_RNis an intersecting falling edge.

7. The test load is specified in test circuit.

Document #: 38-07206 Rev. *A

Page 5 of 11

CY2220

Switching Waveforms

Duty Cycle Timing

(Single Ended Output)

t

1B

t

1A

Duty Cycle Timing (CPU Differential Output)

t

1B

t

1A

All Outputs Rise/Fall Time

V

OH

OUTPUT

0V

t

2

t

3

CPU-CPU Clock Skew

Host_b

Host

Host_b

Host

t

4

3V66-3V66 Clock Skew

3V66

t₅

Document #: 38-07206 Rev. *A

Page 6 of 11

CY2220

Switching Waveforms (continued)

PCI-PCI Clock Skew

PCI

t

6

3V66-PCI Clock Skew

3V66

PCI

t

7

CPU Clock Cycle-Cycle Jitter

t

8A

8B

Host_b

Host

Cycle-Cycle Clock Jitter

t

9A

9B

CLK

PWR_DOWN^[8]

CPUCLK

(Internal)

PCICLK

(Internal)

PWR_DWN

CPUCLK

(External)

PCICLK

(External)

VCO

Crystal

Note:

8. Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock.

Document #: 38-07206 Rev. *A

Page 7 of 11

CY2220

Test Circuit^{[9, 10]}

Rs 33.2Ω

Rp 49.9Ω

V_DDPCI, V_DD3V66

V_DDUSB, V_DDREF

AV_DD,V_DDCPU

V_DDMRef

,

1, 7, 13, 19, 24, 32, 33, 37, 40, 46, 53

4, 10, 16, 22, 27, 29, 36, 38, 43, 49, 56

CY2220

,

R_p

R_s

Ref, USB Outputs

CPU

OUTPUTS

Test Node

Test

Nodes

20 pF

PCI, 3V66, MRef Outputs

R_s

Test Node

R_p

30 pF

Ordering Information

Package

Operating

Range

Ordering Code

CY2220PVC-1

Name

Package Type

56-Pin SSOP

O56

Commercial

CY2220PVC-2

O56

Notes:

9. Each supply pin must have an individual decoupling capacitor.

10. All capacitors must be placed as close to the pins as is physically possible.

Document #: 38-07206 Rev. *A

Page 8 of 11

CY2220

Layout Example

+3.3V Supply

FB

VDDQ3

10 µF

0.005 µF

C3

C4

G

1

56

55

54

53

2

3

4

G

V

5

52

6

7

8

9

10

11

12

51

50

49

48

47

46

45

V

G

V

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

V

G

V

G

V

G

V

G

FB = Dale ILB1206 - 300 (30Ω @ 100 MHz)

µF

C4 = 0.005

µF

Cermaic Caps C3 = 10–22

= VIA to GND plane layer

V =VIA to respective supply plane layer

G

Note: Each supply plane or strip should have a ferrite bead and capacitors

All bypass caps = 0.01 µF ceramic

Document #: 38-07206 Rev. *A

Page 9 of 11

CY2220

Package Diagram

56-Lead Shrunk Small Outline Package O56

51-85062-*C

Document #: 38-07206 Rev. *A

Page 10 of 11

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

CY2220

Document Title: CY2220 133-MHz Spread Spectrum Clock Synthesizer/Driver with Differential CPU Outputs

Document Number: 38-07206

Issue

Orig. of

Change

REV.

**

ECN NO.

111730

Date

Description of Change

01/17/02

12/30/02

DSG

RBI

Change from Spec number: 38-00813 to 38-07206

Power up requirements added to Operating Conditions Information

*A

121841

Document #: 38-07206 Rev. *A

Page 11 of 11


型号：	CY2220-2
厂家：	CYPRESS
描述：	133-MHz Spread Spectrum Clock Synthesizer/Driver With Differential CPU Outputs 133 - MHz的扩频时钟合成器/驱动器，具有差分输出的CPU 驱动器时钟
文件：	总11页 (文件大小：130K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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