CY2037-311WAF-IL [CYPRESS]
Clock Generator, 133MHz, CMOS, WAFER-11;
| 型号： | CY2037-311WAF-IL |
| 厂家： | 
CYPRESS |
| 描述： | Clock Generator, 133MHz, CMOS, WAFER-11 时钟 外围集成电路 晶体 |
| 文件： | 总16页 (文件大小：473K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY2037
High Accuracy EPROM Programmable
PLL Die for Crystal Oscillators
High Accuracy EPROM Programmable PLL Die for Crystal Oscillators
Features
Functional Description
■ Erasable programmable read only memory (EPROM) -
programmable die for in-package programming of crystal
oscillators
CY2037 is an EPROM-programmable, high accuracy,
PLL-based die designed for the crystal oscillator market. The die
attaches directly to a low cost 10 to 30 MHz crystal and can be
packaged into a 4-pin through-hole or surface mount packages.
The oscillator devices may be stocked as blank parts and custom
frequencies programmed in-package at the last stage before
shipping. This enables fast-turn manufacture of custom and
standard crystal oscillators without the need for dedicated,
expensive crystals.
■ High resolution Phase locked loop (PLL) with 12-bit multiplier
and 10-bit divider
■ EPROM programmable capacitor tuning array with optional
shadow register
■ Twice programmable die
CY2037 contains an on-chip oscillator and a unique oscillator
tuning circuit for fine-tuning of the output frequency. The crystal
■ Simple 2-wire programming interface
C
load may be selectively adjusted by programming a set of seven
■ On-chip oscillator runs from 10 MHz to 30 MHz fundamental
tuned crystal
EPROM bits. This feature is used to compensate for crystal
variations or to obtain a more accurate synthesized frequency.
■ EPROM-selectable Transistor transistor logic (TTL) or
Complementarymetaloxidesemiconductor(CMOS)dutycycle
levels
CY2037 uses EPROM programming with a simple 2-wire, 4-pin
interface that includes VSS and VDD. Clock outputs may be
generated up to 133 MHz at 5 V or up to 100 MHz at 3.3 V. The
entire configuration can be reprogrammed once, which allows
the programmed inventory to be altered or reused.
■ Operating frequency:
❐ 1 MHz to 133 MHz at 5 V
❐ 1 MHz to 100 MHz at 3.3 V
❐ 1 MHz to 66.6 MHz at 2.7 V
CY2037 PLL die is designed for very high resolution. It has a
12-bit feedback counter multiplier and a 10-bit reference counter
divider. This enables the synthesis of highly accurate and stable
output clock frequencies with zero or low PPM error. The clock
is further modified by eight output divider options of 1, 2, 4, 8, 16,
32, 64, and 128. The divider input can be selected as the PLL or
crystal oscillator output, providing a total of 16 separate output
options. For further flexibility, the ouput is selectable between
TTL and CMOS duty cycle levels.
■ Eight selectable post divide options, using PLL or reference
oscillator output
■ Programmable asynchronous or synchronous OE and
power-down (PD#) modes(CY2037 and CY2037-2)
■ Frequency select (CY2037-3)
CY2037 also contain flexible power management controls.
These parts include both power down (PD#) and output enable
(OE) features with integrated pull-up resistors. The PD# and OE
modes have an additional setting to determine timing
(asynchronous or synchronous) with respect to the output signal.
When PD# or OE modes are enabled, CLKOUT is tri-stated and
pulled low by a weak pull-down. In PD# mode, all active circuitry
on chip get shutdown, where in OE mode PLL and oscillator
remain operating.
■ Low jitter outputs typically:
❐ < ± 100 ps (pk-pk) at 5 V and f > 33 MHz
❐ < ± 125 ps (pk-pk) at 3.3 V and f > 33 MHz
■ 3.3 V or 5 V operation
■ Small die
■ Controlled rise and fall times and output slew rate
Controlled rise and fall times, unique output driver circuits, and
innovative circuit layout techniques enable CY2037 to have low
jitter and accurate outputs, making it suitable for most PC,
networking, and consumer applications.
Table 1. Device Functionality: Output Frequencies
Parameter Description
Condition
Min Max Unit
Fo
Output
frequency
VDD = 4.5 V to 5.5 V
1
1
1
133 MHz
100 MHz
66 MHz
On the other hand, CY2037-3 contains a frequency select
function in place of the power-down and output enable modes.
For example, consumer products often require frequency
compatibility with different electrical standards around the world.
With this frequency select feature, a product that incorporates
CY2037-3 could be compatible with both NTSC for North
American, and PAL for Europe by simply changing the FS line.
The twice programmable feature is absent in CY2037-3,
because the second EPROM row is now being used for the
alternate frequency.
VDD = 3.0 V to 3.6 V
DD = 2.7 V to 3.0 V
V
Cypress Semiconductor Corporation
Document Number: 38-07354 Rev. *K
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 13, 2013
CY2037
Logic Block Diagram
PD#/OE
or FS
CONFIGURATION
EPROM
HIGH
ACCURACY
PLL
X
G
CRYSTAL
X
D
OSCILLATOR
MUX
CLKOUT
/ 1, 2, 4, 8, 16, 32, 64, 128
Document Number: 38-07354 Rev. *K
Page 2 of 16
CY2037
Contents
Die Pad Description ..........................................................4
Die Pad Summary .............................................................4
EPROM Configuration Block ...........................................5
PLL Output Frequency .....................................................5
Power Management Features ..........................................5
Crystal Oscillator Tuning Circuit ....................................5
CY2037 Vs CY2037-2 ........................................................6
Frequency Select Feature of CY2037-3 ..........................6
Inkless Die Pick Map (DPM) Format ................................6
Absolute Maximum Ratings ............................................7
Operating Conditions .......................................................7
Electrical Characteristics .................................................8
Output Clock Switching Characteristics ........................9
Switching Waveforms ....................................................11
Ordering Information ......................................................13
Ordering Code Definitions .........................................13
Acronyms ........................................................................14
Reference Documents ....................................................14
Document Conventions .................................................14
Units of Measure .......................................................14
Document History Page .................................................15
Sales, Solutions, and Legal Information ......................16
Worldwide Sales and Design Support .......................16
Products ....................................................................16
PSoC® Solutions ......................................................16
Cypress Developer Community .................................16
Technical Support .....................................................16
Document Number: 38-07354 Rev. *K
Page 3 of 16
CY2037
Die Pad Description
Note:
Horizontal scribe
Active die size:
X = 55.9 mils / 1420.1
m
1
11
10
VDD
CLKOUT
N/C
Y = 40.9 mils / 1039.4
m
Scribe:
X (horizontal) = 3.1mils / 80
2
VDD
m
Y (vertical) = 3.1 mils / 80
Bond pad opening: 85 m x 85
Pad pitch: 125 m x 125
(pad center to pad center)
Bottom side of Die can be connected to Vss
or can be isolated. Do not connect to VDD
m
m
3
4
5
6
7
XX
Vertical scribe
Device Name
m
XD
Y
N/C
.
XG
VSS
VSS
CY2037EBWAF-IL
CY2037-2WAF-IL
7C80383A
7C80381A
9
PD#/OE or FS
8
CY2037-311WAF-IL 7C80340A
CY2037-209WAF-IL 7C80381A
X
Die Pad Summary
X Coordinate
Y Coordinate
Name
Die Pad
Description
(m)
(m)
VDD
1, 2
124.7
1291.35
124.7
855.6, 731
99.6, 225.2
481.8
Voltage supply
Ground
VSS
XD
XX
8, 9
4
Crystal connection
No connect [1]
Crystal connection
3
124.7
606.4
XG
6
124.7
232.6
PD#/OE or 7
FS
124.7
108
CY2037 and CY2037-2: EPROM-programmable power-down or
output enable pad
CY2037-3: Frequency select.
Serves as VPP in programming mode for all devices
CLKOUT
N/C
11
5, 10
1282.45
901.8
Clock output. Also serves as three-state input during programming.
No connect (so do not bond to these pads)
124.7, 1282.45
357.2, 769.4
Note
1. For customers not bonding the X or X pad to external pins, an alternative bonding option would be shorting the Xx pad to the X pad.
D
G
D
Document Number: 38-07354 Rev. *K
Page 4 of 16
CY2037
EPROM Configuration Block
Power Management Features
Table 2 summarizes the features that are configurable by
EPROM. Refer “7C8038x/7C8034X Proprietary Specification”
for further details. This specification can be obtained from your
CY2037 contains EPROM-programmable PD# and OE
functions. If power-down (PD#) is selected, all active circuitry on
the chip is shut down, output is tri-stated and pulled low by a
weak pull-down when the control pin goes LOW. The weak
pull-down is easily overdriven by another active CLKOUT for
applications that require multiple CLKOUTs on a single signal
path.The oscillator and PLL circuits must relock when the part
leaves the power-down mode. If output enable (OE) mode is
selected, the output is tri-stated and weakly pulled low when the
control pin goes low. In this mode the oscillator and PLL circuits
continue to operate, allowing a rapid return to normal operation
when the control input is deasserted.
Cypress factory representative.
.
Table 2. EPROM Adjustable Features
Adjustable Features
Adjust
frequency
Feedback counter value (P)
Reference counter value (Q)
Output divider selection
In addition, the PD# and OE modes can be programmed to occur
synchronously or asynchronously with respect to the output
signal. When the asynchronous setting is used, the power-down
or output disable occurs immediately (allowing for logic delays),
regardless of the position in the clock cycle. However, when the
synchronous setting is used, the part waits for a falling edge at
the output before the power-down or output enable signal is
initiated, thus preventing output glitches. In asynchronous or
synchronous setting, the output is always enabled
synchronously by waiting for the next falling edge of the output.
Oscillator tuning (load capacitance values)
Duty cycle levels (TTL or CMOS)
Power management mode (OE or PD#)
Power management timing (synchronous or asynchronous)
PLL Output Frequency
CY2037 contains a high resolution PLL with 12-bit multiplier and
10-bit divider. The output frequency of the PLL is determined by
the following formula:
2 P + 5
Q + 2
---------------------------
FREF
FPLL
=
In this formula, P is the feedback counter value and Q is the
reference counter value. P and Q are EPROM programmable
values.
Crystal Oscillator Tuning Circuit
CY2037 contains a unique tuning circuit to fine-tune the output frequency of the device. The tuning circuit consists of an array of eleven
load capacitors on both sides of the oscillator drive inverter. The capacitor load values are EPROM-programmable and may be
increased in small increments. As the capacitor load is increased the circuit is fine-tuned to a lower frequency. The capacitor load
values vary from 0.17 pF to 8 pF for a 100:1 total control ratio. The tuning increments are shown in Table 3 on page 6. Refer to
“7C8038x/7C8034x Proprietary Specification” for further details.
Figure 1. Crystal Oscillator Tuning Circuit
Rf
External Crystal
C6
C5
C4
C3
C2
C1
C0
Cgo
C7
C8
C9 C10
Cdo
CD6 CD5 CD4 CD3 CD2 CD1 CD0
CD3 CD4 CD5 CD6
CD = EPROM BIT
C = LOAD CAPACITOR
Document Number: 38-07354 Rev. *K
Page 5 of 16
CY2037
Table 3. Crystal Oscillator Parameter
Parameter
Description
Min
Typ
Max
Unit
Rf
Feedback resistor, VDD = 4.5 V to 5.5 V
Feedback resistor, VDD = 2.7 V to 3.6 V
0.5
1.0
2
4
3.5
9.0
M
M
Capacitors have ± 20% tolerance
Cg
Cd
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
Gate capacitor
Drain capacitor
Series capacitor
Series capacitor
Series capacitor
Series capacitor
Series capacitor
Series capacitor
Series capacitor
Series capacitor
Series capacitor
Series capacitor
Series capacitor
–
–
–
–
–
–
–
–
–
–
–
–
–
13
9
–
–
–
–
–
–
–
–
–
–
–
–
–
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
0.27
0.52
1.00
0.7
1.4
2.6
5.0
0.45
0.85
1.7
3.3
CY2037 Vs CY2037-2
Table 4. Frequency Select Pin Decoding for CY2037-3
CY2037 contains a shadow register in addition to the EPROM
register. The shadow register is an exact copy of the EPROM
register and is the default register when the valid bit is not set. It
is useful when the prototype or production environment calls for
measuring and adjusting the CLKOUT frequency several times.
Multiple adjustments can be performed with the shadow register.
After the required frequency is achieved the EPROM register is
permanently programmed.
FS Pin
Output Frequency
0
1
From EPROM row 0 configuration
From EPROM row 1 configuration
Inkless Die Pick Map (DPM) Format
Cypress ships inkless wafers to customers with an
accompanying die pick map, which is used to determine the good
die for assembly and programming. Customers can also access
individual DPM files at their convenience through
ftp.cypress.com with a valid user account login and password.
Contact your local Cypress Field Application Engineer (FAE) or
sales representative for a customer FTP account. The DPM files
are named with the fab lot number and wafer number scribed on
the wafer. The DPM files are transferred to the customer’s FTP
account when the factory ships out the wafers against their
purchase order (PO).
Some production flows do not require the use of the shadow
register. If this is the case, then CY2037-2 is the chosen device
and CY2037-2 has a disabled shadow register. CY2037-3
contains the shadow register.
Frequency Select Feature of CY2037-3
CY2037-3 contains a frequency select function in place of the
power-down and the output enable functions. With the frequency
select feature, customers can switch two different frequencies
that are configured in the two EPROM rows. Table 4 lists the
definition of the frequency select pin (FS).
Document Number: 38-07354 Rev. *K
Page 6 of 16
CY2037
Input voltage ....................................... –0.5 V to VDD + 0.5 V
Storage temperature (non-condensing) ..... 55 °C to +150 °C
Junction temperature ............................... –40 °C to +100 °C
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.[2]
Static discharge voltage
(per MIL-STD-883, method 3015) ............................. 2000 V
Supply voltage .............................................–0.5 V to +7.0 V
Operating Conditions
Parameter
VDD
Description
Min
Max
Unit
Supply voltage (3.3 V)
Supply voltage (5.0 V)
2.7
4.5
3.6
5.5
V
V
[3]
TAJ
Operating temperature, Junction
–10
–
+100
C
CTTL
Max. capacitive load on outputs for TTL levels
VDD = 4.5 V to 5.5 V, output frequency = 1 MHz to 40 MHz
50
25
pF
pF
V
DD = 4.5 V to 5.5 V, output frequency = 40 MHz to 133 MHz
Max. capacitive load on outputs for CMOS levels
DD = 4.5 V to 5.5 V, output frequency = 1 MHz to 66.6 MHz
VDD = 4.5 V to 5.5 V, output frequency = 66.6 MHz to 133 MHz
CCMOS
–
V
50
25
30
15
15
pF
pF
pF
pF
pF
V
V
DD = 3.0 V to 3.6 V, output frequency = 1 MHz to 40 MHz
DD = 3.0 V to 3.6 V, output frequency = 40 MHz to 100 MHz
VDD = 2.7 V to 3.0 V, output frequency = 1 MHz to 66 MHz
XREF
tPU
Reference frequency, input crystal. Fundamental tuned crystals only
10
30
50
MHz
ms
Power up time for all VDD’s to reach minimum specified voltage (power ramps must
be monotonic)
0.05
Notes
2. Stresses greater than listed can impair the life of the device.
3. This product is sold in die form so operating conditions are specified for the die, or junction temperature.
Document Number: 38-07354 Rev. *K
Page 7 of 16
CY2037
Electrical Characteristics
Over the Operating Range
Parameter [4]
VIL
Description
Test Conditions
VDD = 4.5 V to 5.5 V
DD = 2.7 V to 3.6 V
Min
Typ
Max
Unit
Low-level input voltage
High-level input voltage
Low-level output voltage
–
–
0.8
0.2 × VDD
V
V
V
VIH
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 3.6 V
2.0
0.7 × VDD
–
–
–
–
–
V
V
VOL
VDD = 4.5 V to 5.5 V, IOL = 16 mA
–
0.4
0.4
V
V
VDD = 2.7 V to 3.6 V, IOL = 8 mA
VOHCMOS
VOHTTL
High-level output voltage, CMOS VDD = 4.5 V to 5.5 V, IOH = –16 mA VDD – 0.4
–
V
V
levels
VDD = 2.7 V to 3.6 V, IOH = –8 mA
V
DD – 0.4
High-level output voltage, TTL
levels
VDD = 4.5 V to 5.5 V, IOH = –8 mA
2.4
–
V
IIL
Input low-current
Input high-current
VIN = 0 V
VIN = VDD
–
–
–
–
–
–
10
5
A
A
IIH
IDD
Power supply current, Unloaded VDD = 4.5 V to 5.5 V,
output frequency 133 MHz
DD = 2.7 V to 3.6 V,
45
25
mA
mA
V
output frequency 100 MHz
[5]
IDDS
Standby current
VDD = 2.7 V to 3.6 V
–
10
50
A
RUP
Input pull-up resistor
VDD = 4.5 V to 5.5 V, VIN = 0 V
1.1
50
3.0
100
8.0
200
M
k
VDD = 4.5 V to 5.5 V, VIN = 0.7 × VDD
IPD_CLKOUT
CLKOUT pull-down current (OE VDD = 5.0 V
or PD# mode)
–
20
–
A
Notes
4. This part was characterized in a 20-pin SOIC package with external crystal, Electrical Characteristics can change with other package types.
5. If external reference is used, it is required to stop the reference (set reference to LOW) during power-down.
Document Number: 38-07354 Rev. *K
Page 8 of 16
CY2037
Output Clock Switching Characteristics
Over the Operating Range
Parameter [6]
t1w
Description
Test Conditions
Min
Typ
Max
Unit
Output duty cycle at 1.4 V,
DD = 4.5 V to 5.5 V
1w = t1A t1B
Figure 2 on page 11.
1 MHz to 40 MHz, CL 50 pF
40 MHz to 66 MHz, CL 15 pF
66 MHz to 125 MHz, CL 25 pF
125 MHz to 133 MHz, CL 15 pF
45
45
40
40
–
55
55
60
60
%
%
%
%
V
t
t1x
t1y
t1z
t2
Output duty cycle at VDD/2,
VDD = 4.5 V to 5.5 V
1 MHz to 66.6 MHz, CL 25 pF
66.6 MHz to 125 MHz, CL 25 pF
125 MHz to 133 MHz, CL 15 pF
45
40
40
–
–
–
–
55
60
60
%
%
%
t
1x = t1A t1B
Figure 2 on page 11.
Output duty cycle at VDD/2,
1 MHz to 40 MHz, CL 30 pF
40 MHz to 100 MHz, CL 15 pF
45
40
55
60
%
%
VDD = 3.0 V to 3.6 V
t1y = t1A t1B
Figure 2 on page 11.
Output duty cycle at VDD/2,
1 MHz to 40 MHz, CL 15 pF
40 MHz to 66.6 MHz, CL 10 pF
40
40
60
60
%
%
VDD = 2.7 V to 3.0 V
t
1z = t1A t1B
Figure 2 on page 11.
Output clock rise time
Figure 3 on page 11.
Between 0.8 V to 2.0 V,
VDD = 4.5 V to 5.5 V, CL = 50 pF
Between 0.8 V to 2.0 V,
–
–
–
1.8
1.2
0.9
3.4
4.0
2.4
ns
ns
ns
ns
ns
ns
VDD = 4.5 V to 5.5 V, CL = 25 pF
Between 0.8 V to 2.0 V,
VDD = 4.5 V to 5.5 V, CL = 15 pF
Between 0.2 VDD to 0.8 VDD
VDD = 4.5 V to 5.5 V, CL = 50 pF
Between 0.2 VDD to 0.8 VDD
,
,
V
DD = 3.0 V to 3.6 V, CL = 30 pF
Between 0.2 VDD to 0.8 VDD
,
V
DD = 2.7 V to 3.6 V, L = 15 pF
Between 0.8 V to 2.0 V,
DD = 4.5 V to 5.5 V, CL = 50 pF
t3
Output clock fall time
Figure 3 on page 11.
–
V
1.8
1.2
0.9
3.4
4.0
ns
ns
ns
ns
ns
Between 0.8 V to 2.0 V,
VDD = 4.5 V to 5.5 V, CL = 25 pF
Between 0.8 V to 2.0 V,
V
DD = 4.5 V to 5.5 V, CL = 15 pF
Between 0.2 VDD to 0.8 VDD
,
V
DD = 4.5 V to 5.5 V, CL = 50 pF
Between 0.2 VDD to 0.8 VDD
,
VDD = 3.0 V to 3.6 V, CL = 30 pF
Between 0.2 VDD to 0.8 VDD
DD = 2.7 V to 3.6 V, CL = 15 pF
,
V
2.4
2
ns
t4
Startup time out of power-down PD# pin LOW to HIGH[7]
Figure 4 on page 11.
1
ms
Notes
6. Not all parameters measured in production testing.
7. Oscillator start time cannot be guaranteed for all crystal types. This specification is for operation with AT cut crystals with ESR < 70 ohms.
Document Number: 38-07354 Rev. *K
Page 9 of 16
CY2037
Output Clock Switching Characteristics (continued)
Over the Operating Range
Parameter [6]
t5a
Description
Test Conditions
Min
Typ
Max
Unit
Power-down delay time
(synchronous setting)
Figure 4 on page 11.
PD# pin LOW to output LOW
(T = period of output clk)
–
T/2
T + 10
ns
t5b
Power-down delay time
(asynchronous setting)
Figure 4 on page 11.
PD# pin LOW to output LOW
From power-on[8]
–
10
15
ns
t6
Power-up time
Figure 5 on page 11.
–
–
1
2
ms
ns
t7a
Output disable time
(synchronous setting)
Figure on page 13.
OE pin LOW to output high Z
(T = period of output clk)
T/2
T + 10
t7b
Output disable time
(asynchronous setting)
Figure on page 13.
OE pin LOW to output high Z
–
–
–
10
T
15
ns
ns
t8
Output enable time (always
synchronous enable)
Figure on page 13.
OE pin LOW to HIGH
(T = period of output clk)
1.5T + 25
t9
Peak-to-peak period jitter
Figure 7 on page 12.
VDD = 4.5 V to 5.5 V, FO > 33 MHz,
VCO > 100 MHz
ps
ps
ps
±100
±125
VDD = 2.7 V to 3.6 V, FO > 33 MHz,
VCO > 100 MHz
VDD = 2.7 V to 5.5 V, FO < 33 MHz
±125
±250
±200
1% of FO
Note
8. Oscillator start time cannot be guaranteed for all crystal types. This specification is for operation with AT cut crystals with ESR < 70 ohms.
Document Number: 38-07354 Rev. *K
Page 10 of 16
CY2037
Switching Waveforms
Figure 2. Duty Cycle Timing (t1w, 1x, t1y, t1z)
t
t
1B
t
1A
OUTPUT
Figure 3. Output Rise/Fall Time
VDD
0 V
OUTPUT
t
2
t
3
Figure 4. Power Down Timing (Synchronous and Asynchronous Modes)
VDD
0V
VIH
POWER
DOWN
VIL
t4
CLKOUT
[
(synchronous 9]
)
T
t5a
1/f
CLKOUT
[
(asynchronous 10]
)
t5b
1/f
Figure 5. Power-Up Timing
VDD
0 V
V
DD – 10%
POWER
t6
UP
min. 50 s
max. 50 ms
CLKOUT
1/f
Notes
9. In synchronous mode the power down or output tri-state is not initiated until the next falling edge of the output clock.
10. In asynchronous mode the power down or output tri-state occurs within 25 ns regardless of position in the output clock cycle.
Document Number: 38-07354 Rev. *K
Page 11 of 16
CY2037
Switching Waveforms (continued)
Figure 6. Output Enable Timing (Synchronous and Asynchronous Modes)
VDD
0 V
OUTPUT
ENABLE
VIH
VIL
T
CLKOUT
(synchronous 11]
High Impedance
[
)
t7a
t8
CLKOUT
High Impedance
[
(asynchronous 12]
)
t7b
t8
Figure 7. Period Jitter
t9
50%
CLK
Notes
11. In synchronous mode the power down or output tri-state is not initiated until the next falling edge of the output clock.
12. In asynchronous mode the power down or output tri-state occurs within 25 ns regardless of position in the output clock cycle.
Document Number: 38-07354 Rev. *K
Page 12 of 16
CY2037
Ordering Information
Ordering Code
CY2037EBWAF-IL
CY2037-2WAF-IL
Type
Inkless wafer
Wafer Thickness
14 ± 0.5 Mils
Operating Range
–10 C to 100 C
Inkless wafer
Inkless wafer
Inkless wafer
14 ± 0.5 Mils
11 ± 0.5 Mils
8.66 ± 0.3 Mils
–10 C to 100 C
–10 C to 100 C
–10 C to 100 C
CY2037-311WAF-IL
CY2037-209WAF-IL
Ordering Code Definitions
CY 2037 XX -
X
XX WAF-IL
Fixed for Inkless Wafer
Wafer Thickness: XX = 11 or 09 or blank
“11” for 11 Mils; “09” for 8.66 Mils, blank for 14 Mils
Part Version: X = 2, 3 or blank for base part
Die Revision: EB or None
Part Identifier
Company ID: CY = Cypress
Document Number: 38-07354 Rev. *K
Page 13 of 16
CY2037
Acronyms
Acronym
CLKOUT
CMOS
DPM
Description
Clock Output
Complementary Metal Oxide Semiconductor
Die Pick Map
EPROM
NTSC
OE
Erasable Programmable Read Only Memory
National Television System Committee
Output Enable
PAL
Phase Alternate Line
PD
Power Down
PLL
Phase Locked Loop
PPM
Parts Per Million
TTL
Transistor-Transistor Logic
Reference Documents
Reference documents are available through your local Cypress sales representative. You can also direct your requests to
tsbusdev@cypress.com.
Document Number
Document Title
Description
7C8038x/7C8034X proprietary
specification
Appendix C contains programming specification for customer use
71-00005
Document Conventions
Units of Measure
Symbol
°C
Unit of Measure
Symbol
µW
Unit of Measure
degrees Celsius
decibels
micro Watts
milli Amperes
milli meters
milli seconds
milli Volts
dB
mA
mm
ms
mV
nA
ns
dBc/Hz
fC
decibels relative to the carrier per Hertz
femto Coulomb
femto Farads
Hertz
fF
Hz
nano Amperes
nano seconds
nano Volts
KB
1024 bytes
Kbit
kHz
k
1024 bits
nV
kilo Hertz
ohms
kilo ohms
pA
pF
pp
pico Amperes
pico Farads
peak-to-peak
parts per million
pico seconds
MHz
M
µA
mega Hertz
mega Ohms
micro Amperes
micro Farads
micro Henrys
micro seconds
micro Volts
ppm
ps
µF
µH
sps
samples per second
µs
sigma: one standard deviation
µV
µVrms
micro Volts root-mean-square
Document Number: 38-07354 Rev. *K
Page 14 of 16
CY2037
Document History Page
Document Title: CY2037, High Accuracy EPROM Programmable PLL Die for Crystal Oscillators
Document Number: 38-07354
Orig. of
Change
Submission
date
Revision
ECN
Description of Change
**
112248
121857
291092
522769
DSG
RBI
03/01/02
12/14/02
Change from Spec number: 38-00679 to 38-07354
*A
*B
*C
Power up requirements added to Operating Conditions Information
RGL
RGL
See ECN Updated Min. Operating Temperature, Junction
See ECN Added CY2037B information.
Updated absolute maximum Junction temperature specification.
Updated Ordering information table.
Added Die Pad description and coordinates
*D
*E
804376
RGL
See ECN Minor Change: To post on web
See ECN Added Inkless Die information.
2192266
DPF /
PYRS
*F
2748211
2761988
TSAI
KVM
08/10/09
09/14/09
Posting to external web.
*G
Add CY2037EBWAF-IL to Ordering Information table
Remove obsolete part numbers: CY2037AWAF, CY2037-2WAF,
CY2037-3WAF, CY2037-3WAF-IL.
Removed Status column in Ordering Information table; replaced with footnotes
*H
*I
2906472
3022612
CXQ
04/07/2010 Removed inactive part from Ordering Information table.
BASH
09/03/2010 Post divider number corrected in “Feature” section from 16 to 8 on page 1.
Removed all references of obsolete parts(CY2037A) and Benefits section from
page 1.(CTI die scribe: X(horizontal)= 2.6 mils/65.6 µm, Y(vertical)=3.0
mils/76.9 µm)
Die diagram on page 3 updated with Pad numbers, Scribe dimensions for
TSMC part, Device name table, note for bottom side of die connection.
“T” for Transistor removed from Figure 1 on page 4 as it is not mentioned in
figure anywhere.
Changed parameter name to IPD_CLOCKOUT and clarified its description in
Electrical Characteristics table on page 7.
Added Figure 6 and 7 for OE and Period Jitter on page 9.
Part numbers CY2037EB and CY2037-311 added in ordering information on
page 9.
Added Ordering code definitions.
Added Acronyms, Reference documents and Document conventions.
*J
3069175
4175824
BASH
CINM
10/25/2010 Removing CY2037B from die pad description on page 4, ordering information
and ordering code definitions.
*K
11/13/2013 Updated Die Pad Description.
Updated Ordering Information (Added new part number CY2037-209WAF-IL).
Updated in new template.
Completing Sunset Review.
Document Number: 38-07354 Rev. *K
Page 15 of 16
CY2037
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Clocks & Buffers
Interface
Cypress Developer Community
Lighting & Power Control
Community | Forums | Blogs | Video | Training
Technical Support
Memory
cypress.com/go/memory
cypress.com/go/psoc
cypress.com/go/support
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2010-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-07354 Rev. *K
Revised November 13, 2013
Page 16 of 16
2
2
2
Purchase of I C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I C Patent Rights to use these components in an I C system, provided
2
that the system conforms to the I C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors.
All products and company names mentioned in this document may be the trademarks of their respective holders.
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