CY2037B-11WAF-IL [CYPRESS]
High-Accuracy EPROM Programmable PLL Die for Crystal Oscillators; 高精度EPROM可编程PLL模晶体振荡器
| 型号： | CY2037B-11WAF-IL |
| 厂家： | 
CYPRESS |
| 描述： | High-Accuracy EPROM Programmable PLL Die for Crystal Oscillators |
| 文件： | 总11页 (文件大小：264K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY2037
High-Accuracy EPROM Programmable
PLL Die for Crystal Oscillators
Features
Benefits
■ EPROM-programmable die for in-package programming of
■ Enables quick turnaround of custom oscillators
crystal oscillators
■ Lowers inventory costs through stocking of blank parts
■ High resolution PLL with 12-bit multiplier and 10-bit divider
■ Enables synthesis of highly accurate and stable output clock
■ EPROM-programmable capacitor tuning array with shadow
frequencies with zero or low PPM
register
■ Enables fine-tuning of output clock frequency by adjusting
CLoad of the crystal
■ Twice programmable die (CY2037A, CY2037B[1], and
CY2037-2)
■ Enables reprogramming of programmed part to correct errors,
■ Simple 2-wire programming interface
and control excess inventory
■ On-chip oscillator runs from 10 - 30 MHz fundamental tuned
■ Enables programming of output frequency after packaging
crystal
■ Lowers cost of oscillator because PLL may be programmed to
■ EPROM-selectable TTL or CMOS duty cycle levels
a high frequency using a low frequency, low cost crystal
■ Operating frequency:
❐ 1 - 133 MHz at 5V
❐ 1 - 100 MHz at 3.3V
❐ 1 - 66.6 MHz at 2.7V
■ Duty cycle centered at 1.4V or VDD/2
■ Provides flexibility to service most TTL or CMOS applications
■ Provides flexibility in output configurations and testing
■ Enables low power operations or output enable functions
■ Sixteen selectable post divide options, using PLL or reference
oscillator output
■ Enables two frequency options for meeting different industry
standards, that is, PAL/NTSC
■ Programmable power down (PD#) or OE pin (CY2037A,
CY2037B, and CY2037-2)
■ Provides flexibility for system applications through selectable
instantaneous or synchronous change in outputs
■ Frequency select (CY2037-3)
■ Suitable for most PC, consumer, and networking applications
■ Programmable asynchronous or synchronous OE and power
down (PD#) modes (CY2037A, CY2037B, and CY2037-2)
■ Lowers inventory costs because the same die services both
applications
■ Low jitter outputs typically:
❐ < ± 100 ps (pk-pk) at 5V and f>33 MHz
❐ < ± 125 ps (pk-pk) at 3.3V and f>33 MHz
■ Enables encapsulation in small size, surface mount packages
■ Has lower EMI than oscillators
■ 3.3V or 5V operation
■ Small die
■ Controlled rise and fall times and output slew rate
Table 1. Device Functionality: Output Frequencies
Parameter
Fo
Description
Output frequency
Condition
Min
1
Max
133
100
66
Unit
MHz
MHz
MHz
VDD = 4.5V–5.5V
V
DD = 3.0V–3.6V
DD = 2.7V–3.0V
1
V
1
Note
1. CY2037A and CY2037B are identical. However, CY2037B is recommended for all new designs.
Cypress Semiconductor Corporation
Document Number: 38-07354 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 06, 2008
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CY2037
Logic Block Diagram
PD#/OE
or FS
CONFIGURATION
EPROM
HIGH
ACCURACY
PLL
X
G
CRYSTAL
X
D
OSCILLATOR
MUX
CLKOUT
/ 1, 2, 4, 8, 16, 32, 64, 128
Document Number: 38-07354 Rev. *E
Page 2 of 11
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CY2037
Die Pad Description
Horizontal scribe
VDD
VDD
XX
CLKOUT
N/C
Note
Active die size: X = 55.9 mils / 1420.1 μm
Scribe: X (horizontal) = 2.6 mils / 65.6 μm
Vertical scribe
Device Name
Y (vertical) = 3.0 mils / 76.9
Bond pad opening: 85 m x 85
Pad pitch: 125 m x 125
(pad center to pad center)
μm
XD
Y
μ
μm
μ
μm
N/C
XG
VSS
VSS
PD#/OE or FS
X
Die Pad Summary
Die
X Coordinate Y Coordinate
Name
VDD
Description
Pad
(μm)
124.7
1291.35
124.7
124.7
124.7
124.7
(μm)
855.6, 731
99.6, 225.2
481.8
1, 2
Voltage supply
VSS
XD
XX
8, 9
4
Ground
Crystal connection
No connect [2]
Crystal connection
3
606.4
XG
6
232.6
PD#/OE
or FS
7
108
CY2037A, CY2037B, and CY2037-2: EPROM-programmable power down
or output enable pad
CY2037-3: Frequency select. Serves as VPP in programming mode for all
devices
CLKOUT 11
1282.45
901.8
Clock output. Also serves as three-state input during programming.
N/C
5, 10
124.7,1282.45
357.2, 769.4 No connect (so do not bond to these pads)
Note
2. For customers not bonding the X or X pad to external pins, an alternative bonding option would be shorting the Xx pad to the X pad.
D
G
D
Document Number: 38-07354 Rev. *E
Page 3 of 11
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CY2037
Functional Description
EPROM Configuration Block
CY2037 is an EPROM-programmable, high accuracy,
PLL-based die designed for the crystal oscillator market. The die
attaches directly to a low cost 10 - 30 MHz crystal and can be
packaged into a 4-pin through-hole or surface mount packages.
The oscillator devices may be stocked as blank parts and custom
frequencies programmed in-package at the last stage before
shipping. This enables fast-turn manufacture of custom and
standard crystal oscillators without the need for dedicated,
expensive crystals.
Table 2 summarizes the features that are configurable by
EPROM. Refer “7C8038x/7C8034X Programming Specification”
for further details. This specification can be obtained from your
Cypress factory representative.
.
Table 2. EPROM Adjustable Features
Adjustable Features
Adjust
Frequency
Feedback Counter Value (P)
Reference Counter Value (Q)
Output Divider Selection
CY2037 contains an on-chip oscillator and a unique oscillator
tuning circuit for fine-tuning of the output frequency. The crystal
C
load may be selectively adjusted by programming a set of seven
Oscillator Tuning (Load Capacitance Values)
Duty Cycle Levels (TTL or CMOS)
EPROM bits. This feature is used to compensate for crystal
variations or to obtain a more accurate synthesized frequency.
Power Management Mode (OE or PD#)
CY2037 uses EPROM programming with a simple 2-wire, 4-pin
interface that includes VSS and VDD. Clock outputs may be
generated up to 133 MHz at 5V or up to 100 MHz at 3.3V. The
entire configuration can be reprogrammed once, which allows
the programmed inventory to be altered or reused.
Power Management Timing (Synchronous or Asynchronous)
PLL Output Frequency
CY2037 PLL die is designed for very high resolution. It has a
12-bit feedback counter multiplier and a 10-bit reference counter
divider. This enables the synthesis of highly accurate and stable
output clock frequencies with zero or low PPM error. The clock
is further modified by eight output divider options of 1, 2, 4, 8, 16,
32, 64, and 128. The divider input can be selected as the PLL or
crystal oscillator output, providing a total of 16 separate output
options. For further flexibility, the ouput is selectable between
TTL and CMOS duty cycle levels.
CY2037 contains a high resolution PLL with 12-bit multiplier and
10-bit divider. The output frequency of the PLL is determined by
the following formula:
2 • (P + 5)
(Q + 2)
---------------------------
• FREF
FPLL
=
In this formula, P is the feedback counter value and Q is the
reference counter value. P and Q are EPROM programmable
values.
CY2037, CY2037B, and CY2037-2 also contain flexible power
management controls. These parts include both power down
(PD#) and OE features with integrated pull up resistors. The PD#
and OE modes have an additional setting to determine timing
(asynchronous or synchronous) with respect to the output signal.
When PD# or OE modes are enabled, CLKOUT is pulled low by
a weak pull down. The weak pull down is easily overdriven by
another active CLKOUT for applications that require multiple
CLKOUTs on a single signal path.
Power Management Features (except CY2037-3)
CY2037 contains EPROM-programmable PD# and OE
functions. If power down is selected, all active circuitry on the
chip is shut down when the control pin goes LOW. The oscillator
and PLL circuits must relock when the part leaves the power
down mode. If output enable mode is selected, the output is
tri-stated and weakly pulled low when the control pin goes low.
In this mode the oscillator and PLL circuits continue to operate,
allowing a rapid return to normal operation when the control input
is deasserted.
Controlled rise and fall times, unique output driver circuits, and
innovative circuit layout techniques enable CY2037 to have low
jitter and accurate outputs, making it suitable for most PC,
networking, and consumer applications.
In addition, the PD# and OE modes can be programmed to occur
synchronously or asynchronously with respect to the output
signal. When the asynchronous setting is used, the power down
or output disable occurs immediately (allowing for logic delays),
regardless of the position in the clock cycle. However, when the
synchronous setting is used, the part waits for a falling edge at
the output before the power down or output enable signal is
initiated, thus preventing output glitches. In asynchronous or
synchronous setting, the output is always enabled
synchronously by waiting for the next falling edge of the output.
On the other hand, CY2037-3 contains a frequency select
function in place of the power down and output enable modes.
For example, consumer products often require frequency
compatibility with different electrical standards around the world.
With this frequency select feature, a product that incorporates
CY2037-3 could be compatible with both NTSC for North
American, and PAL for Europe by simply changing the FS line.
The twice programmable feature is also absent in CY2037-3,
because the second EPROM row is now being used for the
alternate frequency.
Document Number: 38-07354 Rev. *E
Page 4 of 11
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CY2037
Crystal Oscillator Tuning Circuit
CY2037 contains a unique tuning circuit to fine-tune the output frequency of the device. The tuning circuit consists of an array of eleven
load capacitors on both sides of the oscillator drive inverter. The capacitor load values are EPROM-programmable and may be
increased in small increments. As the capacitor load is increased the circuit is fine-tuned to a lower frequency. The capacitor load
values vary from 0.17 pF to 8 pF for a 100:1 total control ratio. The tuning increments are shown in Table 3. Refer to “7C8038x/7C8034x
Programming Specification” for further details.
Figure 1. Crystal Oscillator Tuning Circuit
Rf
External Crystal
C6
C5
C4
C3
C2
C1
C0
Cgo
C7
C8
C9 C10
Cdo
CD6 CD5 CD4 CD3 CD2 CD1 CD0
CD3 CD4 CD5 CD6
CD = EPROM BIT
T = TRANSISTOR
C = LOAD CAPACITOR
Table 3. Crystal Oscillator Parameter
Parameter
Description
Feedback resistor, VDD = 4.5–5.5V
Feedback resistor, VDD = 2.7–3.6V
Capacitors have ± 20% tolerance
Min
Typ.
Max
Unit
Rf
0.5
1.0
2
4
3.5
9.0
MΩ
MΩ
Cg
Gate capacitor
Drain capacitor
Series cap
Series cap
Series cap
Series cap
Series cap
Series cap
Series cap
Series cap
Series cap
Series cap
Series cap
13
9
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
Cd
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
0.27
0.52
1.00
0.7
1.4
2.6
5.0
0.45
0.85
1.7
3.3
Document Number: 38-07354 Rev. *E
Page 5 of 11
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CY2037
CY2037A/CY2037B Versus CY2037-2
Inkless Die Pick Map (DPM) Format
CY2037A and CY2037B contain a shadow register in addition to
the EPROM register. The shadow register is an exact copy of the
EPROM register and is the default register when the Valid bit is
not set. It is useful when the prototype or production environment
calls for measuring and adjusting the CLKOUT frequency
several times. Multiple adjustments can be performed with the
shadow register. After the required frequency is achieved the
EPROM register is permanently programmed.
Cypress ships inkless wafers to customers with an
accompanying die pick map, which is used to determine the good
die for assembly and programming. Customers can also access
individual DPM files at their convenience through
ftp.cypress.com with a valid user account login and password.
Contact your local Cypress Field Application Engineer (FAE) or
sales representative for a customer FTP account. The DPM files
are named with the fab lot number and wafer number scribed on
the wafer. The DPM files are transferred to the customer’s FTP
account when the factory ships out the wafers against their
purchase order (PO).
Some production flows do not require the use of the shadow
register. If this is the case, then CY2037-2 is the chosen device
and CY2037-2 has a disabled shadow register. CY2037-3
contains the shadow register.
Frequency Select Feature of CY2037-3
CY2037-3 contains a frequency select function in place of the
powerdown and the output enable functions. With the frequency
select feature, customers can switch two different frequencies
that are configured in the two EPROM rows. Table 4 lists the
definition of the frequency select pin (FS).
Table 4. Frequency Select Pin Decoding for CY2037-3
FS Pin
Output Frequency
0
1
From EPROM row 0 configuration
From EPROM row 1 configuration
Document Number: 38-07354 Rev. *E
Page 6 of 11
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CY2037
Input voltage.............................................. –0.5V to VDD+0.5
Storage temperature (non-condensing)........ 55°C to +150°C
Junction temperature.................................. –40°C to +100°C
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.[3]
Static discharge voltage............................................... 2000V
(per MIL-STD-883, Method 3015)
Supply voltage..................................................–0.5 to +7.0V
Operating Conditions
Parameter
Description
Min
Max
Unit
VDD
Supply voltage (3.3V)
2.7
4.5
3.6
5.5
V
V
Supply voltage (5.0V)
[4]
TAJ
Operating temperature, Junction
–10
+100
°C
CTTL
Max. capacitive load on outputs for TTL levels
VDD = 4.5–5.5V, output frequency = 1 - 40 MHz
50
25
pF
pF
VDD = 4.5–5.5V, output frequency = 40 - 133 MHz
CCMOS
Max. capacitive load on outputs for CMOS levels
VDD = 4.5–5.5V, output frequency = 1 - 66.6 MHz
50
25
30
15
15
pF
pF
pF
pF
pF
VDD = 4.5–5.5V, output frequency = 66.6 - 133 MHz
VDD = 3.0–3.6V, output frequency = 1 - 40 MHz
V
DD = 3.0–3.6V, output frequency = 40 - 100 MHz
DD = 2.7–3.0V, output frequency = 1 - 66 MHz
V
XREF
tPU
Reference frequency, input crystal. Fundamental tuned crystals only
10
30
50
MHz
ms
Power up time for all VDDs to reach minimum specified voltage (power ramps must
be monotonic)
0.05
Electrical Characteristics
Over the Operating Range[5]
Parameter
VIL
Description
Test Conditions
Min
Typ. Max
Unit
Low level input voltage
VDD = 4.5V - 5.5V
DD = 2.7V - 3.6V
0.8
0.2VDD
V
V
V
VIH
High level input voltage
Low level output voltage
VDD = 4.5V - 5.5V
DD = 2.7V - 3.6V
2.0
0.7VDD
V
V
V
VOL
VDD = 4.5V - 5.5V, IOL= 16 mA
VDD = 2.7V - 3.6V, IOL= 8 mA
0.4
0.4
V
V
VOHCMOS
High level output voltage, VDD = 4.5V - 5.5V, IOH = –16 mA
DD = 2.7V - 3.6V, IOH = –8 mA
VDD – 0.4
V
V
V
VDD – 0.4
CMOS levels
VOHTTL
High level output voltage, VDD = 4.5V - 5.5V, IOH = –8 mA
TTL levels
2.4
V
IIL
Input low current
Input high current
Power supply current,
Unloaded
VIN = 0V
10
5
μA
μA
IIH
IDD
VIN = VDD
VDD = 4.5V - 5.5V, output frequency <= 133 MHz
45
25
mA
mA
VDD = 2.7V - 3.6V, output frequency <= 100 MHz
[6]
IDDS
Standby current
Input pull up resistor
VDD = 2.7V - 3.6V
10
50
μA
RUP
VDD = 4.5V - 5.5V, VIN = 0V
VDD = 4.5V - 5.5V, VIN = 0.7VDD
1.1
50
3.0
100
8.0
200
MΩ
kΩ
IOE_CLKOUT CLKOUT pull down current VDD = 5.0
20
μA
Notes
3. Stresses greater than listed can impair the life of the device.
4. This product is sold in die form so operating conditions are specified for the die, or junction temperature.
5. This part was characterized in a 20-pin SOIC package with external crystal, Electrical Characteristics can change with other package types.
6. If external reference is used, it is required to stop the reference (set reference to LOW) during power down.
Document Number: 38-07354 Rev. *E
Page 7 of 11
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CY2037
Output Clock Switching Characteristics
Over the Operating Range[7]
Parameter
Description
Test Conditions
Min
Typ
Max Unit
t1w
Output duty cycle at 1.4V, 1 - 40 MHz, CL <=50 pF
45
45
40
40
55
55
60
60
%
%
%
%
VDD = 4.5–5.5V
40 - 66 MHz, CL <=15 pF
66 - 125 MHz, CL <=25 pF
125 - 133 MHz, CL <=15 pF
t1w = t1A ÷ t1B
t1x
t1y
t1z
t2
Output duty cycle at VDD/2, 1 - 66.6 MHz, CL <=25 pF
45
40
40
55
60
60
%
%
%
V
DD = 4.5–5.5V
66.6 - 125 MHz, CL <=25 pF
125 - 133 MHz, CL <=15 pF
t
1x = t1A ÷ t1B
Output duty cycle at VDD/2, 1 - 40 MHz, CL <=30 pF
DD = 3.0–3.6 40 - 100 MHz, CL <=15 pF
t1y = t1A ÷ t1B
45
40
55
60
%
%
V
Output duty cycle at VDD/2, 1 - 40 MHz, CL <=15 pF
40
40
60
60
%
%
VDD = 2.7–3.0
1y = t1A ÷ t1B
40 - 66.6 MHz, CL <=10 pF
t
Output clock rise time
Between 0.8V - 2.0V, VDD = 4.5V - 5.5V, CL = 50 pF
Between 0.8V - 2.0V, VDD = 4.5V - 5.5V, CL = 25 pF
Between 0.8V - 2.0V, VDD = 4.5V - 5.5V, CL = 15 pF
Between 0.2VDD - 0.8VDD, VDD = 4.5V - 5.5V, CL = 50 pF
Between 0.2VDD - 0.8VDD, VDD = 3.0V - 3.6V, CL = 30 pF
Between 0.2VDD - 0.8VDD, VDD = 2.7V - 3.6V, CL = 15 pF
1.8
1.2
0.9
3.4
4.0
2.4
ns
ns
ns
ns
ns
ns
t3
Output clock fall time
Between 0.8V - 2.0V, VDD = 4.5V - 5.5V, CL = 50 pF
Between 0.8V - 2.0V, VDD = 4.5V - 5.5V, CL = 25 pF
Between 0.8V - 2.0V, VDD = 4.5V - 5.5V, CL = 15 pF
Between 0.2VDD - 0.8VDD, VDD = 4.5V - 5.5V, CL = 50 pF
Between 0.2VDD - 0.8VDD, VDD = 3.0V - 3.6V, CL = 30 pF
Between 0.2VDD - 0.8VDD, VDD = 2.7V - 3.6V, CL = 15 pF
1.8
1.2
0.9
3.4
4.0
2.4
ns
ns
ns
ns
ns
ns
t4
Startup time out of power
down
PD# pin LOW to HIGH[8]
1
2
ms
ns
ns
t5a
t5b
Power down delay time
(synchronous setting)
PD# pin LOW to output LOW
(T = period of output clk)
T/2
10
T+10
15
Power down delay time
(asynchronous setting)
PD# pin LOW to output LOW
t6
Power up time
From power on[8]
1
2
ms
ns
t7a
Output disable time
(synchronous setting)
OE pin LOW to output Hi-Z
(T = period of output clk)
T/2
T+10
t7b
t8
Output disable time
(asynchronous setting)
OE pin LOW to output Hi-Z
10
T
15
ns
Output enable time
(always synchronous
enable)
OE pin LOW to HIGH
(T = period of output clk)
1.5T+2 ns
5
t9
Peak-to-peak period jitter
VDD = 4.5V - 5.5V, Fo > 33 MHz, VCO > 100 MHz
VDD = 2.7V - 3.6V, Fo > 33 MHz, VCO > 100 MHz
±100 ±125
±125 ±200
±250 1% of
FO
ps
ps
ps
VDD = 2.7V - 5.5V, Fo < 33 MHz
Notes
7. Not all parameters measured in production testing.
8. Oscillator start time cannot be guaranteed for all crystal types. This specification is for operation with AT cut crystals with ESR < 70 ohms.
Document Number: 38-07354 Rev. *E
Page 8 of 11
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CY2037
Switching Waveforms
Figure 2. Duty Cycle Timing (t1w, 1x, t1y, t1z)
t
t
1B
t
1A
OUTPUT
Figure 3. Output Rise/Fall Time
VDD
0V
OUTPUT
t
2
t
3
Figure 4. Power Down Timing (synchronous and asynchronous modes)
VDD
0V
VIH
POWER
DOWN
VIL
t4
CLKOUT
[
(synchronous 9]
)
T
t5a
1/f
CLKOUT
[
(asynchronous 10]
)
t5b
1/f
Figure 5. Power Up Timing
VDD
0V
VDD – 10%
POWER
t6
UP
min. 30 μs
max. 30 ms
CLKOUT
1/f
Notes
9. In synchronous mode the power down or output tri-state is not initiated until the next falling edge of the output clock.
10. In asynchronous mode the power down or output tri-state occurs within 25 ns regardless of position in the output clock cycle.
Document Number: 38-07354 Rev. *E
Page 9 of 11
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CY2037
Ordering Information[11]
Ordering Code
CY2037AWAF
Status
Obsolete
Obsolete
Obsolete
Obsolete
Obsolete
Active
Type
Wafer Thickness
14 ± 0.5 mils
14 ± 0.5 mils
14 ± 0.5 mils
14 ± 0.5 mils
11 ± 0.5 mils
14 ± 0.5 mils
11 ± 0.5 mils
14 ± 0.5 mils
Operating Range
Inked Wafer
Inked Wafer
Inked Wafer
Inked Wafer
Inked Wafer
Inkless Wafer
Inkless Wafer
Inkless Wafer
–10°C to +100°C
–10°C to +100°C
–10°C to +100°C
–10°C to +100°C
–10°C to +100°C
–10°C to +100°C
–10°C to +100°C
–10°C to +100°C
CY2037-2WAF
CY2037-3WAF
CY2037BWAF
CY2037B-11WAF
CY2037BWAF-IL
CY2037B-11WAF-IL
Active
CY2037-2WAF-IL
Obsolete, CY2037BWAF-IL is
recommended for new designs
CY2037-3WAF-IL
Obsolete
Inkless Wafer
14 ± 0.5 mils
–10°C to +100°C
Notes
11. The only difference between the CY2037A/CY2037B, and the CY2037-2 is that the CY2037-2 has the shadow register disabled. CY2037-3 replaces the power
down options with a frequency select and contains the shadow register.
Document Number: 38-07354 Rev. *E
Page 10 of 11
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CY2037
Document History Page
Document Title: CY2037 High-Accuracy EPROM Programmable PLL Die for Crystal Oscillators
Document Number: 38-07354
Orig. of
REV.
ECN NO. Issue Date
Description of Change
Change
DSG
RBI
**
112248
121857
291092
522769
03/01/02
12/14/02
See ECN
See ECN
Change from Spec number: 38-00679 to 38-07354
Power up requirements added to Operating Conditions Information
Updated Min. Operating Temperature, Junction
*A
*B
*C
RGL
RGL
Added CY2037B information. Updated absolute maximum Junction temper-
ature specification. Updated Ordering information table.
Added Die Pad description and coordinates
*D
*E
804376
See ECN
RGL
Minor Change: To post on web
2192266
See ECN DPF/PYRS Added Inkless Die information.
© Cypress Semiconductor Corporation, 2002-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-07354 Rev. *E
Revised March 06, 2008
Page 11 of 11
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided
that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their respective holders.
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