CY2037WAF [CYPRESS]
High Accuracy EPROM Programmable PLL Die for Crystal Oscillators; 高精度EPROM可编程PLL模晶体振荡器
| 型号： | CY2037WAF |
| 厂家： | 
CYPRESS |
| 描述： | High Accuracy EPROM Programmable PLL Die for Crystal Oscillators |
| 文件： | 总7页 (文件大小：89K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
CY2037
High Accuracy EPROM Programmable
PLL Die for Crystal Oscillators
Benefits
Features
• EPROM-programmable die for in-package programming of Enables quick turnaround of custom oscillators
crystal oscillators Lowers inventory costs through stocking of blank parts
• High resolution PLL with 12 bit multiplier and 10 bit divider Enables synthesis of highly accurate and stable output clock
frequencies with zero or low PPM
• EPROM-programmable capacitor tuning array
Enables fine-tuning of output clock frequency by adjusting
of the crystal
C
Load
• Twice programmable die
Enables reprogramming of programmed part, to correct errors,
and control excess inventory
• Simple 4-wire programming interface
Enables programming of output frequency after packaging
• On-chip oscillator runs from 10–30 MHz crystal
Lowers cost of oscillator as PLL can be programmed to a high
frequency using a low-frequency, low-cost crystal
• EPROM-selectable TTL or CMOS duty cycle levels
Duty cycle centered at 1.5V or V /2
DD
Provides flexibility to service most TTL or CMOS applications
• Operating frequency
— 1–200 MHz at 5V
— 1–100 MHz at 3.3V
— 1–66.67 MHz at 2.7V
Services most PC, networking, and consumer applications
• Sixteen selectable post-divide options, using either PLL or Provides flexibility in output configurations and testing
reference oscillator output
• Programmable PWR_DWN or OE pin
Enables low-power operation or output enable function
• Programmable asynchronous or synchronous OE and
PWR_DWN modes
Provides flexibility for system applications, through selectable
instantaneous or synchronous change in outputs
• Low Jitter outputs
Suitable for most PC, consumer, and networking applications
— < ±100ps (pk-pk) at 5V
— < ±125ps (pk-pk) at 3.3V
• 3.3V or 5V operation
Lowers inventory cost as same die services both applications
Enables encapsulation in small-size, surface mount packages
Has lower EMI than oscillators
• Small Die
• Controlled rise and fall times and output slew rate
CY2037 Logic Block Diagram
Die Configuration
Top View
PWR_DWN
or OE
VDD
AVDD
XD
CLKOUT
1
2
10
3
4
5
CONFIGURATION
EPROM
HIGH
ACCURACY
XD
XG
XD
XD
CRYSTAL
N/C
XG
PLL
AVSS
VSS
6
7
9
8
OSCILLATOR
PWR_DWN
or OE
MUX
CLKOUT
/ 1, 2, 4, 8, 16, 32, 64, 128
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
December 24, 1997
PRELIMINARY
CY2037
Functional Description
PLL Output Frequency
The CY2037 is an EPROM programmable, high accuracy,
PLL-based die designed for the crystal oscillator market. The
die attaches directly to a low-cost 10-30MHz crystal and can
be packaged into 4-pin through-hole or surface mount pack-
ages. The oscillator devices can be stocked as blank parts and
custom frequencies programmed in-package at the last stage
before shipping. This enables fast-turn manufacture of custom
and standard crystal oscillators without the need for dedicated,
expensive crystals.
The CY2037 contains a high resolution PLL with 12 bit multi-
plier and 10 bit divider.The output frequency of the PLL is de-
termined by the following formula:
2 • (P + 5)
---------------------------
• FREF
FPLL
=
(Q + 2)
The CY2037 contains an on-chip oscillator and a unique oscil-
lator tuning circuit for fine-tuning of the output frequency. The
crystal C
can be selectively adjusted by programming a set
load
of seven EPROM bits. This feature can be used to compen-
sate for crystal variations or to obtain a more accurate synthe-
sized frequency.
where P is the feedback counter value and Q is the reference
counter value. P and Q are EPROM programmable values.
The CY2037 uses EPROM programming with a simple 2-wire,
Power Management features
4-pin interface that includes V and V . Clock outputs can
SS
DD
be generated up to 200 MHz at 5V or up to 100 MHz at 3.3V.
The entire configuration can be reprogrammed one time allow-
ing programmed inventory to be altered or reused.
The CY2037 contains EPROM programmable PWR_DWN
and OE functions. If Powerdown is selected, all active circuitry
on the chip is shut down when the control pin goes low. The
output is forced to a hard low in this mode and the oscillator
and PLL circuits must re-lock when the part leaves the Power-
down mode. If Output Enable mode is selected, the output is
three-stated when the Control pin goes low. In this mode the
oscillator and PLL circuits continue to operate, allowing a rapid
return to normal operation when the Control input is
deasserted.
The CY2037 PLL die has been designed for very high resolu-
tion. It has a 12 bit feedback counter multiplier and a 10 bit
reference counter divider. This enables the synthesis of highly
accurate and stable output clock frequencies with zero or low
PPM. The clock can be further modified by eight output divider
options of 1, 2, 4, 8, 16, 32, 64 and 128. The divider input can
be selected as either the PLL or crystal oscillator output pro-
viding a total of sixteen separate output options. For further
flexibility, the ouput is selectable between TTL and CMOS duty
cycle levels.
In addition, the PWR_DWN and OE modes can be pro-
grammed to occur synchronously or asynchronously with re-
spect to the output signal. When the asynchronous setting is
used, the powerdown or output three-state occurs immediately
(allowing for logic delays) irrespective of position in the clock
cycle. However, when the synchronous setting is used, the
part waits for a falling edge at the output before powerdown or
output enable is initiated, thus preventing output glitches.
The CY2037 also contains flexible power management con-
trol. The part includes both PWR_DWN and OE features with
integrated pull-up resistors. The PWR_DWN and OE modes
have an additional setting to determine timing (asynchronous
or synchronous) with respect to the output signal.
Controlled rise and fall times, unique output driver circuits, and
innovative circuit layout techniques enable the CY2037 to
have low jitter and accurate outputs making it suitable for most
PC, networking and consumer applications
Crystal Oscillator Tuning Circuit
The CY2037 contains a unique tuning circuit to fine-tune the
output frequency of the device. The tuning circuit consists of
an array of seven load capacitors on the input side of the os-
cillator drive inverter. The capacitor load values are EPROM
programmable and can be increased in small increments. As
the capacitor load is increased the circuit is fine-tuned to a
lower frequency. The capacitor load values vary from 0.17pF
to 8 pF for a 100:1 total control ratio. The tuning increments
are shown in the table below
EPROM Configuration Block
The following table summarizes the features which are config-
urable by EPROM. Please refer to the “CY2037 Programming
Specification” for further details. The specification can be ob-
tained from your local Cypress representative.
Table 1. Crystal Tuning Increments
EPROM Adjustable Features
Feedback counter value (P)
+8pF +4.2pF +2.2pF +1.2pF +0.6pF +0.3pF +0.17pF
Reference counter value (Q)
Output divider selection
Oscillator Tuning (load capacitance values)
Duty cycle levels (TTL or CMOS)
Power management mode (OE or PWR_DWN)
Power management timing
(synchronous or asynchronous)
2
PRELIMINARY
CY2037
Die Pad Summary
Name
Die Pad
Description
V
1
Digital voltage supply
DD
AV
2
Analog voltage supply, 3.3V or 5V
Digital Ground
DD
SS
V
8
SS
AV
9
Analog Ground
X
X
3,4
6
Crystal connection, drain pad. Bond to crystal drain.
Crystal connection, gate pad. Bond to crystal gate.
D
G
PWR_DWN / OE
CLKOUT
N/C
7
EPROM programmable power down or output enable pad. Serves as V in programming mode.
PP
10
5
Clock output. Also serves as three-state input during programming.
No Connect. Do not connect.
Device Functionality: Output Frequencies
Symbol
Description
Condition
Min.
Max.
200
100
66
Unit
MHz
MHz
MHz
Fo
Output frequency
V
V
V
= 4.5–5.5V
= 3.0–3.6V
= 2.7–3.6V
1
1
1
DD
DD
DD
Crystal Oscillator Tuning Circuit
R
f
CRYSTAL
LOCATED
EXTERNAL
TO DIE
C
C
C
C
C
C
C
0
6
5
4
3
2
1
C
C
g
d
T
T
T
T
T
T
T
0
6
5
4
3
2
1
CD = EPROM BIT
T = TRANSISTOR
C = LOAD CAPACITOR
CD
CD
CD
CD
CD
CD
CD
6
5
4
3
2
1
0
Symbol
Description
Feedback resistor, V = 4.5–5.5V
Min
0.5
1.0
Typ
Max
Unit
R
2
4
3.5
9.0
MΩ
MΩ
f
DD
Feedback resistor, V = 3.0–3.6V
DD
C
C
C
C
C
C
C
C
C
Gate capacitor
Drain Capacitor
Series Cap
Series Cap
Series Cap
Series Cap
Series Cap
Series Cap
Series Cap
6.4
8
9.6
pF
pF
pF
pF
pF
pF
pF
pF
pF
g
d
0
1
2
3
4
5
6
12
15
18
0.14
0.26
0.49
0.93
1.77
3.36
6.4
0.17
0.32
0.61
1.16
2.21
4.2
0.20
0.38
0.73
1.39
2.65
5.04
9.6
8
3
PRELIMINARY
CY2037
Absolute Maximum Ratings
Storage Temperature (Non-Condensing)... –55°C to +150°C
Junction Temperature ............................... –55°C to +150°C
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage........................................... >2000V
(per MIL-STD-883, Method 3015)
Supply Voltage..................................................–0.5 to +7.0V
Input Voltage.............................................. –0.5V to V +0.5
DD
Operating Conditions
Parameter
Description
Analog and Digital Supply Voltage
Min.
2.7
Max.
5.5
Unit
V
AV , V
DD
DD
[1]
T
Operating Temperature, Junction
–40
+100
°C
AJ
C
Max. Capacitive Load on outputs for TTL levels
TTL
V
V
V
= 4.5–5.5V, Output frequency = 1–40 MHz
= 4.5–5.5V, Output frequency = 40–125 MHz
= 4.5–5.5V, Output frequency = 125–200 MHz
50
25
15
pF
pF
pF
DD
DD
DD
C
Max. Capacitive Load on outputs for CMOS levels
CMOS
V
V
V
V
V
V
= 4.5–5.5V, Output frequency = 1–66.6 MHz
= 4.5–5.5V, Output frequency = 66.6–125 MHz
= 4.5–5.5V, Output frequency = 125–200 MHz
= 3.0–3.6V, Output frequency = 1–50 MHz
= 3.0–3.6V, Output frequency = 50–100 MHz
= 2.7–3.6V, Output frequency = 1–66.6 MHz
50
25
15
30
15
15
pF
pF
pF
pF
pF
pF
DD
DD
DD
DD
DD
DD
X
Reference Frequency, input crystal
10
30
MHz
REF
Electrical Characteristics Over the Operating Range
Parameter Description
Test Conditions
Min.
Typ.
Max.
Unit
V
V
V
V
V
Low-level Input Voltage
High-level Input Voltage
Low-level Output Voltage
V
V
V
= 4.5–5.5V
= 3.0–3.6V
= 2.7–3.6V
0.8
0.2V
0.2V
V
V
V
IL
DD
DD
DD
DD
DD
V
V
V
= 4.5–5.5V
= 3.0–3.6V
= 2.7–3.6V
2.0
0.5V
0.5V
V
V
V
IH
DD
DD
DD
DD
DD
V
V
V
= 4.5–5.5V, I = 16 mA
= 3.0–3.6V, I = 8 mA
= 2.7–3.6V, I = 8 mA
0.4
0.4
0.4
V
V
V
OL
DD
DD
DD
OL
OL
OL
High-level Output Voltage,
CMOS levels
V
V
V
= 4.5–5.5V, I = –16 mA
= 3.0–3.6V, I = –8 mA
= 2.7–3.6V, I = –8 mA
V
V
V
–0.4
–0.4
–0.4
V
V
V
OHCMOS
OHTTL
DD
DD
DD
OH
DD
DD
DD
OH
OH
High-level Output Voltage,
TTL levels
V
= 4.5–5.5V, I = –16 mA
2.4
V
DD
OH
I
I
I
Input Low Current
Input High Current
V
V
= 0V
10
5
µA
µA
IL
IN
IN
= V
IH
DD
Power Supply Current,
Unloaded
V
V
V
= 4.5–5.5V, Output frequency <= 200 MHz
= 3.0–3.6V, Output frequency <= 100 MHz
= 2.7–3.6V, Output frequency <= 66.6 MHz
45
25
20
mA
mA
mA
DD
DD
DD
DD
I
Stand-by current
V
V
V
= 4.5–5.5V
= 3.0–3.6V
= 2.7–3.6V
10
2
2
50
20
20
µA
µA
µA
DDS
DD
DD
DD
Rup
Input pull-Up resistor
V
V
= 4.5–5.5V, V = 0V
1.1
15
3.0
30
8.0
100
MΩ
kΩ
DD
DD
IN
= 4.5–5.5V, V = 0.7V
IN
DD
Note:
1. This product is sold in die form so operating conditions are specified for the die, or junction temperature
4
PRELIMINARY
CY2037
Output Clock Switching Characteristics Over the Operating Range
Symbol
Description
Test Conditions
1–27 MHz, C <= 50 pF
Min
Typ
Max
Unit
t
Output Duty Cycle at
45
45
40
40
55
55
60
60
%
%
%
%
1w
L
1.4V, V = 4.5–5.5V
27–80 MHz, C <= 15pF
DD
L
t
= t ÷ t
27–125 MHz, C <= 25pF
L
1w
1A
1B
125–200 MHz, C <= 15pF
L
t
t
t
t
Output Duty Cycle at
1–66.6 MHz, C <= 50 pF
45
40
40
55
60
60
%
%
%
1x
1y
1z
2
L
V
/2, V = 4.5–5.5V 66.6–125 MHz, C <= 25 pF
DD
DD
L
t
= t ÷ t
125–200 MHz, C <= 15pF
1x
1A
1B
L
Output Duty Cycle at
/2, V = 3.0–3.6
1–50 MHz, C <= 30 pF
45
40
55
60
%
%
L
V
50–100 MHz, C <= 15pF
DD
DD
L
t
= t ÷ t
1y
1A 1B
Output Duty Cycle at
1–40 MHz, C <= 15 pF
45
40
55
60
%
%
L
V
/2, V = 2.7–3.6V 40–66.6 MHz, C <= 15 pF
DD
DD
L
t
= t ÷ t
1z
1A 1B
Output Clock Rise time Between 0.8 –2.0V, V = 4.5V–5.5V, C = 50 pF
1.8
1.2
0.9
3.4
4.0
2.4
4.0
ns
ns
ns
ns
ns
ns
ns
DD
L
Between 0.8 –2.0V, V = 4.5V–5.5V, C = 25 pF
DD
L
L
Between 0.8 –2.0V, V = 4.5V–5.5V, C = 15 pF
DD
Between 0.2V – 0.8V , V = 4.5V–5.5V, C = 50 pF
DD
DD
DD
L
Between 0.2V – 0.8V , V = 3.0V–3.6V, C = 30 pF
DD
DD
DD
DD
L
L
Between 0.2V – 0.8V , V = 3.0V–3.6V, C = 15 pF
DD
DD
Between 0.2V – 0.8V , V = 2.7V–3.6V, C = 15 pF
DD
DD
DD
L
t
Output Clock Fall time Between 0.8V–2.0V, V = 4.5V–5.5V, C = 50 pF
1.8
1.2
0.9
3.4
4.0
2.4
4.0
ns
ns
ns
ns
ns
ns
ns
3
DD
L
Between 0.8 –2.0V, V = 4.5V–5.5V, C = 25 pF
DD
L
Between 0.8 –2.0V, V = 4.5V–5.5V, C = 15 pF
DD
L
Between 0.2V – 0.8V , V = 4.5V-5.5V, C = 50 pF
DD
DD
DD
L
Between 0.2V – 0.8V , V = 3.0V–3.6V, C = 30 pF
DD
DD
DD
L
Between 0.2V – 0.8V , V = 3.0V–3.6V, C = 15 pF
DD
DD
DD
L
Between 0.2V – 0.8V , V = 2.7V–3.6V, C = 15 pF
DD
DD
DD
L
[2]
t
t
t
Start-up time out of
power-down
PWR_DWN or OE pin LOW to HIGH
1
2
ms
ns
ns
4
Power Down delay time PWR_DWN pin HIGH to output LOW
(synchronous setting) (T=frequency oscillator period)
T/2
10
T+10
15
5a
5b
Power Down delay time PWR_DWN pin HIGH to output LOW
(asynchronous setting)
[2]
t
t
Power Up time
From power on
1
2
ms
ns
6
Output disable time
OE pin HIGH to output Hi-Z
T/2
T+10
7a
(synchronous setting)
(T=frequency oscillator period)
t
Output disable time
(asynchronous setting)
OE pin HIGH to output Hi-Z
10
15
ns
ns
7b
t
t
Output enable time
PWR_DWN or OE pin LOW to HIGH
100
8
Peak-to-Peak Period
Jitter
V
V
V
= 4.5V–5.5V, Fo > 33 MHz, VCO > 100 MHz
= 3.0V–3.6V, Fo > 33 MHz, VCO >100 MHz
= 3.0V–5.5V, Fo <33 MHz
±50
±75
±100
±100
±125
±250
ps
ps
ps
9
DD
DD
DD
Note:
2. Oscillator start time cannot be guaranteed for all crystal types. This specification is for operation with AT cut crystals with ESR < 70 ohms.
5
PRELIMINARY
CY2037
Switching Waveforms
Duty Cycle Timing (t
t
t
t )
1w, 1x, 1y, 1z
t
1B
t
1A
OUTPUT
Output Rise/Fall Time
OUTPUT
VDD
0V
t
2
t
3
Power Down Timing (synchronous and asynchronous modes)
VDD
VIH
POWER
DOWN
VIL
t4
0V
CLKOUT
[3
]
(synchronous
)
T
t5a
1/f
CLKOUT
[4
]
(asynchronous
)
t5b
1/f
Power Up Timing
VDD
0V
V
DD-10%
POWER
UP
t6
min 2ns
CLKOUT
1/f
Notes:
3. In synchronous mode the powerdown or output 3-state is not initiated until the next falling edge of the output clock.
4. In asynchronous mode the powerdown or output 3-state occurs within 25ns irrespective of position in the ouput clock cycle.
6
PRELIMINARY
CY2037
Switching Waveforms (continued)
Output Enable Timing (synchronous and asynchronous modes)
VDD
VIH
OUTPUT
ENABLE
VIL
0V
T
CLKOUT
High Impedance
[3
]
(synchronous
)
t7a
t8
CLKOUT
High Impedance
[4
]
(asynchronous
)
t7b
t8
Ordering Information
Die Size Dimensions
Ordering Code
Type
Wafer
Operating Range
x by y
1497x1105 microns
14 ±0.5 mils
CY2037WAF
Industrial
Wafer Thickness
Document #: 38–00679
© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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