FX623P [CMLMICRO]
Call Progress Tone Decoder; 呼叫进程音解码器
| 型号： | FX623P |
| 厂家： | 
CML MICROCIRCUITS |
| 描述： | Call Progress Tone Decoder |
| 文件： | 总6页 (文件大小：50K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CML Semiconductor Products
PRODUCT INFORMATION
Call Progress Tone Decoder
FX623
Publication D/623/3 July 1994
Provisional Issue
Features
Measures Call Progress Tone
Custom Tone Decoder
[13 Call-Progress Frequencies
Recognized]
Frequencies
[‘Busy’, ‘Dial’, ‘Fax-Tone’ etc.]
Telephone, PABX, Fax and
Dial-Up Modem Applications
Operates to a 3.579545MHz
Telephone System Clock
Low-Power Requirement
(600µA at 3.3 VoltsTYP)
for Line-Powered Applications
Operates Under Simple Logic
or µProcessor System Control
V
DD
SIGNAL IN
MEASUREMENT
DIGITAL
FILTER
AND
DECODE
V
SS
LIMITER
CHIP SELECT
XTAL/CLOCK
DATA
CHANGE
Clocks
XTAL/CLOCK
OSCILLATOR
Clocks
FX623
XTAL
DATA
OUTPUTS
HOLD
Q0
CONTROL
CIRCUITRY
OUTPUT
LATCHES
Q1
Q2
Q3
TIMER
PURS
IRQ
Fig.1 Functional Block Diagram
Brief Description
This information can then be employed in telephone
applications (simple or complex) to control telephone
operations. The data output will require a suitable
software format to analyze the frequency information
from the FX623.
The FX623 is a low-power decoding microcircuit that
measures the frequency of telephone system call
progress tones.
With progress signals input from the telephone line,
this single-chip product is programmed to recognize up
to thirteen of the World's most commonly used
call-progress frequencies, analyze signal quality and
present the measured result as a 4-bit parallel data
word at the tri-state Data Output.
Requiring only a single 3.0[MIN] volt power supply, the
FX623 may be line-powered and will operate under
simple logic or system µProcessor control using the
'Data-Change, 'Hold' and 'Chip-Select' functions.
Using the parallel information from the FX623, the
host system suitably configured, can recognize such
call progress information as: ‘Dial’, ‘Busy’, ‘Number
Unobtainable’, ‘Ringing’ and Fax/Modem system
signals.
The FX623, whose small size and low power
consumption makes it ideal for remote applications,
requires a 3.579545MHz telephone system clock or Xtal
input, is available in a 16-pin plastic DIL package.
Pin Number
Function
FX623P
Q3:
1
2
3
4
Data Outputs: A 4-bit parallel data word, forming a HEX character representing the
decoded tone frequency. This word is output after a successful decode. Table 1 details the
Hex character output codes for the relevant decoded tone frequencies. Upon power-up this
output is set to ‘EH’, but no Data Change pulse generated. These are tri-state outputs.
Q2:
Q1:
Q0:
VDD: Positive supply rail. A minimum supply voltage of 3.0 volts is required. Levels and voltages within
this decoder are dependent upon this supply.
5
6
Signal In: The composite audio input. Signals to this pin should be a.c. coupled. The d.c. bias of the
limiter section is set internally; this pin should not be loaded with any other circuitry.
No internal connection. Leave open circuit.
Xtal: The output of the on-chip clock oscillator inverter.
No internal connection. Leave open circuit.
7
8
9
Xtal/Clock: The input to the clock oscillator inverter. A 3.579545MHz Xtal or externally derived clock
10
should be connected here (see Figure 2).
VSS: Negative supply rail (GND).
11
12
Hold: An input to control the Output Latch condition; employed in combination with the Data Change
output to facilitate, if required, Interrupt and/or handshake operations with a µProcessor.
With Hold placed “Low”, with a tone input, the Data Change output will be held “High” at the next data
change, and the current output code is locked in the Output Latches regardless of any changes to the
input signal.
The output code remains as held until this input is returned “High” (see Figure 3). Whilst this input is
“High” the output data, Q0 - Q3, cycles normally with the input audio.
This pin has an internal 1.0MΩ pullup resistor.
PURS: Power-Up ReSet. To reset internal circuitry at power-up; a logic “1” level is required at this pin
for a duration of at least 2.5mS after the Xtal/Clock input and full VDD levels are applied.
The component configuration shown in Figure 2 is recommended; for slow-rising power supplies the
time constant of components should be increased accordingly.
13
14
IRQ: Interrupt Request. An output for µProcessor operation; normally “High” this output is latched
“Low” when an internal data change occurs if the Chip Select input is “High”. This output is reset
(“High”) the when Chip Select line is taken “Low”.
To permit “wire-OR” connection with other peripherals, this output has a low-impedance when “Low”
and a high-impedance when “High”.
CS: Chip Select- A controlling function. When held “High” the Data Outputs Q0, Q1, Q2 and Q3 and
the Data Change output are disabled.
When taken “Low” the Data Outputs Q0, Q1, Q2 and Q3 and the Data Change output are enabled;
the Interrupt Request (IRQ) is reset (“High”) when CS is taken “Low”. See Figures 3 and 4.
15
16
Data Change: A positive-going pulse is generated at this output when the data changes (Tone or
NOTONE). New tone-data is presented to the Q0, Q1, Q2 and Q3 Data Outputs if the Hold input is set
“High”. This is a tri-state output.
2
Application Information
V
DD
C
5
V
SS
DATA CHANGE
CS
Q3
Q2
Q1
Q0
1
2
3
4
5
6
7
8
DATA OUTPUTS
16
15
14
13
12
11
10
9
C
1
A HEX Code
Output representing
the decoded tone
frequency
IRQ
See Table 1
P U R S
HOLD
FX623P
V
DD
V
COMPOSITE SIGNAL IN
SIGNAL IN
SS
C
XTAL/CLOCK
2
XTAL
R
1
X
1
R
2
C
C
3
4
V
SS
Fig.2 Recommended External Components
Band Edges (Hz) Nominal
Component
Value
Hex
Output Code Lower
Upper
Edge
Centre
Freq.
R1
R2
C1
C2
C3
C4
C5
X1
1.0MΩ
1.0MΩ
Character Q3 Q2 Q1 Q0
Edge
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
364
488
386
520
375
500
47.0nF
4.7nF
2
3
520
580
580
618
550
600
33.0pF
33.0pF
4
5
386
412
412
436
400
425
1.0µF
6
436
463
450
3.579545MHz
7
8
463
900
487
475
950
Tolerances R = ±10%
C = ±20%
1008
1325
1455
1855
2140
9
1273
1350
1750
2062
1300
1400
1800
2100
A
B
C
D
E
F
frequency not guaranteed
frequency not guaranteed
NOTONE
Table 1 Tone Decode Frequencies
Timing Information
With CS Low - Figure 3.
After initial power-up and the Hold input inactive
(High), as frequencies are input, with the Data Change
output as an active (High) indicator, the data is
presented at the Data Outputs.
With the Hold input held High - Figure 4.
As frequencies are input a correct decode will
produce an active (Low) interrupt level.
This interrupt (IRQ) is serviced and reset by an
active (Low) CS input.
If/when the Hold input is placed active (Low), the
data at the Data Outputs is frozen and the Data
Change output held High at its next active excursion -
until the Hold input is returned High.
Note the ‘valid data’ period at the Data Outputs.
3
Application Information
Decoder Timing
VDD
tPURS
PURS
NOTONE
SIGNAL IN NOTONE
Tone 1
Tone 2
Tone 3
Tone ’N’
tNT
tDE
tRESP
OUTPUTS
Q0 to Q3
’N’
t DC
t PUL
DATA CHANGE
HOLD
t HOLD
t NORM
Fig.3 Timing with the Chip Select Input Held “Low”; CS and IRQ are not used
VDD
tPURS
PURS
SIGNAL IN
NOTONE
Tone 1
OUTPUTS
Q0 - Q3
E
F
1
(INTERNAL)
DATA CHANGE
t RIRQ
IRQ
t IR
CS
tHIZ
tACS
DATA OUT Q0 - Q3
TRI-STATE
TRI-STATE
VALID DATA
(READ DATA)
VALID DATA
(READ DATA)
Fig.4 Timing with the HOLD Input Held “High”; CS and IRQ are used
4
Specification
Absolute Maximum Ratings
Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits
is not implied.
Supply voltage
-0.3 to 7.0V
Input voltage at any pin (ref VSS = 0V)
-0.3 to (VDD + 0.3V)
Sink/source current (supply pins)
(other pins)
+/- 30mA
+/- 20mA
Total device dissipation @ TAMB 25°C
Derating
800mW Max.
10mW/°C
Storage temperature range:
FX623P
-40°C to +85°C (plastic)
Operating Limits ......
Supply Voltage (VDD)
Min.
3.0
Max.
5.5
Unit
V
at 25°C
Operating Temperature ......
-40
+85
°C
All device characteristics are measured under the following conditions unless otherwise specified:
VDD = 3.3V, TOP = -40 to +85 °C. Audio Level 0dB ref: = 775mVrms. Xtal/Clock Frequency = 3.579545MHz
Characteristics
See Note
Min.
Typ.
Max.
Unit
Static Values
Supply Current
Input Logic “1”
Input Logic “0”
Output Logic “1”
-
0.7
-
0.8
-
0.6
1.0
-
0.3
mA
-
-
-
-
%VDD
%VDD
%VDD
%VDD
-
Output Logic “0”
0.2
Impedance
CS and PURS Input
Hold Input
Signal Input
IRQ Output (logic “1”)
IRQ Output (logic “0”)
Q0 - Q3 & Data-Change Outputs (logic “1”)
Q0 - Q3 & Data-Change Outputs (logic “0”)
Q0 - Q3 & Data-Change Outputs (high Z)
Dynamic Values
10.0
0.5
0.1
-
-
-
-
-
-
-
-
-
-
MΩ
MΩ
MΩ
kΩ
Ω
kΩ
Ω
MΩ
1
30.0
175
0.7
175
-
100
500
2.0
500
-
1.0
Signal Input Range
Decode Bandedge Tolerance
Xtal Inverter
2, 5
3
35.0
-1.0
1,166
1.0
mVrms
%
-
Voltage Gain
Input Impedance
Output Impedance
20.0
10.0
-
-
-
-
-
-
V/V
MΩ
kΩ
160
Decoder Timing - Figures 3 and 4
Power Up Reset Time
Data 'E' Time
tPURS
tDE
tRESP
tNT
2.5
31.0
-
-
-
-
-
-
ms
ms
ms
ms
ms
ms
µs
µs
ms
ns
NOTONE to Tone Response Time
Tone to NOTONE Response Time
Data to Data-Change Pulse Time
Data-Change Pulse Width
Hold to Data-Change Rise Time
HOLD to Data-Change Fall Time
IRQ Tone Response Time
IRQ Reset Time
4
4
27.0
-
-
1.25
-
-
50.0
60.0
1.15
-
tDC
0.625
tPUL
tHOLD
tNORM
tRIRQ
tIR
-
63.0
-
-
-
-
-
-
150
52.0
250
250
100
29.0
-
-
-
Data Access Time
CS High to Output Tri-State Time tHIZ
tACS
ns
ns
Notes
1. This pin has an on-chip 1.0MΩ pullup resistor.
2. An a.c. coupled sine or squarewave.
3. See Table 1, Tone Decode Frequencies.
4. Delay between the change of input (Tone/NOTONE) and the change at the Q0 - Q3 outputs.
5. The signal input maximum value is determined by the formula VDD/2.83.
5
Package Outlines
The FX623 is available in the package styles outlined
below. Mechanical package diagrams and specifications
are detailed in Section 10 of this document.
Handling Precautions
The FX623 is a CMOS LSI circuit which includes input
protection. However precautions should be taken to
prevent static discharges which may cause damage.
Pin 1 identification marking is shown on the relevant
diagram and pins on all package styles number
anti-clockwise when viewed from the top.
FX623P
16-pin plastic DIL
(P3)
NOT TO SCALE
Max. Body Length 20.57mm
Max. Body Width
6.60mm
Ordering Information
FX623P
16-pin plastic DIL
(P3)
CML does not assume any responsibility for the use of any circuitry described. No circuit patent licences are implied
and CML reserves the right at any time without notice to change the said circuitry.
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