FX641D2 [CMLMICRO]
Dual Subscriber Private Metering (SPM) Detector; 双用户私人测光（ SPM ）检测器
| 型号： | FX641D2 |
| 厂家： | 
CML MICROCIRCUITS |
| 描述： | Dual Subscriber Private Metering (SPM) Detector |
| 文件： | 总13页 (文件大小：130K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CML Semiconductor Products
PRODUCT INFORMATION
Dual Subscriber Private
Metering (SPM) Detector
FX641
Publication D/641/4 February 2001
Provisional Issue
Features
Two (12kHz/16kHz) SPM
Detectors on a Single Chip
Selectable Tone Follower or
Packet Mode Outputs
Detects 12kHz and 16kHz SPM
Frequencies
High Speech-Band Rejection
Properties
Xtal Accuracy; Stable Frequency
Limits
“Output Enable” Multiplexing
Facility
“Controlled” (µC) and “Fixed”
Signal Sensitivity Modes
Call-Charge Applications on
PABX Line Cards
VDD
CLOCK OUT
CLOCK IN
XTAL/CLOCK
VBIAS
XTAL/CLOCK
BUFFER
CLOCK
DIVIDERS
INTERNAL
CLOCKS
GENERATOR
VSS
XTAL
12kHz/16kHz
SYSTEM
TONE FOLLOWER
Ch 1 AMP OUT
Ch1 AMP IN (-)
Ch
1
MODE
Ch 1
OUTPUT
COMPARATOR
-
-
PULSE
GENERATOR
AND
PULSE
MEASUREMENT
LOGIC
Ch 1
BANDPASS
FILTER
PULSE
LENGTH
LOGIC
OUTPUT
SELECT
CIRCUITS
+
+
DIVIDER
Ch1 AMP IN (+)
Ch
1
PACKET
MODE
INPUT
INTERNAL
COMPARATOR
THRESHOLD
AMPLIFIER
GAIN
ADJUST
CHANNEL 1
PRESET LEVEL
CHIP SELECT
OUTPUT
ENABLE
12kHz/16kHz
SYSTEM
SERIAL
DATA
FX641
12kHz/16kHz
SYSTEM
SERIAL
INPUT
LOGIC
LEVEL/
SYSTEM
SETTING
OUTPUT
SELECT
SERIAL
CLOCK
SYSTEM SELECT
INTERNAL
COMPARATOR
THRESHOLD
Ch
2
GAIN
ADJUST
CHANNEL 2
INPUT
PACKET
MODE
AMPLIFIER
-
Ch2 AMP IN (-)
+
-
PULSE
GENERATOR
AND
PULSE
MEASUREMENT
LOGIC
Ch 2
BANDPASS
FILTER
PULSE
LENGTH
LOGIC
OUTPUT
SELECT
CIRCUITS
+
DIVIDER
Ch2 AMP IN (+)
Ch 2 AMP OUT
Ch 2
OUTPUT
Ch
2
COMPARATOR
TONE FOLLOWER
MODE
Fig.1 Functional Block Diagram
Brief Description
The FX641 is a low-power, system-selectable Dual
Subscriber Private Metering (SPM) Detector -two
detectors on a single chip- to indicate the presence,
on a telephone line, of either 12kHz or 16kHz
telephone call-charge frequencies.
The digital output is pin-selectable to one of three
modes:
(1) Tone Follower mode -a logic level for the period of
a correct decode.
(2) Packet mode -respond/de-respond after a
cumulative period of tone or notone in a preset
period.
(3) High-impedance output -for device multiplexing.
For non-µProcessor systems a preset sensitivity/system
input allows external channel level and system setting.
This device, which is suitable for PBX and PABX
line-card and remote telephone installations, is available
in compact 24-pin plastic DIL and small outline (S.O.I.C.)
packages.
Under µProcessor control via a common serial
interface, each channel of the FX641 will detect
call-charge pulses from a telephone line and provide a
digital output for recording, billing or security
purposes.
A common set of external components and a stable
3.579545MHz Xtal/clock input ensures that the FX641
adheres accurately to most national “Must and Must-
Not” decode band-edges and threshold levels.
The FX641 requires approximately 4.5mA at 5-volts.
Pin Number
Function
FX641
D2/P4
1
Xtal/Clock: The input to the on-chip clock oscillator; for use with a 3.579545MHz Xtal in conjunction
with the Xtal output; circuit components are on-chip. When using a Xtal input, the Clock Out pin
should be connected directly to the Clock In pin. If a clock pulse input is employed to the Clock In pin,
this (Xtal/Clock) pin must be connected directly to VDD (see Figure 2). See Figure 4 for details of clock
frequency distribution.
2
3
Xtal: The output of the on-chip clock oscillator inverter.
Clock Out: The buffered output of the on-chip-clock oscillator inverter. If a Xtal input is employed,
this output should be connected directly to Clock In pin. This output can support up to 3 additional
FX641 microcircuits. See Figure 4 for details of clock frequency distribution.
4
5
Clock In: The 3.579545 clock pulse input to the internal clock dividers. If an externally generated
clock pulse input is employed, the Xtal/Clock input pin should be connected to VDD.
Output Enable: For multi-chip output multiplexing; controls the state of both Ch1 and Ch2 outputs.
When this input is placed high (logic '1') both outputs are set to a high impedance. When placed low
(logic '0') both outputs are enabled.
6
7
8
Ch 2 Output: The digital output of the Channel 2 SPM detector when enabled. The format of the
signal at this pin, in common with Ch 1, is selectable to either 'Tone Follower' or 'Packet' mode via the
Output Select input.
Ch 1 Output: The digital output of the Channel 1 SPM detector when enabled. The format of the
signal at this pin, in common with Ch 2, is selectable to either 'Tone Follower' or 'Packet' mode via the
Output Select input.
VBIAS: The output of the on-chip analogue bias circuitry. Held internally at VDD/2, this pin should be
decoupled to VSS (see Figure 2).
Ch 1 Amp Out: The output of the Channel 1 Input Amplifier. See Figures 2 and 3.
Ch 1 Amp In (-): The negative input to the Channel 1 Input Amplifier. See Figures 2 and 3.
Ch 1 Amp In (+): The positive input to the Channel 1 Input Amplifier. See Figures 2 and 3.
VSS: Negative supply rail (GND).
9
10
11
12
Pin Number
Function
FX641
D2/P4
13
14
15
16
17
No internal connection; leave open circuit.
Ch 2 Amp In (+): The positive input to the Channel 2 Input Amplifier. See Figures 2 and 3.
Ch 2 Amp In (-): The negative input to the Channel 2 Input Amplifier. See Figures 2 and 3.
Ch 2 Amp Out: The output of the Channel 2 Input Amplier. See Figures 2 and 3.
Output Select: A logic input to set the Channel 1 and Channel 2 output modes.
When high (logic '1'), the outputs are in the Tone Follower mode; when low (logic '0'), the outputs are
in the Packet mode.
18
19
Preset Level: A logic input to set the sensitivity mode of the FX641.
When high (logic '1'), both channels are in the Fixed Sensitivity mode. The external components
govern the input sensitivity; the System Select input selects 12kHz or 16kHz operation. When low
(logic '0'), both channels are in the Controlled Sensitivity mode. Device sensitivities and system
selection are via the Chip Select/Serial Data/Serial Clock inputs. This input has an internal pullup
resistor on chip (Fixed Sensitivity Mode).
Chip Select: The Chip Select input for use in data loading when using the FX641 in the Controlled
Sensitivity mode (see Figure 9).
The device is selected when this input is set low (logic '0').
When the device is in the Fixed Sensitivity mode this input should be connected to either VSS or VDD.
Serial Clock: The Serial Clock input for use in data loading when using the FX641 in the Controlled
Sensitivity mode (see Figure 9). Data is loaded to the FX641 on this clock's rising edge.
When the device is in the Fixed Sensitivity mode this input should be connected to either VSS or VDD.
20
21
22
Serial Data: The Serial Data input for use in data loading when using the FX641 in the Controlled
Sensitivity mode (see Figure 9 and Table 2).
When the device is in the Fixed Sensitivity mode this input should be connected to either VSS or VDD.
System Select: In the Fixed Sensitivity mode this pin selects the system frequency.
High (logic ‘1’) = 12kHz; Low (logic ‘0’) = 16kHz.
In the Controlled Sensitivity mode this pin should be tied to Vdd or left unconnected.
This pin has an internal pullup resistor on chip.
No internal connection; leave open circuit.
23
24
VDD: Positive supply rail; a single, stable power supply is required. Critical levels and voltages within
the FX641 are dependant upon this supply. This pin should be decoupled to VSS by a capacitor
mounted close to the pin.
Application Information
VDD
C1
XTAL/CLOCK
XTAL/CLOCK
X1
VDD
1
24
23
22
21
20
19
18
17
16
15
14
13
V SS
For use with a Clock Pulse input
- Remove Xtal (X1)
- Connect Pin 1 to VDD
- Remove link (Pins 3/4)
- Input clock pulses to CLOCK IN
See Figure 4
2
XTAL
OUT
CLOCK
SYSTEM SELECT
SERIAL DATA
3
IN
4
CLOCK IN
SERIAL CLOCK
CHIP SELECT
OUTPUT ENABLE
5
Ch2 OUTPUT
Ch1 OUTPUT
6
PRESET LEVEL
OUTPUT SELECT
FX641D2
7
VBIAS
8
R7
Ch1 AMP OUT
Ch1 AMP IN (-)
Ch2 AMP OUT
9
Ch2 AMP IN (-)
R5
C3
C4
R3
C5
10
11
12
R1
R2
R6
V SS
Ch2 AMP IN (+)
Ch1 AMP IN (+)
C6
R4
R8
C2
V SS
Component
Value
68kΩ
68kΩ
750kΩ
750kΩ
68kΩ
68kΩ
750kΩ
750kΩ
Tolerance
± 1%
±1%
R1
R2
R3
R4
R5
R6
R7
R8
C1
C2
C3
C4
C5
C6
1.0µF
±20%
±20%
±5%
±5%
±5%
±5%
1.0µF
270pF
270pF
270pF
270pF
±1%
±1%
± 1%
± 1%
±1%
±1%
X1
3.579545MHz
Fig.2 Recommended External Components
Fixed Sensitivity Setting
Note that when calculating/selecting gain components, R3, R4, R7 and R8 should always be greater than or equal to
100kΩ.
Differential Input
Common Mode Input
INPUT AMP
INPUT AMP
-
-
Tip (a)
+
+
Ring (b)
FX641 (part)
VBIAS
FX641 (part)
VBIAS
VSS
VSS
Fig.3 Example Input Configurations
Application Information ......
CLOCK
IN
CLOCK
IN
CLOCK
IN
CLOCK
OUT
CLOCK
IN
XTAL/CLOCK
FX641
µController
FX641
FX641
FX641
(used as
Master
Oscillator)
X1
XTAL
I/O Ports
VDD
Ch 2
Ch 1
3 to’N’ LINE
DECODER
"OUTPUT ENABLE"
ADDRESSING
Maximum number of driven clocks (including Master) = 4
Maximum capacitive load on Clock Out output = 15.0pF
Fig.4 Examples of Xtal/Clock Distribution and Output Multiplexing
Channel Outputs
Xtal/Clock Distribution
Channels 1 and 2 outputs operate together under
the control of the Output Enable and Output Select
inputs. Table 3 describes the operations.
The FX641 requires a 3.579545MHz Xtal or clock
pulse input. With the exception of the Xtal, all oscillator
components are incorporated on chip. If a Xtal input is
employed the Clock Out pin should be directly linked to
the Clock In pin.
The Front Page description describes the output
formats.
To reduce component and layout complexity, the
clock requirements of up to 3 additional FX641
microcircuits may be supplied from a Xtal-driven
FX641 acting as the system master clock. With
reference to Figure 4, the clock should be distributed
as illustrated and the Xtal/Clock pins of the driven
microcircuits should be connected directly to VDD.
Note that the maximum load on the master Clock Out
pin should not be exceeded.
SIGNAL INPUT
TONE
NOTONE
Ch1 and Ch 2 OUTPUTS
TONE FOLLOWER OUTPUT
RESPONSE
DELAY
PACKET MODE OUTPUT
SIGNAL INPUT ......
TONE FOLLOWER OUTPUT ......
DERESPONSE
DELAY
PACKET MODE OUTPUT ......
Fig.5 Tone Follower and Packet Mode Outputs
Application Information ......
Sensitivity Setting
To enable the FX641 to operate correctly to most national 12kHz and 16kHz SPM specifications, the input
sensitivity can be accurately adjusted and set.
There are two different pin-selectable modes of sensitivity setting available to the FX641: Controlled Sensitivity
Mode and Fixed Sensitivity Mode
The Controlled Sensitivity mode allows the sensitivity setting from a µController via a 6-bit serial data input. This
same serial input also sets operation (bit 0) to either 12kHz or 16kHz systems. Both channels are set identically.
The Fixed Sensitivity mode allows the sensitivity of each channel to be set to a fixed “gain” by external
components at the input amplifiers. Operation to either 12kHz or 16kHz is by the System Select input.
Controlled Sensitivity Setting
12kHz System
Bit D0 = ‘1’
16kHz System
Bit D0 = ‘0’
Serial Data
Bits
D5 - D1
Bandpass
Filter Gain
(dB)
Minimum Nominal Maximum
Sensitivity Sensitivity Sensitivity
Minimum Nominal Maximum
Sensitivity Sensitivity Sensitivity
dB(ref.)
dB(ref.)
dB(ref.)
dB(ref.)
dB(ref.)
dB(ref.)
0 0 0 0 0
0 0 0 0 1
0 0 0 1 0
0 0 0 1 1
0 0 1 0 0
0 0 1 0 1
0 0 1 1 0
0 0 1 1 1
0 1 0 0 0
0 1 0 0 1
0 1 0 1 0
0 1 0 1 1
0 1 1 0 0
0 1 1 0 1
0 1 1 1 0
0 1 1 1 1
1 0 0 0 0
1 0 0 0 1
1 0 0 1 0
1 0 0 1 1
1 0 1 0 0
1 0 1 0 1
1 0 1 1 0
1 0 1 1 1
1 1 0 0 0
1 1 0 0 1
1 1 0 1 0
1 1 0 1 1
1 1 1 0 0
1 1 1 0 1
1 1 1 1 0
1 1 1 1 1
0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
-16.2
-17.2
-18.2
-19.2
-20.2
-21.2
-22.2
-23.2
-24.2
-25.2
-26.2
-27.2
-28.2
-29.2
-30.2
-31.2
-32.2
-33.2
-34.2
-35.2
-36.2
-37.2
-38.2
-39.2
-40.2
-41.2
-42.2
-43.2
-17.5
-18.5
-19.5
-20.5
-21.5
-22.5
-23.5
-24.5
-25.5
-26.5
-27.5
-28.5
-29.5
-30.5
-31.5
-32.5
-33.5
-34.5
-35.5
-36.5
-37.5
-38.5
-39.5
-40.5
-41.5
-42.5
-43.5
-44.5
-18.8
-19.8
-20.8
-21.8
-22.8
-23.8
-24.8
-25.8
-26.8
-27.8
-28.8
-29.8
-30.8
-31.8
-32.8
-33.8
-34.8
-35.8
-36.8
-37.8
-38.8
-39.8
-40.8
-41.8
-42.8
-43.8
-44.8
-45.8
-16.9
-17.9
-18.9
-19.9
-20.9
-21.9
-22.9
-23.9
-24.9
-25.9
-26.9
-27.9
-28.9
-29.9
-30.9
-31.9
-32.9
-33.9
-34.9
-35.9
-36.9
-37.9
-38.9
-39.9
-40.9
-41.9
-42.9
-43.9
-18.2
-19.2
-20.2
-21.2
-22.2
-23.2
-24.2
-25.2
-26.2
-27.2
-28.2
-29.2
-30.2
-31.2
-32.2
-33.2
-34.2
-35.2
-36.2
-37.2
-38.2
-39.2
-40.2
-41.2
-42.2
-43.2
-44.2
-45.2
-19.5
-20.5
-21.5
-22.5
-23.5
-24.5
-25.5
-26.5
-27.5
-28.5
-29.5
-30.5
-31.5
-32.5
-33.5
-34.5
-35.5
-36.5
-37.5
-38.5
-39.5
-40.5
-41.5
-42.5
-43.5
-44.5
-45.5
-46.5
8.0
9.0
10.0
11.0
12.0
13.0
14.0
15.0
16.0
17.0
18.0
19.0
20.0
21.0
22.0
23.0
24.0
25.0
26.0
27.0
These states should never be used. If senstivities of this order are required (eg. the Swedish Rural SPM
Specification), it is recommended that the Controlled Sensitivity setting is set to 20dB (1 0 1 0 0) and
external components selected to set the Input Amp gain to a higher figure.
Table 2 Controlled Sensitivity Setting Information
The figures provided in Table 2 assume:
1.
2.
3.
The recommended amplifier components (see Figure 2) are employed providing an amplifier gain at
16kHz of 19.8dB ±0.3dB or at 12kHz of 19.1dB ±0.3dB.
A comparator sensitivity of 1.6dB(ref.) ±1dB (the variation being due to filter gain error, filter output offset,
comparator input offset or a combination of all 3).
The applied VDD is 5.0 volts; 0dB (ref.) = 775mVrms.
Application Information ......
Controlled Sensitivity Setting ......
With the external gain (sensitivity) components employed as shown in Figure 2 the gain of the input stages is
19.8dB (12kHz) or 20.5dB (16kHz). For controlled sensitivity setting the gain of each bandpass filter, and hence
the device sensitivity, is adjusted by the applied serial bits D1 to D5.
In the Controlled Sensitivity mode the system frequency is selected by bit D0 (‘1’ = 12kHz; ‘0’ = 16kHz). Data is
loaded Bit 5 (D5) first.
Table 2 details the serial data input to produce the required sensitivity. Minimum, Nominal and Maximum
Sensitivity figures are provided to make complete allowance for internal circuit offsets and component tolerances.
0dB(ref.) = 775mVrms at VDD = 5.0 volts; varies directly with VDD.
Examples are provided as a guide to meeting national specifications.
German FTZ Specification
16kHz
-21dB(ref.)
MUST DECODE
This system has a Must Decode level of -21dB(ref.)
and a Must-Not Decode level of -27dB(ref.). Reference
to Table 2 shows that Bandpass Filter Gain settings of
5dB, 6dB or 7dB will enable an FX641 channel to meet
this level specification.
-21.9
WILL DECODE
-22.9
-23.2 5.0dB
Figure 6 illustrates the range of these various settings.
Hence to meet the German FTZ specification, the
input data (D5 to D0 ) can be:
-23.9
-24.2 6.0dB
-24.5
-25.2 7.0dB
0 0 1 0 1
0 0 1 1 0
0 0 1 1 1
0
0
0
5.0dB
6.0dB
7.0dB
-25.5
WILL-NOT DECODE
or
or
-26.5
Selecting the middle setting would give the greatest
noise immunity.
-27dB(ref.)
MUST-NOT DECODE
Fig.6 German Specification -Possible Settings
French Specification
12kHz
-17.36dB(ref.)
MUST DECODE
This system has a Must Decode level of
-17.36dB(ref.) and a Must-Not Decode level of
-23.8dB(ref.). Reference to Table 2 shows that
-18.2
WILL DECODE
Bandpass Filter Gain settings of 2dB, 3dB or 4dB will
enable an FX641 channel to meet this level
specification.
Fig 7 illustrates the range of these various settings.
Hence to meet the French SPM specification, the
input data (D5 to D0 ) can be:
-19.2
-19.5 2.0dB
-20.2
-20.5 3.0dB
-20.8
-21.5 4.0dB
-22.8
-21.8
WILL-NOT DECODE
0 0 0 1 0
0 0 0 1 1
0 0 1 0 0
1
1
1
2.0dB
3.0dB
4.0dB
or
or
-23.8dB(ref.)
MUST-NOT DECODE
Selecting the middle setting would give the greatest
noise immunity.
Fig.7 French Specification -Possible Settings
System
Select
Preset
Level
Output
Select
Output
Enable
Operating Mode
X
X
0
1
0
1
X
0
0
1
1
1
1
X
0
1
0
0
1
1
X
0
0
0
0
0
0
1
Packet Mode Output;
Tone Follower Output;
Packet Mode Output;
Packet Mode Output;
Tone Follower Output;
Tone Follower Output;
Tristate Output
Serial Data Control
Serial Data Control
Preset Sensitivity 16kHz
Preset Sensitivity 12kHz
Preset Sensitivity 16kHz
Preset Sensitivity 12kHz
High Z
Table 3 Operating Mode Configurations
X = don't care
Application Information ......
-10
-15
-20
MUST DECODE LEVEL
-25
MUST-NOT DECODE LEVEL
-30
-35
-40
-45
MINIMUM AMPLIFIER GAIN
MAXIMUM AMPLIFIER GAIN
-50
-20
-15
-10
-5
0
5
10
15
20
25
AMPLIFIER GAIN (dB)
o
o
VDD = 5.0 (+/- 0.1) VOLTS; TEMP = -40C to +85 C
Fig.8 Input Gain Calculation Graph for use in the Fixed Sensitivity Mode
Application Information ......
Fixed Sensitivity Setting
In this mode the sensitivity of each channel is set
by the correct selection of the components around the
Channel Input Amplifier.
Note that the device sensitivity is directly proportional
to the applied power supply (VDD).
Microcircuit Protection Against High Voltages
Telephone systems may have high d.c. and a.c.
voltages present on the line. If the FX641 is part of a
host equipment that has its own signal input protection
circuitry, there will be no need for further protection as
long as the voltage on any pin is limited to within VDD
+0.3V and VSS -0.3V.
Input Gain Calculation
If the host system does not have input protection, or
there are signals present outside the device's specified
limits, the FX641 will require protection diodes at its
signal inputs (+ and -). The breakdown voltage of
capacitors and the peak inverse voltage of the diodes
must be sufficient to withstand the sum of the d.c.
voltages plus all expected signal peaks.
The input amplifier, with its external circuitry, is
available to set the sensitivity of the FX641 to conform
to the user's national level specification with regard to
‘Must’ and ‘Must-Not’ decode signal levels.
With reference to the graph in Figure 8, the
following steps will assist in the determination of the
requiredgain/attenuation.
Step 1
Aliasing
Draw two horizontal lines from the Y-axis (Signal
Level (dB)).
The upper line will represent the required ‘Must’
decode level.
The lower line will represent the required ‘Must-Not’
decode level.
Due to the switched-capacitor filters employed in
the FX641, care should be taken, with the chosen
external components, to avoid the effects of alias
distortion.
Possible Alias Frequencies:
12kHz Mode
16kHz Mode
=
=
52kHz
69kHz
Step 2
If these alias frequencies are liable to cause
problems and/or interference, it is recommended that
anti-alias capacitors are employed across input
resistors R3 and R4 or R7 and R8.
Values of anti-alias capacitors should be chosen so
as to provide a highpass cutoff frequency, in
conjunction with R3 (R4) (R7) (R8) of approximately
20kHz to 25kHz (12kHz system) or 25kHz to 30kHz
(16kHz system).
Mark the intersection of the upper horizontal line
and the upper sloping line; drop a vertical line from
this point to the X-axis (Amplifier Gain (dB)).
The point where the vertical line meets the X-axis
will indicate the MINIMUM Input Amp gain required
for reliable decoding of valid signals.
Step 3
Mark the intersection of the lower horizontal line
and the lower sloping line; drop a vertical line from
this point to the X-axis.
The point where the vertical line meets the X-axis
will indicate the MAXIMUM allowable Input Amp
gain.
Input signals at or below the ‘Must-Not’ decode
level will not be detected as long as the amplifier
gain is no higher than this level.
i.e. C
=
1
2 x π x f0 x R3
When anti-alias capacitors are used, allowance
must be made for reduced gain at the SPM frequency
(12kHz or 16kHz).
Select the Input Gain Components as described.
Input Gain Components
With reference to the gain components shown in
Figure 2.
The user should calculate and select external
components (R1/R3/C3, R2/R4/C4 and R5/R7/C5, R6/R8/C6)
to provide amplifier gains within the limits obtained in
Steps 2 and 3.
Component tolerances should not move the gain-
figure outside these limits. The graph in Figure 8 is for the
calculation of input gain components for an FX641 using
a VDD of 5.0 (±0.1) volts.
It is recommended that the designed gain is near the
centre of the calculated range.
Specification
Absolute Maximum Ratings
Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits is not
implied.
Supply voltage
-0.3 to 7.0V
Input voltage at any pin (ref VSS = 0V)
-0.3 to (VDD + 0.3V)
Sink/source current (supply pins)
(other pins)
+/- 30mA
+/- 20mA
Total device dissipation @ TAMB 25°C
Derating
800mW Max.
10mW/°C
Operating Temperature (TOP):
Storage Temperature range (TST): FX641D2/P4
FX641D2/P4
-40°C to +85°C
-40°C to +85°C
Operating Limits
Correct operation of the device outside these limits is not implied.
Parameter
Min.
Max.
Unit
Supply Voltage (VDD)
Operating Temperature (TOP)
Xtal/Clock/Clock In Frequency
4.5
-40.0
3.558918
5.5
+85.0
3.589368
V
°C
MHz
Operating Characteristics
All device characteristics are measured under the following conditions unless otherwise specified:
VDD = 5.0V TAMB = -40°C to +85°C. Audio Level 0dB(ref.): = 775mVrms. Noise Bandwidth = 50kHz.
Xtal/Clock or ‘Clock In’ Frequency = 3.579545MHz. System Setting = 12kHz or 16kHz.
Characteristics
See Note
Min.
Typ.
Max.
Unit
Supply Current
Input/Output Parameters
Clock Out Load
-
2.0
5.0
mA
-
-
15.0
pF
Logic Inputs
Input Logic ‘1’
Input Logic ‘0’
Input Leakage Current (VIN = 0 to VDD)
Input Current (VIN = 0)
(High)
(Low)
3.5
-
-5.0
-15.0
-
-
-
-
-
V
V
µA
µA
1.5
5.0
-
13
14
Channel Outputs
Output Logic ‘1’
Output Logic ‘0’
Output Leakage Current (High-Z Output)
Input Amplifier
(IOH) = 120µA) (Enabled)
(IOL) = 360µA) (Enabled)
1
1
2
4.6
-
-5.0
-
-
-
-
V
V
µA
0.4
5.0
D. C. Gain
Bandwidth (-3dB)
Input Impedance
60.0
-
1.0
-
100
-
-
-
-
dB
Hz
MΩ
Overall Performance
12kHz Detect Bandwidth
12kHz Not-Detect Frequencies (below 12kHz)
12kHz Not-Detect Frequencies (above 12kHz
16kHz Detect Bandwidth
16kHz Not-Detect Frequencies (below 16kHz)
16kHz Not-Detect Frequencies (above 16kHz)
Level Sensitivity
3
11.82
-
12.48
15.76
-
12.18
11.52
-
16.24
15.36
-
kHz
kHz
kHz
kHz
kHz
kHz
3
3
3
3
3
-
-
-
-
16.64
Controlled Sensitivity Mode
Preset Sensitivity Mode
3, 4, 12, 15
3, 4, 5, 16
2.6
-25.4
1.6
-26.4
0.6
-27.4
dB(ref.)
dB(ref.)
Signal Quality Requirements for Correct Operation
Signal-to-Noise (Amp Input)
Signal-to-Voice (Amp Input)
Signal-to-Voice (Amp Output)
4, 8, 9, 10
4, 8, 9, 11
4, 8, 10, 11
22.0
-36.0
-1.0
20.0
-40.0
-
-
-
dB
dB
dB
-27.0
Continued on next page ......
Specification ......
Characteristics
See Note
Min.
Typ.
Max.
Unit
Channel Outputs (Ch1 and Ch2) Figure 5
Mode Change Time
Tone Follower Mode (Table 3)
Response and De-Response Time
Packet Mode (Table 3)
6
-
-
-
-
-
500
10.0
48.0
ns
ms
ms
3, 4, 7
3, 4, 7
Response and De-Response Time
40.0
Notes
1.
2.
3.
4.
5.
6.
Tone Follower or Packet mode enabled; see Table 3.
Tristate selected; see Table 3.
With adherence to Signal-to-Voice and Signal-to Noise specifications.
12kHz and/or 16kHz system.
With Input Amp gain setting = 0dB.
Time taken to change between any two of the operational modes: Tone Follower, Packet or Tristate, and with
a maximum capacitive load of 30pF on an output.
7.
The time delay, after a valid serial data load (or after device powerup), before the condition of the outputs can
be guaranteed correct.
8.
Immunity to false responses and/or de-responses.
9.
Common Mode SPM and balanced voice input signal.
10.
With SPM and voice signal amplitudes balanced; to avoid false de-responses due to saturation, the peak-to-
peak voice + noise level at the output of the Input Amp should be no greater than the dynamic range of the
device. For this reason, the signal-to-voice figure at the Am[ Output will vary with the sensitivity setting. The
lowest signal-to-voice figure occurs at the highest sensitivity setting (Table 2, 27dB).
Maximum voice frequencies = 3.4kHz.
With the Input Amplifier gain at 0dB and the Bandpass Filter gain set at 0dB (Table 2); subtract 1.0dB from this
specification for each extra single dB of Bandpass Filter gain programmed.
Alternatively, with the input components as recommended in Figure 2, the sensitivity is as defined in Table 2.
Logic inputs with no internal pullup; Chip Select, Serial Data, Serial Clock, Output Enable, Output Select and
Clock In pins.
11.
12.
13.
14.
15.
Logic inputs with an internal pullup; Preset Level and System Select pins.
Preset Level= ‘0’, System Select = don't care; Chip Select, Serial Clock and Serial Data inputs active;
see Table 3.
16.
Preset Level = ‘1’, System Select = input active; Chip Select, Serial Clock and Serial Data inputs inactive;
see Table 3.
tCSE
CHIP SELECT
tCYC
tCSH
SERIAL CLOCK
SERIAL DATA
tDS
tDH
tPWL
tPWH
Don’t
Care
Data
BIT D5
BIT D4
D3
BIT D0
Fig.9 Data Load Timing for the Controlled Sensitivity Mode
Parameter
Min.
Typ.
Max.
Unit
tPWH
tPWL
tCYC
tCSE
tDH
Serial Clock ‘High’ Pulse Width
Serial Clock ‘Low’ Pulse Width
Serial Clock Period
Chip Select ‘Low’ to Clock ‘High’ Edge
Data Hold Time
Data Setup Time
250
250
600
450
50.0
250
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
tDS
tCSH
Chip Select ‘High’ from:
Clock ‘High’ Edge
50.0
-
-
-
-
1
ns
Clock ‘High’ Edge
serial clock period
Package Outlines
Handling Precautions
The FX641 is a CMOS LSI circuit which includes input
protection. However precautions should be taken to
prevent static discharges which may cause damage.
The FX641 is available in the package styles outlined
below. Mechanical package diagrams and
specifications are detailed in Section 10 of this
document.
Pin 1 identification marking is shown on the relevant
diagram and pins on all package styles number
anti-clockwise when viewed from the top.
FX641D2 24-pin plastic S.O.I.C.
FX641P4 24-pin plastic DIL
NOT TO SCALE
NOT TO SCALE
Max. Body Length 31.85mm
Max. Body Length 15.70mm
Max. Body Width
13.82mm
Max. Body Width
7.65mm
Ordering Information
FX641D2
FX641P4
24-pin plastic S.O.I.C.
24-pin plastic DIL
CML does not assume any responsibility for the use of any circuitry described. No circuit patent licences are implied
and CML reserves the right at any time without notice to change the said circuitry.
CML Microcircuits
COMMUNICATION SEMICONDUCTORS
CML Product Data
In the process of creating a more global image, the three standard product semiconductor
companies of CML Microsystems Plc (Consumer Microcircuits Limited (UK), MX-COM, Inc
(USA) and CML Microcircuits (Singapore) Pte Ltd) have undergone name changes and, whilst
maintaining their separate new names (CML Microcircuits (UK) Ltd, CML Microcircuits (USA)
Inc and CML Microcircuits (Singapore) Pte Ltd), now operate under the single title CML Micro-
circuits.
These companies are all 100% owned operating companies of the CML Microsystems Plc
Group and these changes are purely changes of name and do not change any underlying legal
entities and hence will have no effect on any agreements or contacts currently in force.
CML Microcircuits Product Prefix Codes
Until the latter part of 1996, the differentiator between products manufactured and sold from
MXCOM, Inc. and Consumer Microcircuits Limited were denoted by the prefixes MX and FX
respectively. These products use the same silicon etc. and today still carry the same prefixes.
In the latter part of 1996, both companies adopted the common prefix: CMX.
This notification is relevant product information to which it is attached.
Company contact information is as below:
CML Microcircuits
(UK)Ltd
CML Microcircuits
(USA) Inc.
CML Microcircuits
(Singapore)PteLtd
COMMUNICATION SEMICONDUCTORS
COMMUNICATION SEMICONDUCTORS
COMMUNICATION SEMICONDUCTORS
Oval Park, Langford, Maldon,
Essex, CM9 6WG, England
Tel: +44 (0)1621 875500
Fax: +44 (0)1621 875600
uk.sales@cmlmicro.com
www.cmlmicro.com
4800 Bethania Station Road,
Winston-Salem, NC 27105, USA
Tel: +1 336 744 5050,
0800 638 5577
Fax: +1 336 744 5054
us.sales@cmlmicro.com
www.cmlmicro.com
No 2 Kallang Pudding Road, 09-05/
06 Mactech Industrial Building,
Singapore 349307
Tel: +65 7450426
Fax: +65 7452917
sg.sales@cmlmicro.com
www.cmlmicro.com
D/CML (D)/1 February 2002
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