FX629J [CMLMICRO]
Delta Modulation Codec; DELTA调制编解码器
| 型号： | FX629J |
| 厂家： | 
CML MICROCIRCUITS |
| 描述： | Delta Modulation Codec |
| 文件： | 总10页 (文件大小：95K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CML Semiconductor Products
PRODUCT INFORMATION
Delta Modulation Codec
FX629
Publication D/629/2 July 1994
Provisional Issue
Features/Applications
Designed to Meet Mil-Std-188-113
Military Communications
Programmable Sampling Clocks
3 or 4-bit Compand Algorithm
Forced Idle Facility
Delta MUX, Switch and Phone
Applications
Powersave Facility
Single 5V CMOS Process
Single-Chip Full-Duplex Codec
On-Chip Input and Output Filters
Full-Duplex CVSD* Codec
DATA ENABLE
ENCODER FORCE IDLE
ENCODER INPUT
MOD
VDD
VSS
ENCODER OUTPUT
f1
f 2
XTAL/CLOCK
f 0
XTAL
CLOCK RATE
ENCODER DATA CLOCK
DECODER DATA CLOCK
VBIAS
GENERATORS
FX629
MODE 1
CLOCK MODE
LOGIC
MODE 2
SAMPLING RATE
CONTROL
ALGORITHM
3 or 4-BIT
POWERSAVE
f 3
f 1
DECODER INPUT
DEMOD
DECODER OUTPUT
DECODER FORCE IDLE
Fig.1 Internal Block Diagram
Brief Description
The FX629 is an LSI circuit designed as a
The encoder has an enable function for use in
*Continuously Variable Slope Delta Codec and multiplexer applications.
is intended for use in military communications
systems.
Designed to meet Mil-Std-188-113 with
Encoder and Decoder forced idle facilities are
provided, forcing a 10101010..... pattern in
encode and a VDD/2 bias in decode.
external components, the device is suitable for The companding circuits may be operated with
applications in military Delta Multiplexers,
switches and phones.
Encoder input and decoder output filters are
a pin-selected 3 or 4-bit algorithm.
The powersave facility puts the device into the
standby mode thereby reducing current
incorporated on-chip. Sampling clock rates can consumption when not operating.
be programmed to 16, 32 or 64 k bits/second
from an internal clock generator or may be
externally applied in the range 8 to 64 k bits/
A reference 1.024MHz oscillator uses an
external clock pulse or Xtal input.
The FX629 is a low-power, 5 volt CMOS
second. Sampling clock frequencies are output device and is available in 22-pin cerdip DIL
for the synchronization of external circuits. package.
Pin Number Function
FX629J
1
Xtal/Clock : Input to the clock oscillator inverter. A 1.024MHz Xtal input or externally
derived clock is injected here. See Clock Mode pins and Figure 3.
2
Xtal : Output of clock oscillator inverter. Xtal circuitry shown is in accordance with CML
application note D/XT/1 April 1986.
3
4
No connection
Encoder Data Clock : A logic I/O port. External encode clock input or internal data clock
output. Clock frequency is dependant upon clock mode 1, 2 inputs and Xtal frequency (see
Clock Mode pins).
5
Encoder Output : The encoder digital output, this is a three state output whose condition is
set by Data Enable and Powersave inputs as shown :
Data Enable
Powersave
Encoder Output
Enabled
High Z (o/c)
1
0
1
1
1
0
Vss
6
7
Encoder Force Idle : When this pin is a logical '0' the encoder is forced to an idle state and
the encoder digital output is 0101..., a perfect idle pattern. When this pin is a logical '1' the
encoder encodes as normal. Internal 1MΩ Pullup.
Data Enable : Data is made available at the encoder output pin by control of this input. See
Encoder Output pin. Internal 1MΩ Pullup.
8
9
No connection
Bias : Normally at V /2 bias, this pin requires to be externally decoupled by a capacitor,
C4. Internally pulledDtoD VSS when "Powersave" is a logical '0'.
10
11
Encoder Input : The analogue signal input. Internally biased at VDD /2, external components
are required on this input. The source impedance should be less than 100Ω, output idle
channel noise levels will improve with an even lower source impedance. See Fig. 3.
VSS : Negative Supply.
2
Pin Number Function
FX629J
No connection
12
Decoder Output : The recovered analogue signal is output at this pin, it is the buffered
output of a bandpass filter and requires external components. During "Powersave" this
output is o/c.
13
No connection
14
15
Powersave : A logical '0' at this pin puts most parts of the codec into a quiescent non-
operational state. When at a logical '1' the codec operates normally. Internal 1MΩ Pullup.
Decoder Force Idle : A logical '0' at this pin gates a 0101...pattern internally to the
decoder so that the decoder output goes to VDD/2. When this pin is at a logical '1' the
decoder operates as normal. Internal 1MΩ Pullup.
16
Decoder Input : The received digital signal input. Internal 1MΩ Pullup.
17
18
Decoder Data Clock : A Logic I/O port. External decode clock input or internal data clock
output, dependant upon clock mode 1, 2 inputs, see Clock Mode pins.
Algorithm : A logical '1' at this pin sets this device for a 3-bit companding algorithm. A
logical '0' sets a 4-bit companding algorithm. Internal 1MΩ Pullup.
19
Clock Mode 2 :
20
21
Clock Mode 1
Clock Mode 2
Facility
External clocks
Internal, 64kb/s = f ÷ 16
Internal, 32kb/s = f ÷ 32
Internal, 16kb/s = f ÷ 64
Clock Mode 1 :
Internal 1MΩ
Pullups.
0
0
1
1
0
1
0
1
Clock rates refer to f = 1.024 MHz Xtal/clock input. During internal operation the data clock
frequencies are available at the ports for external circuit synchronization.
Independent or common data rate inputs to Encode and Decode data clock ports may be
employed in the External Clocks mode. Optimum performance will be achieved when the
applied external clocks are synchronous with the master Xtal/clock, and a sub-multiple of
128kHz.
VDD : Positive Supply. A single + 5 volt power supply is required.
22
3
Codec Integration
FX629 PARAMETERS
MEASURED HERE
FX629 PARAMETERS
MEASURED HERE
REGULATED POWER
SUPPLY
FX629
FX629
ANALOGUE
ANALOGUE
OUTPUT
INTERFACE
(BALUN
&
ENCODER
DECODER
INPUT
INTERFACE
(BALUN
&
SYSTEM
INPUT
SYSTEM
OUTPUT
BUFFER)
BUFFER)
DATA
DATA
CLOCK MODE
16/32/64kb/s
CLOCKS
CLOCKS
1.024 MHz
1.024 MHz
SYNCHRONOUS CLOCK
AND
DATA SYSTEM
Fig.2 System Configuration Diagram – showing the FX629, which with the indicated interfacing, will conform to
the Mil-Std-188-113 Specification
Component
Unit Value
Note – with reference to Figure 3 (below)
R1
R2
C1
C2
C3
1M
Selectable
33p
Oscillator Inverter bias resistor.
Xtal Drive limiting resistor.
Xtal Circuit drain capacitor.
Xtal Circuit gate capacitor.
Encoder Input coupling capacitor – The drive source impedance to this
input should be less than 100Ω. Output Idle channel noise levels will
improve with an even lower source impedance.
Bias decoupling capacitor.
33p
1.0µ
C4
C5
X1
1.0µ
1.0µ
1.024 MHz
VDD decoupling capacitor.
A 1.024 MHz Xtal/clock input will yield exactly 16/32/64 kb/s data clock
rates. Xtal circuitry shown is in accordance with CML application note
D/XT/1 April 1986.
Tolerance :– Resistors ± 10% Capacitors ± 20%
VDD
XTAL/CLOCK
VDD
X 1
1
22
21
R1
CLOCK MODE 1
CLOCK MODE 2
XTAL
2
C 2
C1
R 2
N/C
3
20
ENCODER DATA CLOCK
ALGORITHM
4
19
18
17
16
15
14
13
12
DECODER DATA CLOCK
ENCODER OUTPUT
ENCODER FORCE IDLE
DATA ENABLE
5
C5
DECODER INPUT
FX629J
6
DECODER FORCE IDLE
POWERSAVE
N/C
7
N/C
8
BIAS
9
ENCODER INPUT
DECODER OUTPUT
N/C
10
11
C3
VSS
C4
VSS
Fig.3 Recommended External Components
4
Codec Timing Information
ENCODER TIMING
ENCODER
CLOCK
t
t CH
t IR
CH
t CL
t IF
DATA CLOCKED
ENCODER DATA
OUTPUT
tPCO
DECODER TIMING
DECODER
CLOCK
DATA CLOCKED
DECODER DATA
INPUT
tSU
tH
DATA TRUE TIME
MULTIPLEXING FUNCTION
ENCODER
OUTPUT
HIGH Z
HIGH Z
tDR
tDF
DATA ENABLE
TIMING
tCH Clock '1' Pulse Width
tIR Clock Rise Time
tSU Data Set-up Time tSU + tH = Data True Time
1.0µs Min.
100ns Typ.
450ns Min.
tCL Clock '0' Pulse Width
tIF Clock Fall Time
tH Data Hold Time
tPCO Clock to Output Delay Time
1.0µs Min.
100ns Typ.
600ns Min.
750ns Max.
tDR Data Rise Time
tDF Data Fall Time
Xtal Input Frequency
100ns Typ.
100ns Typ.
1.024MHz.
Fig.4 Codec Timing Diagrams
Digital to Analogue Performance ...... Using the bit sequence tests shown in Table 1 (below) at the
Decoder Input pin, the analogue signals measured at the Decoder Output pin are 800Hz ± 10Hz at the levels
described.
Sample Rate
Bit Sequence at Decoder Input
“Run of Threes”
Output Level
(%)
(dBm0)
16kbit/s
32kbit/s
11011011010010010010
1101101101010100100100100100101010110110
0
0
-29.2 ± 2
-30.0 ± 2
16kbit/s
32kbits
11111011010000010010
1111110110101010000100000010010101011110
30
30
0 ± 1
0 ± 1
Table 1 Bit Sequence Tests and Results
at 800Hz
5
Typical Codec Performance ...... relative to the Mil-Std-188-113 Specification
3
2
3
2
1
1
0
0
- 1
- 1
0dBm0 Input Level = 489mVrms
Input Frequency = 800Hz
0dBm0 Input Level = 489mVrms
Input Frequency = 800Hz
- 2
- 3
- 2
- 3
Ref Level: -15dBm0 = 87mVrms
Ref Level: -15dBm0 = 87mVrms
ref.
ref.
13
13
- 30
- 20
- 10
0
10
- 30
- 20
- 10
0
10
Input Level (dBm0)
Fig.5 Gain vs Input Level (16kbit/s)
Input Level (dBm0)
Fig.6 Gain vs Input Level (32kbit/s)
Ref: 0dBm0 Input Level = 489mVrms
Input Frequency = 800Hz
Ref: 0dBm0 Input Level = 489mVrms
Input Frequency = 800Hz
20
15
25
20
15
10
5
0
0
- 30
- 10
- 20
0
- 30
- 10
- 20
Input Level (dBm0)
Input Level (dBm0)
Fig.7 S/N vs Input Level (16kbit/s)
Fig.8 S/N vs Input Level (32kbit/s)
+ 10
1.5
0
1.5
- 10
- 20
- 30
Input Level = -15dBm0
- 40
- 50
ref.
- 60
44.2
5
6
2.6
0.3
0
0.8
1
2
3
Frequency (kHz)
Fig.9 Attenuation Distortion vs Frequency (16kbit/s)
6
Typical Codec Performance ...... relative to the Mil-Std-188-113 Specification
30
Input Level = -15dBm0
Input Level = -15dBm0
20
15
25
20
15
10
10
5
5
3.4
0
1
2
3
0
1
2
3
Input Frequency (kHz)
Input Frequency (kHz)
Fig.10 S/N vs Input Frequency (16kbit/s)
Fig.11 S/N vs Input Frequency (32kbit/s)
100
30% 'run-of-threes
0
90.0
- 6
- 12
- 6dB/octave
Beginning of
discharge
48.0
- 18
- 24
- 30
10.0
3.0
0%
'run-of-threes
X
10
100
1k
10k
X
Frequency (Hz)
Time (ms)
Fig.12 Principal Integrator Response
Fig.13 Compand Envelope
+ 10
3
1
0
2
- 10
- 20
- 30
Input Level = -15dBm0
- 40
- 50
- 60
4 4.2
5
6
2.6
1.4
0
1
2
3
3.4
0.3
Frequency (kHz)
Fig.14 Attenuation Distortion vs Frequency (32kbit/s)
7
Specifications
Absolute Maximum Ratings
Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits is
not implied.
Supply voltage
-0.3 to 7.0V
-0.3 to (VDD + 0.3V)
± 30mA
Input voltage at any pin (ref V = 0V)
Source/sink current (supply piSnSs)
(other pins)
± 20mA
Total device dissipation @ 25°C
Derating
Operating temperature range: FX629J
800mW Max.
10mW/°C
-40°C to +85°C
Storage temperature range:
FX629J
-55°C to +125°C
Operating Limits
All characteristics are measured using the following parameters unless otherwise specified:
VDD = 5.0V, TAMB = 25°C, Xtal/Clock f0 = 1.024MHz, Audio Level 0dB ref (0dBm0) = 489 mV rms.
Audio Test Frequency = 800 Hz. Sample Clock Rate = 32kb/s. Compand Algorithm = 3-bit.
Characteristics
Static Values
See Note
Min.
Typ.
Max.
Unit
Supply Voltage
1
4.5
–
–
3.5
–
4.0
5.0
5.5
0.4
–
–
–
5.5
–
–
–
1.5
–
V
Supply Current (Enabled)
Supply Current (Powersave)
Inputs Logic '1'
Inputs Logic '0'
Outputs Logic '1'
mA
mA
V
V
V
8
8
8
8
Outputs Logic '0'
–
–
1.0
V
Digital Input Impedance
(Logic I/O pins)
1.0
10.0
–
MΩ
Digital Input Impedance
(Logic input pins, pullup resistor)
Digital Output Impedance
Analogue Input Impedance
Analogue Output Impedance
Three State Output Leakage
Current (output disabled)
Insertion Loss
2
300
–
–
–
–
1.0
–
–
4
–
800
kΩ
kΩ
kΩ
Ω
4
7
–
-4.0
-2.0
–
–
+4.0
+2.0
µA
dB
3
1,9
Dynamic Values
Encoder:
Analogue Signal Input Levels
Principle Integrator Frequency
Encoder Passband
Compand Time Constant
Decoder:
5,9
-35.0
127
–
+12.0
212
dBm0
Hz
Hz
159
3400
5.0
4.0
6.0
ms
Analogue Signal Output Levels
Decoder Passband
5,9
-35.0
300
–
–
+12.0
3400
dBm0
Hz
Encoder Decoder (Full codec):
Compression Ratio (Cd = 0.3 to Cd = 0.0)
Passband
–
16:1
–
–
–
–
3400
–
–
–
300
4.2
25.0
–
Hz
kHz
dB
dB
Stopband
Stopband Attenuation (4200Hz to 6000Hz)
(> 6kHz)
60.0
Passband Gain
Passband Ripple (300Hz –1400Hz)
(1400Hz – 2600Hz)
–
0
–
–
–
–
dB
dB
dB
dB
dBm0
dBm0
-1.0
-1.0
-2.0
–
+1.0
+3.0
+3.0
–
(2600Hz – 3400Hz)
Output Noise (Input short circuit)
9
-55.0
-57.0
Perfect Idle Channel Noise (Encoder forced) 9
Group Delay Distortion
(1000Hz to 2600Hz)
–
–
6
–
–
–
–
–
–
–
1024
450
750
1.5
–
µs
µs
ms
kHz
(600Hz to 2800Hz)
(500Hz to 3000Hz)
Xtal/Clock Frequency
8
Specifications ......
Process Information
The following Table gives details of the process and test controls employed in the manufacture of the FX629
'Mil Std' Delta Codec.
Function
Hermeticity
Reference
Remarks
Fine Leak Test –
Coarse Leak Test –
Mil Std 883C
Mil Std 883C
using Method 1014 – test condition A1.
using Method 1014 – test condition C.
Burnin
Mil Std 883C
using Method 1015 – test condition E.
168 Hours @ 85°C with 5v power, and clocks applied.
Temperature Cycling
Mil Std 883C
using Method 1010 – test condition B.
10 cycles -55°C to +125°C.
The following mechanical assembly tests are Qualified to BS9450
Vibration
Shock
BS9450
BS9450
BS9450
Section 1.2.6.8.1
55Hz to 500Hz at 98 m/sec acceleration.
Section 1.2.6.6
981 m/sec for 6 msec.
Low Pressure
Transport and Storage –
Operation –
Section 1.2.6.12
225mmHg (altitude 9000m).
600mmHg (altitude 2400m).
Section 1.2.6.4
Humidity
BS9450
96 Hours @ 45°C, 95% relative humidity plus condensed
water.
Notes: 1. Dynamic characteristics are specified at 5V unless otherwise specified.
2. All logic inputs except, Encoder and Decoder Data Clocks.
3. For an Encoder/Decoder combination, insertion loss contributed by a single component is half this
figure.
4. Driven with a source impedance of <100Ω.
5. Recommended values – See Figures 5, 6, 7 and 8.
6 Group Delay Distortion for the full codec is relative to the delay with 820Hz, -20dB at the encoder input.
7. An Emitter Follower output stage.
8. 4.0V = 80% VDD, 3.5V = 70% VDD, 1.5V = 30% VDD, 1.0V = 20% VDD.
9. Analogue Voltage Levels used in this Data Sheet: 0dBm0 = 489mVrms = - 4dBm = 0dB.
-15dBm0 = 87mVrms. - 20dBm0 = 49mVrms = - 24dBm.
Application Recommendations
Due to the very low levels of signal and idle channel noise required in Military applications – a noisy or badly
regulated power supply could cause instability putting the overall system performance out of specification.
Adherence to the points noted below will assist in minimizing this problem.
(a)
Care should be taken on the design and layout of
(e)
Inputs and outputs should be screened wherever
the printed circuit board.
possible.
(f)
A "ground plane" connected to VSS will assist in
(b)
All external components (as recommended in
eliminating external pick-up on the input and output
pins.
Figure 3) should be kept close to the package.
(c)
Tracks should be kept short, particularly the
(g)
It is recommended that the power supply rails
Encoder Input capacitor and the VBIAS capacitor.
have less than 1mVrms of noise allowed.
(d)
Xtal/clock tracks should be kept well away from
(h)
The source impedance to the Encoder Input pin
analogue inputs and outputs.
must be less than 100Ω, Output Idle channel noise
levels will improve with even lower source impedances.
9
Package Outlines
The FX629 is available in the package style outlined
below. Mechanical package diagrams and specifications
are detailed in Section 10 of this document.
Handling Precautions
The FX629 is a CMOS LSI circuit which includes input
protection. However precautions should be taken to
prevent static discharges which may cause damage.
Pin 1 identification marking is shown on the relevant
diagram and pins on all package styles number
anti-clockwise when viewed from the top.
FX629J
22-pin cerdip DIL
(J3)
NOT TO SCALE
Max. Body Length 27.38mm
Max. Body Width
9.75mm
Ordering Information
FX629J
22-pin cerdip DIL
(J3)
CML does not assume any responsibility for the use of any circuitry described. No circuit patent licences are implied
and CML reserves the right at any time without notice to change the said circuitry.
10
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