CS5560-ISZ_技术文档

7/31/07

CS5560

±2.5 V / 5 V, 50 kSps, 24-bit, High-throughput ∆Σ ADC

Features & Description

General Description

The CS5560 is a single-channel, 24-bit analog-to-digital

converter capable of 50 kSps conversion rate. The input

accepts a fully differential analog input signal. On-chip

buffers provide high input impedance for both the AIN in-

puts and the VREF+ input. This significantly reduces the

drive requirements of signal sources and reduces errors

due to source impedances. The CS5560 is a delta-sigma

converter capable of switching multiple input channels at

a high rate with no loss in throughput. The ADC uses a

low-latency digital filter architecture. The filter is designed

for fast settling and settles to full accuracy in one conver-

sion. The converter's 24-bit data output is in serial form,

with the serial port acting as either a master or a slave. The

converter is designed to support bipolar, ground-refer-

enced signals when operated from ±2.5V analog supplies.

Differential Analog Input

On-chip Buffers for High Input Impedance

Conversion Time = 20 µS

Settles in One Conversion

Linearity Error = 0.0007%

Signal-to-Noise = 110 dB

24 Bits, No Missing Codes

Self-calibration:

- Maintains accuracy over time & temperature.

Simple three/four-wire serial interface

Power Supply Configurations:

The CS5560 uses self-calibration to achieve low offset and

gain errors. The converter achieves a S/N of 110 dB. Lin-

earity is ±0.0007% of full scale.

- Analog: +5V/GND; IO: +1.8V to +3.3V

- Analog: ±2.5V; IO: +1.8V to +3.3V

Power Consumption:

The converter can operate from an analog supply of 0-5V

or from ±2.5V. The digital interface supports standard log-

ic operating from 1.8, 2.5, or 3.3 V.

- ADC Input Buffers On: 85 mW

- ADC Input Buffers Off: 70 mW

ORDERING INFORMATION:

See Ordering Information on page 32.

V1+

V2+

VL

CS5560

VREF+

VREF-

SMODE

CS

SERIAL

INTERFACE

DIGITAL

FILTER

LOGIC

SCLK

SDI

ADC

AIN+

AI N-

SDO

RDY

SLEEP

BUFEN

RST

CALIBRATION

MICROCONTROLLER

CONV

CAL

OSC/CLOCK

GENERATOR

BP/UP

MCLK

V2-

VLR

V1-

DCR

This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.

Advance Product Information

AUG ‘07

DS713A5

http://www.cirrus.com

7/31/07

CS5560

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

ANALOG CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

SWITCHING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

DIGITAL CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

DIGITAL FILTER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

GUARANTEED LOGIC LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2. OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3. THEORY OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1 Reset and Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1.1 Offset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1.2 Gain Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.2 Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.3 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.4 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.5 Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.6 Output Coding Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.7 Typical Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.8 AIN & VREF Sampling Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.9 Converter Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.10 Digital Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

3.11 Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.11.1 SSC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.11.2 SEC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.12 Power Supplies & Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.13 Using the CS5560 in Multiplexing Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.14 Synchronizing Multiple Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4. PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5. PACKAGE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6. ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION . . . . . . . . . . . . . . 32

REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2

DS713A5

7/31/07

CS5560

LIST OF FIGURES

Figure 1. SSC Mode - Read Timing, CS remaining low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 2. SSC Mode - Read Timing, CS falling after RDY falls . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3. SEC Mode - Read Timing (Not to Scale). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 4. SEC Mode - Calibration Register Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 5. SEC Mode - Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 6. Voltage Reference Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 7. CS5560 Configured Using ±2.5V Analog Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 8. CS5560 Configured Using a Single 5V Analog Supply . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 9. CS5560 DNL Plot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 10. CS5560 Spectral Response (DC to fs/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 11. CS5560 Spectral Response (DC to 5 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 12. CS5560 Spectral Response (DC to 4fs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 13. Simple Multiplexing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 14. More Complex Multiplexing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

LIST OF TABLES

Table 1. Offset & Gain Calibration Register Read/Write Commands . . . . . . . . . . . . . . . . . . . . . . 16

Table 2. Output Coding, Two’s Complement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 3. Output Coding, Offset Binary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

DS713A5

3

7/31/07

CS5560

1. CHARACTERISTICS AND SPECIFICATIONS

•

Min / Max characteristics and specifications are guaranteed over the specified operating conditions.

Typical characteristics and specifications are measured at nominal supply voltages and T = 25°C.

A

VLR = 0 V. All voltages with respect to 0 V.

ANALOG CHARACTERISTICS T = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V,

A

±5%; VL -VLR = 3.3 V, ±5%; VREF = (VREF+) - (VREF-) = 4.096V; MCLK = 16 MHz; SMODE = VL.

BUFEN = V1+ unless otherwise stated. Connected per Figure 7. Bipolar mode unless otherwise stated.

Parameter

Min

Typ

Max

Unit

Accuracy

Linearity Error

(Note 1)

-

0.0003

±0.1

-

%FS

Differential Linearity Error

(Note 2)

LSB

24

Positive Full-scale Error

After Reset

After Calibration (Note 1)

-

1.0

0.01

-

%FS

Negative Full-scale Error

After Reset

After Calibration (Note 1)

-

1.0

0.01

Full-scale Drift

Unipolar Offset

(Note 3)

-

LSB

24

After Reset

After Calibration (Note 1)

-

±2000

±400

-

Unipolar Offset Drift

Bipolar Offset

-

After Reset

After Calibration (Note 1)

-

±1000

±200

-

Bipolar Offset Drift

-

Noise

9.5

µVrms

Dynamic Performance

Peak Harmonic or Spurious Noise

Total Harmonic Distortion

Signal-to-Noise

1 kHz, -0.5 dB Input

-

-110

110

-

dB

S/(N + D) Ratio

-0.5 dB Input, 1 kHz

-60 dB Input, 1 kHz

-

107

48

-

dB

-3 dB Input Bandwidth

(Note 4)

-

42

-

kHz

1. Applies after calibration at any temperature within -40 °C to +85 °C.

2. No missing codes is guaranteed at 24 bits resolution over the specified temperature range.

3. Total drift over specified temperature range after calibration at power-up, at 25º C.

4. Scales with MCLK.

4

DS713A5

7/31/07

CS5560

ANALOG CHARACTERISTICS (CONTINUED) T = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- =

A

V2- = -2.5 V, ±5%; VL -VLR = 3.3 V, ±5%; VREF = (VREF+) - (VREF-) = 4.096V; MCLK = 16 MHz; SMODE = VL.;

BUFEN = V1+ unless otherwise stated. Connected per Figure 7.

Parameter

Min

Typ

Max

Unit

Analog Input

Analog Input Range

Unipolar

Bipolar

0 to +VREF

±VREF

V

Input Capacitance

-

10

-

pF

CVF Current (Note 5)

AIN Buffer On (BUFEN = V+)

AIN Buffer Off (BUFEN = V-)

ACOM

-

600

130

-

nA

µA

Voltage Reference Input

Voltage Reference Input Range

(VREF+) – (VREF-)

4.2

-

(Note 6)

2.4

-

4.096

10

V

Input Capacitance

CVF Current

pF

VREF+ Buffer On (BUFEN = V+)

VREF+ Buffer Off (BUFEN = V-)

VREF-

-

3

1

-

µA

mA

Power Supplies

DC Power Supply Currents

I

-

18

1.8

0.5

mA

V1

V2

VL

Power Consumption

Normal Operation Buffers On

Buffers Off

-

85

70

105

90

mW

Power Supply Rejection

(Note 7) V1+ , V2+ Supplies

V1-, V2- Supplies

90

110

-

dB

5. Measured using an input signal of 1 V DC.

6. For optimum performance, VREF+ should always be less than (V+) - 0.2 volts to prevent saturation of the VREF+ input buffer.

7. Tested with 100 mVP-P on any supply up to 1 kHz. V1+ and V2+ supplies at the same voltage potential, V1- and V2- supplies at

the same voltage potential.

DS713A5

5

7/31/07

CS5560

SWITCHING CHARACTERISTICS

T = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;

A

VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%

Input levels: Logic 0 = 0V; Logic 1 = VD+; CL = 15 pF.

Parameter

Symbol

Min

Typ

Max

Unit

Master Clock Frequency

Internal Oscillator

External Clock

XIN

12

0.5

14

16

16.2

MHz

f

clk

Master Clock Duty Cycle

Reset

40

-

60

%

RST Low Time

t

1

-

µs

res

RST rising to RDY falling

Internal Oscillator

External Clock

t

-

120

1536

-

µs

MCLKs

wup

Calibration

CAL pulse width

(Note 8)

t

4

0

-

MCLKs

ns

pw

CAL high setup time to RST rising

t

ccw

Calibration Time

t

scl

RST rising (CAL high) to RDY falling

-

331458

-

MCLKs

Calibration Time

CAL rising (RST high) to RDY falling

t

cal

Conversion

CONV Pulse Width

t

4

0

-

MCLKs

ns

cpw

BP/UP setup to CONV falling

(Note 9)

t

scn

bus

CONV low to start of conversion

t

-

2

-

MCLKs

Perform Single Conversion (CONV high before RDY falling)

t

20

Conversion Time

(Note 10)

Start of Conversion to RDY falling

t

-

324

MCLKs

buh

Sleep Mode

SLEEP low to low-power state

SLEEP high to device active (Note 11)

t

-

50

3083

-

µs

MCLKs

con

8. CAL can be controlled by the same signal used for RST. If CAL goes high simultaneously with RST, a calibration

will be performed, but CAL must remain high until RDY falls.

9. BP/UP can be changed coincident CONV falling. BP/UP must remain stable until RDY falls.

10. If CONV is held low continuously, conversions occur every 320 MCLK cycles.

If RDY is tied to CONV, conversions will occur every 322 MCLKs.

If CONV is operated asynchronously to MCLK, a conversion may take up to 324 MCLKs.

RDY falls at the end of conversion.

11. RDY will fall when the device is fully operational when coming out of sleep mode.

6

DS713A5

7/31/07

CS5560

SWITCHING CHARACTERISTICS (CONTINUED)

T = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;

A

VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%

Input levels: Logic 0 = 0V; Logic 1 = VD+; CL = 15 pF.

Parameter

Serial Port Timing in SSC Mode (SMODE = VL)

RDY falling to MSB stable

Symbol

Min

Typ

Max

Unit

t

-

-2

-

MCLKs

ns

1

2

Data hold time after SCLK rising

10

Serial Clock (Out)

(Note 12, 13)

Pulse Width (low)

Pulse Width (high)

t

50

-

ns

3

4

RDY rising after last SCLK rising

t

-

8

-

MCLKs

5

12. SDO and SCLK will be high impedance when CS is high. In some systems it may require a pull-down resister.

13. SCLK = MCLK/2.

MCLK

RDY

t₅

t₁

CS

t₃

t₄

t₂

SCLK(o)

LSB

LSB+1

SDO

MSB

MSB–1

Figure 1. SSC Mode - Read Timing, CS remaining low (Not to Scale)

DS713A5

7

7/31/07

CS5560

SWITCHING CHARACTERISTICS (CONTINUED)

T = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;

A

VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%

Input levels: Logic 0 = 0V; Logic 1 = VD+; CL = 15 pF.

Parameter

Serial Port Timing in SSC Mode (SMODE = VL)

Data hold time after SCLK rising

Symbol

Min

Typ

Max

Unit

t

-

10

-

ns

7

Serial Clock (Out)

(Note 14, 15)

Pulse Width (low)

Pulse Width (high)

t

50

-

ns

8

9

RDY rising after last SCLK rising

CS falling to MSB stable

t

-

8

10

8

-

MCLKs

ns

10

t

11

12

13

14

First SCLK rising after CS falling

CS hold time (low) after SCLK rising

SCLK, SDO tristate after CS rising

t

-

MCLKs

ns

10

-

5

ns

14. SDO and SCLK will be high impedance when CS is high. In some systems it may require a pull-down resister.

15. SCLK = MCLK/2.

MCLK

t₁₀

RDY

t₁₃

CS

t₈

t₉

t₁₄

t₁₂

t₇

SCLK(o)

t₁₁

LSB

LSB+1

MSB

MSB–1

SDO

Figure 2. SSC Mode - Read Timing, CS falling after RDY falls (Not to Scale)

8

DS713A5

7/31/07

CS5560

SWITCHING CHARACTERISTICS (CONTINUED)

T = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;

A

VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%

Input levels: Logic 0 = 0V; Logic 1 = VD+; CL = 15 pF.

Parameter

Serial Port Timing in SEC Mode (SMODE = VLR)

SCLK(in) Pulse Width (High)

Symbol

Min

Typ

Max

Unit

-

30

10

-

ns

SCLK(in) Pulse Width (Low)

CS hold time (high) after RDY falling

t

15

16

17

18

19

20

21

CS hold time (high) after SCLK rising

CS low to SDO out of Hi-Z

10

-

10

-

ns

(Note 16)

Data hold time after SCLK rising

Data setup time before SCLK rising

CS hold time (low) after SCLK rising

RDY rising after SCLK falling

-

10

-

10

16. SDO will be high impedance when CS is high. In some systems it may require a pull-down resistor.

MCLK

t₂₁

RDY

CS

t₁₅

t₂₀

t₁₆

SCLK(i)

SDO

t₁₇

t₁₈

t₁₉

MSB

LSB

Figure 3. SEC Mode - Read Timing (Not to Scale)

DS713A5

9

7/31/07

CS5560

SWITCHING CHARACTERISTICS (CONTINUED)

T_A= -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;

VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%

Input levels: Logic 0 = 0V; Logic 1 = VD+; CL = 15 pF.

Parameter

Calibration Register Read Timing

CS hold time (high) after SCLK rising

Symbol

Min

Typ

Max

Unit

t₂₂

t₂₃

t₂₄

t₂₅

t₂₆

t₂₇

t₂₈

10

-

ns

Data setup time before SCLK rising

Data hold time after SCLK rising

SCLK rising to data stable

-

10

-

Data hold time after SCLK rising

SCLK rising to CS rising

-

10

-

SDO tristate after CS rising

5

CS

t₂₂

t₂₇

SCLK(i)

t₂₃

t₂₄

SDI

MSB

LSB

Command Time

8 SCLKs

t₂₈

t₂₅

t₂₆

SDO

MSB

LSB

Data Time

24 SCLKs

Figure 4. SEC Mode - Calibration Register Read Timing (Not to Scale)

10

DS713A5

7/31/07

CS5560

SWITCHING CHARACTERISTICS (CONTINUED)

T_A= -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;

VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%

Input levels: Logic 0 = 0V; Logic 1 = VD+; CL = 15 pF.

Parameter

Calibration Register Write Timing

Data setup time before SCLK rising

Symbol

Min

Typ

Max

Unit

t₂₉

t₃₀

t₃₁

10

-

ns

Data hold time after SCLK rising

SCLK rising to CS rising

17. SDO will be high impedance when CS is high. In some systems it may require a pull-down resister.

CS

t₃₁

SCLK(i)

SDI

t₂₉

t₃₀

LSB

MSB

LSB

MSB

Command Time

8 SCLKs

Data Time

24 SCLKs

Figure 5. SEC Mode - Write Timing (Not to Scale)

DS713A5

11

7/31/07

CS5560

DIGITAL CHARACTERISTICS

T_A= TMIN to TMAX; VL = 3.3V, ±5% or VL = 2.5V, ±5% or 1.8V, ±5%; VLR = 0V

Parameter

Calibration Memory Retention

Symbol

Min

Typ

Max

Unit

(Note 18)

Power Supply Voltage [V1+ = V2+] – [V1- = V2-]

V_MR

I_in

4.0

-

2

-

V

Input Leakage Current

-

µA

pF

Digital Input Pin Capacitance

C_in

3

Digital Output Pin Capacitance

C_out

-

18. VA- and VD- can be any value from 0 to +5V for memory retention. Neither VA- nor VD- should be allowed to go positive. AIN1,

AIN2, or VREF must not be greater than VA+ or VD+. This parameter is guaranteed by characterization.

DIGITAL FILTER CHARACTERISTICS

T_A= TMIN to TMAX; VL = 3.3V, ±5% or VL = 2.5V, ±5% or 1.8V, ±5%; VLR = 0V

Parameter

Symbol

Min

Typ

Max

Unit

Group Delay

-

160

-

MCLKs

12

DS713A5

7/31/07

CS5560

GUARANTEED LOGIC LEVELS

T_A= -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;

VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%

Input levels: Logic 0 = 0V; Logic 1 = VD+; CL = 15 pF.

Guaranteed Limits

Parameter

Sym

V_IH

VL

Min

Typ

Max

Unit

V

Conditions

Logic Inputs

3.3

2.5

1.8

3.3

2.5

1.8

1.9

1.6

1.2

Minimum High-level Input Voltage:

Maximum Low-level Input Voltage:

1.1

0.95

0.6

V_IL

V

Logic Outputs

3.3

2.5

1.8

3.3

2.5

1.8

2.9

2.1

Minimum High-level Output Voltage:

Maximum Low-level Output Voltage:

I_OH= -2 mA

V_OH

V

1.65

0.36

0.44

V_OL

DS713A5

13

7/31/07

CS5560

RECOMMENDED OPERATING CONDITIONS

(VLR = 0V, see Note 19)

Parameter

Symbol

Min

Typ

Max

Unit

Single Analog Supply

DC Power Supplies:

(Note 19)

V1+

V2-

V1+

V2-

4.75

-

5.0

0

5.25

-

V

V2+

V1-

V2-

0

Dual Analog Supplies

DC Power Supplies:

(Note 19)

V1+

V2-

V1+

V2-

+2.375

-2.375

+2.5

-2.5

+2.625

-2.625

V

V2+

V1-

V2-

Analog Reference Voltage

(Note 20)

VREF

2.4

4.096

4.2

V

[VREF+] – [VREF-]

19. The logic supply can be any value VL – VLR = +1.6 to +3.6 volts as long as VLR ≥ V2- and VL ≤ 3.6 V.

20. The differential voltage reference magnitude is constrained by the V1+ or V1- supply magnitude.

ABSOLUTE MAXIMUM RATINGS

(VLR = 0V)

Parameter

Symbol

Min

Typ

Max

Unit

DC Power Supplies:

[V1+] – [V1-] (Note 21)

VL + [ |V1-| ] (Note 22)

-

0

-

5.5

6.3

V

Input Current, Any Pin Except Supplies

Analog Input Voltage

(Note 23)

I_IN

-

±10

(V1+) + 0.3

VL + 0.3

150

mA

V

(AIN and VREF pins)

V_INA

V_IND

T_stg

(V1-) – 0.3

VLR – 0.3

-65

Digital Input Voltage

V

Storage Temperature

°C

Notes: 21. V1+ = V2+; V1- = V2-

22. V1- = V2-

23. Transient currents of up to 100 mA will not cause SCR latch-up.

WARNING: Operation beyond these limits may result in permanent damage to the device.

14

DS713A5

7/31/07

CS5560

2. OVERVIEW

The CS5560 is a 24-bit analog-to-digital converter capable of 50 kSps conversion rate. The device is ca-

pable of switching multiple input channels at a high rate with no loss in throughput. The ADC uses a

low-latency digital filter architecture. The filter is designed for fast settling and settles to full accuracy in

one conversion.

The converter is a serial output device. The serial port can be configured to function as either a master or

a slave.

The CS5560 provides self-calibration circuitry to achieve low offset and gain errors.

The converter can operate from an analog supply of 5V or from ±2.5V. The digital interface supports stan-

dard logic operating from 1.8, 2.5, or 3.3 V.

The CS5560 converts at 50 kSps when operating from a 16 MHz input clock.

3. THEORY OF OPERATION

The CS5560 converter provides high-performance measurement of DC or AC signals. The converter in-

cludes on-chip calibration circuitry to minimize offset and gain errors. The converter can be used to per-

form single conversions or continuous conversions upon command. Each conversion is independent of

previous conversions and can settle to full specified accuracy, even with a full-scale input voltage step.

This is due to the converter architecture which uses a combination of a high-speed delta-sigma modulator

and a low-latency filter architecture.

Once power is established to the converter, a reset must be performed. A reset initializes the internal con-

verter logic and sets the offset register to zero and the gain register to a decimal value of 1.0. If the CAL

pin is low when RST transitions from low to high, no calibration will be performed. If CAL is high when RST

goes high, the converter’s offset & gain slope will be calibrated.

If CONV is held low then the converter will convert continuously with RDY falling every 320 MCLKs. This

is equivalent to 50 kSps if MCLK = 16.0 MHz. If CONV is tied to RDY, a conversion will occur every 322

MCLKs. If CONV is operated asynchronously to MCLK, it may take up to 324 MCLKs from CONV falling

to RDY falling.

Multiple converters can operate synchronously if they are driven by the same MCLK source and CONV

to each converter falls on the same MCLK falling edge. Alternately, CONV can be held low and all devices

are reset with RST rising on the same falling edge of MCLK.

The output coding of the conversion word is a function of the BP/UP pin.

The active-low SLEEP signal causes the device to enter a low-power state. The calibration register con-

tents are preserved during sleep. When exiting sleep, the converter will take 3083 MCLK cycles before

conversions can be performed. RST should remain inactive (high) when SLEEP is asserted (low).

3.1 Reset and Calibration

After the power supplies and the voltage reference are stable, the converter must be reset. The reset func-

tion initializes the internal logic in the converter, but does not initiate calibration. After reset has been per-

formed, the converter can be used uncalibrated, or calibration can be performed. Calibration minimizes

offset and gain errors inside the converter. If the device is used without calibration, conversions will in-

clude the offset and gain errors of the uncalibrated converter, but the converter will maintain its differential

and integral linearity. Calibration of offset and gain can be performed upon command.

DS713A5

15

7/31/07

CS5560

Calibration can be initiated in either of two ways. If CAL is high when RST transitions from low to high, a

calibration cycle will be performed. When calibration is performed, the offset and full-scale points of the

converter are calibrated. A calibration cycle takes 327,680 MCLK cycles. The RDY signal falls upon com-

pletion of reset and calibration sequence. If CAL is held low when RST transitions from low to high, no

calibration will be performed. Calibrations can be initiated any time the converter is idle by taking the CAL

input high. RDY will fall at the end of the calibration cycle. The CAL pin should be returned low when not

being used.

A calibration cycle calibrates the offset and full-scale points of the converter transfer function. When the

offset portion of the calibration is performed, the AIN+ and AIN- pins are disconnected from the input and

shorted internally. The offset of the converter is then measured and a correction factor is stored in the

offset calibration register. Then the voltage reference is internally connected to act as the input signal to

the converter and a gain calibration is performed. The gain correction results are placed in the gain cali-

bration register. The contents of the 24-bit offset and gain registers are used to map the conversion data

prior to its output from the converter. The offset and gain calibration registers can be read and written if

desired. To read or write the calibration registers inside of the converter, the converter must be idle, and

the serial port must be in the SEC mode (SMODE = VLR). Table 1 depicts the commands necessary to

read or write the calibration registers.

Table 1. Offset & Gain Calibration Register Read/Write Commands

Register

Read Command

0x40

Write Command

0xC0

Offset Register

Gain Register

0x20

0XA0

3.1.1 Offset Register

MSB

Sign

0

D22

2^-2

0

D21

D20

0

D19

0

D18

0

D17

D16

0

D15

D14

0

D13

0

D12

2^-12

0

D5

0

D3

0

D11

2^-11

0

D10

D9

0

D8

0

D7

0

D6

0

D4

0

D2

0

D1

0

LSB

2^-24

0

The offset register maps one for one with the conversion word when the gain register is set to 1 decimal.

After reset all bits are zero.

3.1.2 Gain Register

MSB

2²

0

D23

2¹

0

D22

2⁰

1

D21

2^-1

0

D20

2^-2

0

D19

2^-3

0

D18

2^-4

0

D17

2^-5

0

D16

2^-6

0

D15

2^-7

0

D14

2^-8

0

D13

2^-9

0

D12

2^-10

0

D11

2^-11

0

D10

2^-12

0

D9

2^-13

0

D8

2^-14

0

D7

2^-15

0

D6

2^-16

0

D5

2^-17

0

D4

2^-18

0

D3

2^-19

0

D2

2^-20

0

LSB

2^-21

0

The gain register spans from 0 to (8 - 2^-21). After reset, bit D22 is 1, all others are 0. This results in a dec-

imal gain value of 1.000....000.

16

DS713A5

7/31/07

CS5560

The on-chip calibration registers can be read or written via the serial port. Reading or writing into the cal-

ibration registers requires that the serial port be in the SEC mode. To write into the offset or gain register,

the appropriate 8-bit command (see Table 1 on page 16) is first shifted into the SDI pin. Rising edges of

SCLK latch the bits. To perform a write, the 8-bit command is immediately followed by the 24 bit data word

to be written. When a read command is used, the 24 bit data word from the register will be output from

the SDO pin. The data bits will be output on rising edges of SCLK. The data bits have sufficient hold time

to be latched externally by the next rising edge of SCLK.

3.2 Conversion

The CS5560 converts at 50 kSps when synchronously operated (CONV = VLR) from a 16.0 MHz master

clock. Conversion is initiated by taking CONV low. A conversion lasts 320 master clock cycles, but if

CONV is asynchronous to MCLK there may be an uncertainty of 0-4 MCLK cycles after CONV falls to

when a conversion actually begins. This may extend the throughput to 324 MCLKs

When the conversion is completed, the output word is placed into the serial port and RDY goes low. To

convert continuously, CONV should be held low. In continuous conversion mode with CONV held low, a

conversion is performed in 320 MCLK cycles. Alternately RDY can be tied to CONV and a conversion will

occur every 322 MCLK cycles.

To perform only one conversion, CONV should return high at least 20 master clock cycles before RDY

falls.

Once a conversion is completed and RDY falls, RDY will return high when all the bits of the data word are

emptied from the serial port or if the conversion data is not read and CS is held low, RDY will go high two

MCLK cycles before the end of conversion. RDY will fall at the end of the next conversion when new data

is put into the port register.

See Serial Port on page 24 for information about reading conversion data.

Conversion performance can be affected by several factors. These include the choice of clock source for

the chip, the timing of CONV, and the choice of the serial port mode.

The converter can be operated from an internal oscillator. This clock source has greater jitter than an

external crystal-based clock. Jitter may not be an issue when measuring DC signals, or very-low-fre-

quency AC signals, but can become an issue for higher frequency AC signals. For maximum performance

when digitizing AC signals, a low-jitter MCLK should be used.

To maximize performance, the CONV pin should be held low in the continuous conversion state to per-

form multiple conversions, or CONV should occur synchronous to MCLK, falling when MCLK falls.

If the converter is operated at maximum throughput, the SSC serial port mode is less likely to cause in-

terference to measurements as the SCLK output is synchronized to the MCLK. Alternately, any interfer-

ence due to serial port clocking can also be minimized if data is read in the SEC serial port mode when a

conversion is not is progress.

3.3 Clock

The CS5560 can be operated from its internal oscillator or from an external master clock. The state of

MCLK determines which clock source will be used. If MCLK is tied low, the internal oscillator will start and

be used as the clock source for the converter. If an external CMOS-compatible clock is input into MCLK

the converter will power down the internal oscillator and use the external clock. If the MCLK pin is held

high, the internal oscillator will be held in the stopped state. The MCLK input can be held high to delete

clock cycles to aid in operating multiple converters in different phase relationships.

DS713A5

17

7/31/07

CS5560

The internal oscillator can be used if the signals to be measured are essentially DC. The internal oscillator

exhibits jitter at about 500 picoseconds rms. If the CS5560 is used to digitize AC signals, an external

low-jitter clock source should be used.

If the internal oscillator is used as the clock for the CS5560, the maximum conversion rate will be dictated

by the oscillator frequency.

3.4 Voltage Reference

The voltage reference for the CS5560 can range from 2.4 volts to 4.2 volts. A 4.096 volt reference is re-

quired to achieve the specified performance. Figure 7 and Figure 8 illustrate the connection of the voltage

reference with either a single +5 V analog supply or with ±2.5 V.

For optimum performance, the voltage reference device should be one that provides a capacitor connec-

tion to provide a means of noise filtering, or the output should include some type of bandwidth-limiting fil-

ter. Some 4.096 volt reference devices need only 5 volts total supply for operation and can be connected

as shown in Figure 7 or Figure 8. The reference should have a local bypass capacitor and an appropriate

output capacitor.

Some older 4.096 voltage reference designs require more headroom and must operate from an input volt-

age of 5.5 to 6.5 volts. If this type of voltage reference is used ensure that when power is applied to the

system, the voltage reference rise time is slower than the rise time of the V1+ and V1- power supply volt-

age to the converter. An example circuit to slow the output startup time of the reference is illustrated in

Figure 6.

5.5 to 15 V

2k

10µF

VIN

VOUT

GND

4.096 V

Refer to V1- and VREF1 pins.

Figure 6. Voltage Reference Circuit

3.5 Analog Input

The analog input of the converter is fully differential with a peak input of 4.096 volts on each input. This is

illustrated in Figure 7 and Figure 8. These diagrams also illustrate a differential buffer amplifier configura-

tion for driving the CS5560.

The capacitors at the outputs of the amplifiers provide a charge reservoir for the dynamic current from the

A/D inputs while the resistors isolate the dynamic current from the amplifier. The amplifiers can be pow-

ered from higher supplies than those used by the A/D but precautions should be taken to ensure that the

op amp output voltage remains within the power supply limits of the A/D, especially under start-up condi-

tions.

18

DS713A5

7/31/07

CS5560

3.6 Output Coding Format

The reference voltage directly defines the input voltage range in both the unipolar and bipolar configura-

tions. In the unipolar configuration (BP/UP low), the first code transition occurs 0.5 LSB above zero, and

the final code transition occurs 1.5 LSBs below VREF. In the bipolar configuration (BP/UP high), the first

code transition occurs 0.5 LSB above -VREF and the last transition occurs 1.5 LSBs below +VREF. See

Table 2 for the output coding of the converter.

Table 2. Output Coding, Two’s Complement

Two’s

Bipolar Input Voltage

Complement

>(VREF-1.5 LSB)

VREF-1.5 LSB

7F FF FF

7F FF FE

00 00 00

-0.5 LSB

FF FF FF

80 00 01

-VREF+0.5 LSB

80 00 00

<(-VREF+0.5 LSB)

NOTE: VREF = (VREF+) - (VREF-)

Table 3. Output Coding, Offset Binary

Offset

Unipolar Input Voltage

Binary

>(VREF-1.5 LSB)

FF FF FF

VREF-1.5 LSB

FF FF FE

80 00 00

(VREF/2)-0.5 LSB

7F FF FF

00 00 01

+0.5 LSB

00 00 00

<(+0.5 LSB)

NOTE: VREF = (VREF+) - (VREF-)

DS713A5

19

7/31/07

CS5560

3.7 Typical Connection Diagrams

The following figure depicts the CS5560 powered from bipolar analog supplies, +2.5 V and - 2.5 V.

4700pF

C0G

R₁

49.9

CS5560

C₁

AIN+

60pF

+2.048 V

0 V

-2.048 V

4.99k

SMODE

CS

⁴SCLK

4.99k

49.9

+2.048 V

0 V

-2.048 V

R₁

C₁

AIN-

60pF

4.99k

⁴SDO

RDY

4700pF

C0G

4.99k

(V+) Buffers On

CONV

CAL

BUFEN

VREF+

+2.5 V

BP/UP

SLEEP

(V-) Buffers Off

+4.096

RST

Voltage

Reference

(NOTE 1)

10 µF

0.1 µF

MCLK

TST

VREF-

-2.5 V

+3.3 V to +1.8 V

+2.5 V

V1+

V2+

V2-

VL

10

0.1 µF

10

0.1 µF

X7R

DCR

V1-

VLR

-2.5 V

NOTES

1. See Section 3.4 Voltage Reference for information on required

voltage reference performance criteria.

2.Locate capacitors so as to minimize loop length.

3. The ±2.5 V supplies should also be bypassed to ground at the converter.

4. VLR and the power supply ground for the ±2.5 V should be

connected to the same ground plane under the chip.

5. SCLK and SDO may require pull-down resistors in some applications.

6. An RC input filter can be used to band limit the input to reduce noise.

Select R to be equal to the parallel combination of the feedback of the

feedback resistors 4.99k || 4.99k = 2.5k⎠ ⎠

Figure 7. CS5560 Configured Using ±2.5V Analog Supplies

20

DS713A5

7/31/07

CS5560

The following figure depicts the CS5560 device powered from a single 5V analog supply.

4700pF

C0G

49.9

2.048 V

AIN+

CS5560

47pF

4.99k

4.548 V

2.5 V

-0.452 V

SMODE

CS

+4.548 V

2.5 V

-0.452 V

³SCLK

49.9

AIN-

4.096 V

47pF

4.99k

4700pF

C0G

³SDO

RDY

(V+) Buffers On

(V-) Buffers Off

CONV

CAL

BUFEN

VREF+

+5 V

BP/UP

SLEEP

RST

+4.096

Voltage

Reference

(NOTE 1)

10 µF

0.1 µF

MCLK

TST

VREF-

+3.3 V to 1.8 V

+5 V

V1+

VL

10

0.1 µF

V2+

V2-

0.1 µF

X7R

DCR

V1-

VLR

NOTES

1. See Section 3.4 Voltage Reference for information on

required voltage reference performance criteria.

2. Locate capacitors so as to minimize loop length.

3. V1-, V2-, and VLR should be connected to the same

ground plane under the chip.

4. SCLK and SDO may require pull-down resistors in

some applications.

Figure 8. CS5560 Configured Using a Single 5V Analog Supply

DS713A5

21

7/31/07

CS5560

3.8 AIN & VREF Sampling Structures

The CS5560 uses on-chip buffers on the AIN+, AIN-, and the VREF+ inputs. Buffers provide much higher

input impedance and therefore reduce the amount of drive current required from an external source. This

helps minimize errors.

The Buffer Enable (BUFEN) pin determines if the on-chip buffers are used or not. If the BUFEN pin is

connected to the V1+ supply the buffers will be enabled. If the BUFEN pin is connected to the V1- pin

the buffers are off. The converter will consume about 30 mW less power when the buffers are off, but the

input impedances of AIN+, AIN- and VREF+ will be significantly less than with the buffers enabled.

3.9 Converter Performance

The CS5560 achieves excellent differential nonlinearity (DNL) as shown in Figure 9. Figure 9 illustrates

the code widths on the typical scale of ±1 LSB and on a zoomed scale of ±0.2 LSB.

(Zoom View)

Figure 9. CS5560 DNL Plot

22

DS713A5

7/31/07

CS5560

3.10 Digital Filter Characteristics

The digital filter is designed for fast settling, therefore it exhibits very little in-band attenuation. The filter

attenuation is 1.040 dB at 25 kHz when sampling at 50 kSps.

0.0

-0.0414 dB

fs = 50 kSps

-0.2

-0.4

-0.6

-0.8

-1.0

-1.2

-0.166 dB

-0.3725 dB

-0.664 dB

-1.040 dB

0

5k

10k

15k

20k

25k

Frequency (Hz)

Figure 10. CS5560 Spectral Response (DC to fs/2)

-0.001646 dB

fs = 50 kSps

-0.00663 dB

-0.0149 dB

-0.0262 dB

-0.0414 dB

Frequency (Hz)

Figure 11. CS5560 Spectral Response (DC to 5 kHz)

fs = 50 kSps

Figure 12. CS5560 Spectral Response (DC to 4fs)

DS713A5

23

7/31/07

CS5560

3.11 Serial Port

The serial port on the CS5560 can operate in two different modes: synchronous self clock (SSC) mode &

synchronous external clock (SEC) mode. The serial port must be placed into the SEC mode if the offset

and gain registers of the converter are to be read or written. The converter must be idle when reading or

writing to the on-chip registers.

3.11.1 SSC Mode

If the SMODE pin is high (SMODE = VL), the serial port operates in the SSC (Synchronous Self Clock)

mode. In the SSC mode the port shifts out conversion data words with SCLK as an output. SCLK is gen-

erated inside the converter from MCLK. Data is output from the SDO (Serial Data Output) pin. If CS is

high, the SDO and SCLK pins will stay in a high-impedance state. If CS is low when RDY falls, the con-

version data word will be output from SDO MSB first. Data is output on the rising edge of SCLK and should

be latched into the external logic on the subsequent rising edge of SCLK. When all bits of the conversion

word are output from the port the RDY signal will return to high.

3.11.2 SEC Mode

If the SMODE pin is low (SMODE = VLR), the serial port operates in the SEC (Synchronous External

Clock mode). In this mode, the user usually monitors RDY. When RDY falls at the end of a conversion,

the conversion data word is placed into the output data register in the serial port. CS is then activated low

to enable data output. Note that CS can be held low continuously if it is not necessary to have the SDO

output operate in the high impedance state. When CS is taken low (after RDY falls) the conversion data

word is then shifted out of the SDO pin by driving the SCLK pin from system logic external to the converter.

The SDI input must be held low when reading conversion word data. Data bits are advanced on rising

edges of SCLK and latched by the subsequent rising edge of SCLK.

If CS is held low continuously, the RDY signal will fall at the end of a conversion and the conversion data

will be placed into the serial port. If the user starts a read, the user will maintain control over the serial port

until the port is empty. However, if SCLK is not toggled, the converter will overwrite the conversion data

at the completion of the next conversion. If CS is held low and no read is performed, RDY will rise just

prior to the end of the next conversion and then fall to signal that new data has been written into the serial

port.

24

DS713A5

7/31/07

CS5560

3.12 Power Supplies & Grounding

The CS5560 can be configured to operate with its analog supply operating from 5V, or with its analog sup-

plies operating from ±2.5V. The digital interface supports digital logic operating from either 1.8V, 2.5V, or

3.3V.

Figure 7 on page 20 illustrates the device configured to operate from ±2.5V analog. Figure 8 on page 21

illustrates the device configured to operate from 5V analog.

To maximize converter performance, the analog ground and the logic ground for the converter should be

connected at the converter. In the dual analog supply configuration, the analog ground for the ±2.5V sup-

plies should be connected to the VLR pin at the converter with the converter placed entirely over the an-

alog ground plane.

In the single analog supply configuration (+5V), the ground for the +5V supply should be directly tied to

the VLR pin of the converter with the converter placed entirely over the analog ground plane. Refer to

Figure 8 on page 21.

DS713A5

25

7/31/07

CS5560

3.13 Using the CS5560 in Multiplexing Applications

The CS5560 is a delta-sigma A/D converter. Delta-sigma converters use oversampling as means to

achieve high signal to noise. This means that once a conversion is started the converter takes many sam-

ples to compute the resulting output word. The analog input for the signal to be converted must remain

active during the entire conversion until RDY falls.

The CS5560 can be used in multiplexing applications, but the system timing for changing the multiplexer

channel and for starting a new conversion will depend upon the multiplexer system architecture.

The simplest system is illustrated in Figure 13. Any time the multiplexer is changed, the analog signal

presented to the converter must fully settle. After the signal has settled, the CONV signal is issued to the

converter to start a conversion. Being a delta-sigma converter, the signal must remain present at the input

of the converter until the conversion is completed. Once the conversion is completed, RDY falls. At this

time the multiplexer can be changed to the next channel and the data can be read from the serial port.

The CONV signal should be delayed until after the data is read and until the new analog signal has settled.

In this configuration, the throughput of the converter will be dictated by the settling time of the analog input

circuit and the conversion time of the converter. The conversion data can be read from the serial port after

the multiplexer is changed to the new channel while the analog input signal is settling.

CS556x

4700pF

C0G

CH1+

49.9

AIN+

AIN-

CH2+

CH3+

CH4+

60pF

4.99k

CH1-

CH2-

CH3-

CH4-

49.9

60pF

4.99k

4700pF

C0G

Amplifier

Settling Time

Amplifier

Settling Time

Conversion Time

CONV

RDY

CH1

CH2

Advance

Mux

Throughput

Figure 13. Simple Multiplexing Scheme

A more complex multiplexing scheme can be used to increase the throughput of the converter is illustrated

in Figure 14. In this circuit, two banks of multiplexers are used.

26

DS713A5

7/31/07

CS5560

At the same time the converter is performing a conversion on a channel from one bank of multiplexers,

the second multiplexer bank is used to select the channel for the next conversion. This configuration al-

lows the buffer amplifier for the second multiplexer bank to fully settle while a conversion is being per-

formed on the channel from the first multiplexer bank. The multiplexer on the output of the buffer amplifier

and the CONV signal can be changed at the same time in this configuration. This multiplexing architec-

ture allows for maximum multiplexing throughput from the A/D converter.The following figure depicts the

recommended analog input amplifier circuit.

CH1

4700pF

C0G

B1+

B2+

49.9

60pF

SW2

4.99k

B1-

CS556x

B2-

49.9

CH2

CH3

60pF

4.99k

A1+

A2+

4700pF

C0G

AIN+

4700pF

C0G

C1+

C2+

SW1

49.9

A1-

A2-

60pF

SW3

4.99k

C1-

C2-

AIN-

49.9

CH4

60pF

4.99k

4700pF

C0G

CONV

SW1

Select A1

Select A2

Select A1

Select C2

Select A2

Select A1

SW2

SW3

Select B1

Select C1

Select B2

Select B1

Select C1

Convert on CH1

Convert on CH3

Convert on CH2

Convert on CH4

Convert on CH1

Figure 14. More Complex Multiplexing Scheme

3.14 Synchronizing Multiple Converters

Many measurement systems have multiple converters that need to operate synchronously. The convert-

ers should all be driven from the same master clock. In this configuration, the converters will convert syn-

chronously if the same CONV signal is used to drive all the converters, and CONV falls on a falling edge

of MCLK. If CONV is held low continuously, reset (RST) can be used to synchronize multiple converters

if RST is released on a falling edge of MCLK.

DS713A5

27

7/31/07

CS5560

4. PIN DESCRIPTIONS

Chip Select

Serial Data Input

Serial Mode Select SMODE

CS

SDI

1

2

3

4

24

23

22

21

20

19

18

17

16

15

14

13

RDY

Ready

SCLK Serial Clock Input/Output

SDO

VL

Serial Data Output

Logic Interface Power

Logic Interface Return

Differential Analog Input

Negative Power 1

Positive Power 1

Buffer Enable BUFEN

Voltage Reference Input

Bipolar/Unipolar Select

Sleep Mode Select

AIN+

AIN-

V1-

5

6

7

8

VLR

MCLK Master Clock

V2-

V2+

DCR

CONV Convert

V1+

Negative Voltage 2

Positive Voltage 2

Digital Core Regulator

VREF+

VREF-

BP/UP

SLEEP

9

10

11

12

CAL

RST

Calibrate

Reset

CS – Chip Select, Pin 1

The Chip Select pin allows an external device to access the serial port. If SMODE = VL (SSC

Mode) and CS is held high, the SDO output and the SCLK output will be held in a

high-impedance output state.

SDI – Serial Data Input, Pin 2

SDI is the input pin for reading and writing calibration registers via the serial port. SDI is only

accessible when SMODE is set to enable the SEC serial mode. Data is shifted into this pin by

SCLK. SDI should be held low when the serial port is in SSC mode.

SMODE – Serial Mode Select, Pin 3

The serial interface mode pin (SMODE) dictates whether the serial port behaves as a master or

slave interface.If SMODE is tied high (to VL), the port will operate in the Synchronous

Self-Clocking (SSC) mode. In SSC mode the port acts as a master in which the converter out-

puts both the SDO and SCLK signals. If SMODE is tied low (to VLR) the port will operate in the

Synchronous External Clocking (SEC) mode. In SEC mode, the port acts as a slave in which

the external logic or microcontroller generates the SCLK used to output the conversion data

word from the SDO pin.

AIN+, AIN- – Differential Analog Input, Pin 4, 5

AIN+ and AIN- are differential inputs for the converter.

V1- – Negative Power 1, Pin 6

The V1- and V2- pins provide a negative supply voltage to the core circuitry of the chip. These

two pins should be decoupled as shown in the application block diagrams. V1- and V2- should

be supplied from the same source voltage. For single supply operation these two voltages are

nominally 0 V (Ground). For dual supply operation they are nominally -2.5 V.

V1+ – Positive Power 1, Pin 7

The V1+ and V2+ pins provide a positive supply voltage to the core circuitry of the chip. These

two pins should be decoupled as shown in the application block diagrams. V1+ and V2+ should

be supplied from the same source voltage. For single supply operation these two voltages are

nominally +5 V. For dual supply operation they are nominally +2.5 V.

BUFEN – Buffer Enable, Pin 8

Buffers on input pins AIN+ and AIN- are enabled if BUFEN is connected to V1+ and disabled if

connected to V1-.

28

DS713A5

7/31/07

CS5560

VREF+, VREF- – Voltage Reference Input, Pin 9, 10

A differential voltage reference input on these pins functions as the voltage reference for the

converter. The voltage between these pins can range between 2.4 volts and 4.2 volts, with

4.096 volts being the nominal reference voltage value.

BP/UP – Bipolar/Unipolar Select, Pin 11

The BP/UP pin determines the span and the output coding of the converter. When set high to

select BP (bipolar), the input span of the converter is -4.096 volts to +4.096 volts fully differential

(assuming the voltage reference is 4.096 volts) and outputs data is coded in two's complement

format. When set low to select UP (unipolar), the input span is 0 to +4.096 fully differential and

the output data is coded in binary format.

SLEEP – Sleep Mode Select, Pin 12

When taken low, the SLEEP pin will cause the converter to enter into a low-power state. SLEEP

will stop the internal oscillator and power down all internal analog circuitry.

RST – Reset, Pin 13

Reset is necessary after power is initially applied to the converter. When the RST input is taken

low, the logic in the converter will be reset. When RST is released to go high, certain portions of

the analog circuitry are started. RDY falls when reset is complete.

CAL – Calibrate, Pin 14

After power is applied, a reset should be performed prior to calibration. After an initial reset, cal-

ibration can be performed at any time. Calibration can be initiated in either of two ways. If CAL

is high when coming out of reset, (RST going high), a calibration will be performed. If RST is

taken high with CAL low, a calibration is not performed, but calibration can be initiated by taking

CAL high at any time the converter is idle. RDY will also fall when calibration is completed.

CONV – Convert, Pin 15

The CONV pin initiates a conversion cycle if taken low, unless a calibration cycle or a previous

conversion is in progress. When the conversion cycle is completed, the conversion word is out-

put to the serial port register and the RDY signal goes low. If CONV is held low and remains low

when RDY falls another conversion cycle will be started.

DCR – Digital Core Regulator, Pin 16

DCR is the output of the on-chip regulator for the digital logic core. DCR should be bypassed

with a capacitor to V2-. The DCR pin is not designed to power any external load.

V2+ – Positive Power 2, Pin 17

The V1+ and V2+ pins provide a positive supply voltage to the circuitry of the chip. These two

pins should be decoupled as shown in the application block diagrams. V1+ and V2+ should be

supplied from the same source voltage. For single supply operation these two voltages are

nominally +5 V. For dual supply operation they are nominally +2.5 V.

V2- – Negative Power 2, Pin 18

The V1- and V2- pins provide a negative supply voltage to the circuitry of the chip. These two

pins should be decoupled as shown in the application block diagrams. V1- and V2- should be

supplied from the same source voltage. For single supply operation these two voltages are

nominally 0 V (Ground). For dual supply operation they are nominally -2.5 V.

MCLK – Master Clock, Pin 19

The master clock pin (MCLK) is a multi-function pin. If tied low (MCLK = VLR) the on-chip oscil-

lator will be enabled. If tied high (MCLK = VL), all clocks to the internal circuitry of the converter

will stop. When MCLK is held high the internal oscillator will also be stopped. MCLK can also

function as the input for an external CMOS-compatible clock that conforms to supply voltages

on the VL and VLR pins.

DS713A5

29

7/31/07

CS5560

VLR, VL – Logic Interface Power/Return, Pin 20, 21

VL and VLR are the supply voltages for the digital logic interface. VL and VLR can be config-

ured with a wide range of common mode voltage. The following interface pins function from the

VL/VLR supply: SMODE, CS, SCLK, SDI, SDO, RDY, SLEEP, CONV, RST, CONV, CAL,

BP/UP, and MCLK.

SDO – Serial Data Output, Pin 22

SDO is the output pin for the serial output port. Data from this pin will be output at a rate deter-

mined by SCLK and in a format determined by the BP/UP pin. Data is output MSB first and

advances to the next data bit on the rising edges of SCLK. SDO will be in a high impedance

state when CS is high.

SCLK – Serial Clock Input/Output, Pin 23

The SMODE pin determines whether the SCLK signal is an input or an output signal. SCLK

determines the rate at which data is clocked out of the SDO pin. If the converter is in SSC

mode, the SCLK frequency will be determined by the master clock frequency of the converter

(either MCLK or the internal oscillator). In SEC mode, the user determines the SCLK frequency.

If SMODE = VL (SSC Mode), SCLK will be in a high-impedance state when CS is high.

RDY – Ready, Pin 24

The RDY signal rises when a calibration is initiated. When the calibration is near completion the

state of CONV is examined. If CONV is high, the RDY signal will fall upon the completion of cal-

ibration. If CONV is low the converter will immediately start a conversion and RDY will remain

high until the conversion is completed. At the end of any conversion RDY falls to indicate that a

conversion word has been placed into the serial port. RDY will return high after all data bits are

shifted out of the serial port or two master clock cycles before new data becomes available if the

CS pin is inactive (high); or two master clock cycles before new data becomes available if the

user holds CS low but has not started reading the data from the converter when in SEC mode.

30

DS713A5

7/31/07

CS5560

5. PACKAGE DIMENSIONS

24L SSOP PACKAGE DRAWING

N

D

E1¹

A2

A

E

∝

A1

b²

e

L

END VIEW

SEATING

PLANE

SIDE VIEW

1

2 3

TOP VIEW

INCHES

NOM

--

0.006

0.068

--

0.323

0.307

0.209

0.026

0.03

4°

MILLIMETERS

NOTE

DIM

A

A1

A2

b

D

E

E1

e

L

MIN

--

MAX

0.084

0.010

0.074

0.015

0.335

0.323

0.220

0.030

0.041

8°

MIN

--

NOM

--

0.13

1.73

--

8.20

7.80

5.30

0.65

0.75

4°

MAX

2.13

0.25

1.88

0.38

8.50

8.20

5.60

0.75

1.03

8°

0.002

0.064

0.009

0.311

0.291

0.197

0.022

0.025

0°

0.05

1.62

0.22

7.90

7.40

5.00

0.55

0.63

0°

2,3

1

∝

JEDEC #: MO-150

Controlling Dimension is Millimeters.

Notes: 1.“D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured

at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side.

2.Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b”

dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least

material condition.

3.These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.

DS713A5

31

7/31/07

CS5560

6. ORDERING INFORMATION

Model

CS5560-ISZ

Linearity

Temperature

-40 to +85 °C

Conversion Time

Throughput

Package

0.0007%

20 µs

50 kSps

24-pin SSOP

7. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION

Model Number

CS5560-ISZ

Peak Reflow Temp

MSL Rating*

Max Floor Life

7 Days

260 °C

3

* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.

8. REVISION HISTORY

Revision

A1

Date

Changes

MAY 2007

JUN 2007

AUG 2007

Advance release.

A2

Updated serial interface timing parameters.

Added DNL plot.

A3

A4

Updated Typical Connection diagram.

Corrected liearity spec. in Ordering Information section.

A5

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative.

To find the one nearest to you go to www.cirrus.com

IMPORTANT NOTICE

"Advance" product information describes products that are in development and subject to development changes.

Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject

to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant

information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale

supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus

for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third

parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,

copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con-

sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent

does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP-

ERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE

IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE-

VICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD

TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE

IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN

SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS,

CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS

FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.

Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks

or service marks of their respective owners.

32

DS713A5


型号：	CS5560-ISZ
厂家：	CIRRUS LOGIC
描述：	【2.5 V / 5 V, 50 kSps, 24-bit, High-throughput ツヒ ADC 【 2.5 V / 5 V ， 50 kSPS时， 24位，高通量ツヒADC 转换器模数转换器光电二极管
文件：	总32页 (文件大小：559K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CS5560-ISZ [CIRRUS]

相关型号：

CS5560_08

CS5560_09

CS5566

CS5566-ISZ

CS5566_09

CS5571

CS5571-ISZ

CS5571_08

CS5581

CS5581-ISZ

CS5581_08

CS55AZ