CS5339-KS [CIRRUS]
16-Bit, Stereo A/D Converters for Digital Audio; 16位数字音频立体声A / D转换器
| 型号： | CS5339-KS |
| 厂家： | 
CIRRUS LOGIC |
| 描述： | 16-Bit, Stereo A/D Converters for Digital Audio |
| 文件： | 总34页 (文件大小：681K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CS5336 CS5338 CS5339
16-Bit, Stereo A/D Converters for Digital Audio
Semiconductor Corporation
Features
General Description
The CS5336, CS5338 & CS5339 are complete analog-
to-digital converters for stereo digital audio systems.
They perform sampling, analog-to-digital conversion and
anti-aliasing filtering, generating 16-bit values for both
left and right inputs in serial form. The output word rate
can be up to 50 kHz per channel.
Complete CMOS Stereo A/D System
Delta-Sigma A/D Converters
•
Digital Anti-Alias Filtering
S/H Circuitry and Voltage Reference
Adjustable System Sampling Rates
including 32kHz, 44.1 kHz & 48kHz
•
•
The ADCs use delta-sigma modulation with 64X over-
sampling, followed by digital filtering and decimation,
which removes the need for an external anti-alias filter.
Low Noise and Distortion
>90 dB S/(N+D)
The CS5336 & CS5338 have an SCLK which clocks out
data on rising edges. The CS5339 has an SCLK which
clocks out data on falling edges.
Internal 64X Oversampling
•
•
The CS5336 has a filter passband of dc to 22kHz. The
CS5338 & CS5339 have a filter passband of dc to 24
kHz. The filters have linear phase, 0.01 dB passband
ripple, and >80 dB stopband rejection.
Linear Phase Digital Anti-Alias Filtering
0.01dB Passband Ripple
80dB Stopband Rejection
The ADC’s are housed in a 0.6" wide 28-pin plastic DIP,
and also in a 0.3" wide 28-pin SOIC surface mount
package. Extended temperature range versions of the
CS5336 are also available.
Low Power Dissipation: 400 mW
Power-Down Mode for Portable
Applications
•
•
Evaluation Board Available
ORDERING INFORMATION:
See Page 3-59
S C LK
15
L/R
14
IC LK A
23
APD
6
A C A L
7
O C LK D IC LKD
21 20
F SYN C
17
16
28
SD ATA
VREF
Voltage Reference
12
13
Serial O utput Interface
CM O D E
SM O D E
2
3
A IN L
LP Filter
ZER O L
Digital Decim ation
Filter
S/H
Com parator
11
D AC
T S T
27
26
AIN R
Digital Decim ation
Filter
LP Filter
Z ER O R
8
S/H
N C
N C
Com parator
1
Calibration
Microcontroller
Calibration
S R A M
A GN D
22
D AC
4
5
25
VL+
24
LG N D
9
10
18
V D +
19
VA+
VA-
D C A L D P D
D GN D
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581
AUG ’93
DS23F1
3-39
CS5336, CS5338, CS5339
ANALOG CHARACTERISTICS (Logic 0 = GND; Logic 1 = VD+; K grade: T = 25°C; B and T
A
grades: T = T
to T
; VA+, VL+,VD+ = 5V; VA- = -5V; Full-Scale Input Sinewave, 1kHz; Output word
MAX
A
MIN
rate = 48 kHz; SCLK = 3.072 MHz; Source Impedance = 50Ω with 10 nF to AGND; Measurement Bandwidth is
10 Hz to 20 kHz; unless otherwise specified.)
CS5336,8,9-K
CS5336-B
CS5336-T
Parameter
Symbol Min Typ Max Min Typ Max Min Typ Max Units
Specified Temperature Range
Resolution
T
A
0
to
-
70 -40 to +85 -55 to +125 °C
16
-
16
-
-
16
-
-
Bits
Dynamic Performance
Dynamic Range
92.7 95.7
S/(N+D) 90.7 92.7
96
THD .0025 .001
.0001
100 106
-
-
-
-
-
-
90 93.5
85 89
-
-
-
-
-
-
84 92
82 86
-
-
-
-
-
-
dB
dB
dB
%
Signal-to-(Noise + Distortion); THD+N
Signal to Peak Noise
-
-
95
.005 .001
.0001
90 106
-
94
.013 .005
.0001
83 96
Total Harmonic Distortion
Interchannel Phase Deviation
-
-
-
°
Interchannel Isolation
dc Accuracy
(dc to 20 kHz)
dB
Interchannel Gain Mismatch
-
-
-
-
-
0.01 0.05
-
-
-
-
-
.01 .05
-
-
-
-
-
.01 0.1
dB
%
Gain Error
Gain Drift
(includes Vref tolerance)
(includes Vref drift, Note 1)
±1 ±5
±2 ±5
±3 ±6
25
-
70
-
70
-
ppm/°C
Bipolar Offset Error
(Note 2)
(Note1)
±5 ±15
±10 ±30
±16 ±65 LSB
Offset Drift
15
-
20
-
20
-
ppm/°C
Analog Input
Input Voltage Range
Input Impedance
Power Supplies
(±Full Scale)
VIN
ZIN
±3.5 ±3.68
-
-
±-3.5±3.68
-
-
±3.5 ±3.68
-
-
V
-
65
-
65
-
65
kΩ
Power Supply Current
with APD, DPD low
(Normal Operation)
(VA+)+(VL+)
VA-
IA+
IA-
ID+
-
-
-
25 35
-25 -35
30 45
-
-
-
25 35
-25 -35
30 45
-
-
-
25 35
-25 -35
30 50
mA
mA
mA
VD+
Power Supply Current
with APD, DPD high
(Power-Down Mode)
(VA+)+(VL+)
VA-
IA+
IA-
ID+
-
-
-
10 50
-10 -50
10 400
-
-
-
10 50
-10 -50
10 400
-
-
-
10 50
-10 -50
10 400
µA
µA
µA
VD+
Power Consumption
(APD, DPD Low) PDN
(APD, DPD High) PDS
-
-
400 575
0.15 2.5
-
-
400 575
0.15 2.5
-
-
400 600 mW
0.15 2.5 mW
Power Supply
Rejection Ratio
(dc to 26 kHz)
PSRR
-
-
54
100
-
-
-
-
54
100
-
-
-
-
54
100
-
-
dB
dB
(26 kHz to 3.046 MHz)
Notes: 1. This parameter is guaranteed by design and/or characterization.
2. After calibration with DCAL connected to ACAL, and ZEROL & ZEROR terminated to AGND with an
impedance matched to the AINR & AINL source impedance. Executing a calibration with ACAL tied
low (See Power Down and Offset Calibration section) will yield an offset error of typically less than
± 5LSB.
Specifications are subject to change without notice.
3-40
DS23F1
CS5336, CS5338, CS5339
DIGITAL FILTER CHARACTERISTICS
(T = 25 ° C; VA+, VL+ ,VD+ = 5V ± 5%; VA- = -5V ± 5%; Output word rate of 48 kHz)
A
Units
Parameter
Symbol
Min
Max
Typ
Passband
(-3 dB) CS5336
(-3 dB) CS5338, CS5339
0
0
kHz
kHz
22
24
to
to
(-0.01 dB)
(-0.01 dB)
CS5336
CS5338, CS5339
0
0
kHz
kHz
20
22
to
to
Passband Ripple
Stopband
_+
-
-
dB
0.01
CS5336
CS5338, CS5339
26
28
3046
3044
kHz
kHz
to
to
(Note 3)
Stopband Attenuation
80
-
-
-
dB
s
Group Delay (OWR = Output Word Rate)
Group Delay Variation vs. Frequency
t
18/OWR
-
-
gd
t
0.0
us
-
gd
Notes: 3. The analog modulator samples the input at 3.072MHz for an output word rate of 48 kHz. There is
no rejection of input signals which are multiples of the sampling frequency (that is: there is
no rejection for n x 3.072MHz ±22kHz for the CS5338 & CS5339, or n x 3.072MHz ±20.0kHz for the
CS5336, where n = 0,1,2,3...).
DIGITAL CHARACTERISTICS
(T = 25 °C; VA+, VL+ ,VD+ = 5V ± 5%; VA- = -5V ± 5%)
A
Parameter
Symbol
Min
Typ
Max
Units
V
70%VD+
High-Level Input Voltage
IH
-
-
V
V
V
V
30% VD+
Low-Level Input Voltage
IL
-
-
-
V
V
High-Level Output Voltage at Io = -20uA
Low-Level Output Voltage at Io = 20uA
OH
4.4
-
OL
-
-
-
0.1
-
V
Iin
uA
Input Leakage Current
1.0
ABSOLUTE MAXIMUM RATINGS (AGND, LGND, DGND = 0V, all voltages with respect to GND)
Min
-0.3
+0.3
-0.3
-0.3
Max
Units
Parameter
Symbol
+6.0
V
V
V
V
Positive Analog
Negative Analog
VA+
VA-
DC Power Supplies:
-6.0
(VA+) + 0.3
Positive Logic
Positive Digital
VL+
VD+
+6.0
_+
-
mA
V
I in
10
Input Current, Any Pin Except Supplies
Analog Input Voltage (AIN and ZERO pins)
Digital Input Voltage
(VA- )- 0.3
(VA+ )+ 0.3
(VD+) + 0.3
+125
VINA
VIND
V
-0.3
-55
-65
C
Ambient Temperature (power applied)
Storage Temperature
T
A
+150
C
T
stg
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
DS23F1
3-41
CS5336, CS5338, CS5339
SWITCHING CHARACTERISTICS
(T = 25 °C; VA+, VL+, VD+ = 5V ± 5%; VA- = -5V ± 5%; Inputs: Logic 0 = 0V, Logic 1 = VD+; C = 20 pF)
A
L
Parameter
Symbol
Min
Typ
Max
Unit
ICLKD Period (CMODE low)
ICLKD Low (CMODE low)
(Note 6)
t
78
-
3906
-
ns
ns
clkw1
t
31
-
clkl1
ICLKD High (CMODE low)
t
31
-
-
ns
clkh1
ICLKD rising to OCLKD rising (CMODE low)
ICLKD Period (CMODE high)
ICLKD Low (CMODE high)
t
5
-
40
2604
-
ns
ns
ns
io1
t
52
-
clkw2
t
20
-
clkl2
ICLKD High (CMODE high)
t
20
-
-
ns
clkh2
ICLKD rising or falling to OCLKD rising (CMODE high, Note 4)
ICLKD rising to L/R edge (CMODE low, MASTER mode)
ICLKD rising to FSYNC edge (CMODE low, MASTER mode)
ICLKD rising to SCLK edge (CMODE low, MASTER mode)
ICLKD falling to L/R edge (CMODE high, MASTER mode)
ICLKD falling to FSYNC edge (CMODE high, MASTER mode)
ICLKD falling to SCLK edge (CMODE high, MASTER mode)
SCLK rising to SDATA valid (MASTER mode, Note 5)
SCLK duty cycle (MASTER mode)
t
5
-
45
50
50
50
50
50
50
50
60
20
20
-
ns
ns
ns
io2
t
5
-
ilr1
t
5
-
ifs1
t
5
-
ns
isclk1
t
5
-
ns
ns
ilr2
t
5
-
ifs2
t
5
-
ns
isclk2
t
0
-
ns
%
sdo
40
50
SCLK rising to L/R (MASTER mode, Note 5)
t
-20
-
ns
mslr
SCLK rising to FSYNC (MASTER mode, Note 5)
SCLK Period (SLAVE mode)
t
-20
-
ns
ns
msfs
t
155
-
sclkw
SCLK Pulse Width Low (SLAVE mode)
t
60
-
-
ns
sclkl
SCLK Pulse Width High (SLAVE mode)
t
60
-
-
ns
sclkh
SCLK rising to SDATA valid (SLAVE mode, Note 5)
L/R edge to MSB valid (SLAVE mode)
t
-
-
50
50
-
ns
dss
t
-
-
ns
ns
lrdss
Falling SCLK to L/R edge delay (SLAVE mode, Note 5)
L/R edge to falling SCLK setup time (SLAVE mode, Note 5)
Falling SCLK to rising FSYNC delay (SLAVE mode, Note 5)
Rising FSYNC to falling SCLK setup time (SLAVE mode, Note 5)
DPD pulse width
t
30
-
slr1
t
30
-
-
ns
slr2
t
30
-
-
ns
ns
ns
ns
1/OWR
sfs1
t
30
-
-
sfs2
t
2 x tclkw
-
-
-
pdw
DPD rising to DCAL rising
t
-
-
50
-
pcr
DPD falling to DCAL falling (OWR = Output Word Rate)
t
4096
pcf
Notes: 4. ICLKD rising or falling depends on DPD to L/R timing (see Figure 2).
5. SCLK is shown for CS5336, CS5338. SCLK is inverted for CS5339.
6. Specifies minimum output word rate (OWR) of 1 kHz.
3-42
DS23F1
CS5336, CS5338, CS5339
t
t
clkl2
t
t
clkl
clkh2
clkh
ICLKD
ICLKD
t
t
clkw1
t
clkw2
t
OCLKD
OCLKD
(CMODE low)
(CMODE high)
io1
io2
L/R output
L/R output
(MASTER mode)
(MASTER mode)
t
t
t
t
t
ilr1
ilr2
FSYNC output
FSYNC output
(MASTER mode)
(MASTER mode)
ifs1
ifs2
SCLK output
SCLK output
(MASTER mode)
(MASTER mode)
t
isclk1
isclk2
ICLKD to Outputs Propagation Delays (CMODE low)
ICLKD to Outputs Propagation Delays (CMODE high)
SCLK output
(MASTER mode)
t
mslr
t
t
pcf
L/ R output
pdw
(MASTER mode)
t
sdo
DPD
SDATA
t
t
pcr
msfs
DCAL
FSYNC output
(MASTER mode)
SCLK to SDATA, L/R & FSYNC - MASTER Mode
Power Down & Calibration Timing
t
t
t
sclkh
t
slr1
slr2
sclkl
SCLK input
(SLAVE mode)
t
sclkw
t
L/R input
(SLAVE mode)
t
lrdss
dss
MSB
MSB-1
MSB-2
SDATA
SCLK to L/R & SDATA - SLAVE mode, FSYNC high
t
t
sfs1
sfs2
SCLK input
(SLAVE mode)
FSYNC input
(SLAVE mode)
MSB-1
MSB-2
MSB
SDATA
FSYNC to SCLK - SLAVE Mode, FSYNC Controlled.
DS23F1
3-43
CS5336, CS5338, CS5339
RECOMMENDED OPERATING CONDITIONS
(AGND, LGND, DGND = 0V; all voltages with respect to ground)
Parameter
Symbol
Min
Typ
Max
VA+
Units
DC Power Supplies:
Positive Digital
Positive Logic
Positive Analog
Negative Analog
4.75
5.0
5.0
5.0
V
V
V
V
VD+
VL+
VA+
VA-
4.75
4.75
4.75
VA+
5.25
5.25
_
_
_
5.0
_
V
Analog Input Voltage
V
3.68
-
(Note 7)
3.68
AIN
Notes: 7. The ADCs accept input voltages up to the analog supplies (VA+, VA-). They will produce a positive
full-scale output for inputs above 3.68 V and negative full-scale output for inputs below -3.68 V. These
values are subject to the gain error tolerance specification. Additional tag bits are output to indicate
the amount of overdrive.
+5V Digital
+
Ferrite Bead
0.1
µ
F
µ
1 F
+5V Analog
+
0.1
µ
F
51
Ω
1
µ
F
0.1 µF
18
VD+
4
25
VA+
VL+
6
10
7
Power Down
28
APD
VREF
& Calibrate
Control
0.1
µ
F
10
µ
F
DPD
+
ACAL
9
DCAL
Left Analog Input
51
2
AINL
AINR
CS5336
CS5338
CS5339
13
12
Ω
10 nF
10 nF
SMODE
CMODE
Mode
Settings
Right Analog Input
51
27
Audio
Data
Processor
Ω
16
A/D CONVERTER
SDATA
14
15
17
3
26
1
L/R
Timing
Logic
ZEROL
ZEROR
AGND
SCLK
FSYNC
ICLKD
& Clock
20
21
23
OCLKD
ICLKA
Ferrite bead may
be used if VD+ is
derived from VA+.
If used, do not drive
any other logic
from VD+.
An example ferrite
bead is Permag
VK200-2.5/52
8
NC
NC
22
VA-
LGND
24
DGND
19
TST
VA+
5
11
-5V Analog
+
0.1
µF
1
µF
Figure 1. Typical Connection Diagram
3-44
DS23F1
CS5336, CS5338, CS5339
SYSTEM DESIGN
GENERAL DESCRIPTION
The CS5336, CS5338, and CS5339 are 16-bit, 2-
channel A/D converters designed specifically for
stereo digital audio applications. The devices use
two one-bit delta-sigma modulators which simul-
taneously sample the analog input signals at a 64
X sampling rate. The resulting serial bit streams
are digitally filtered, yielding pairs of 16-bit val-
ues. This technique yields nearly ideal conversion
performance independent of input frequency and
amplitude. The converters do not require difficult-
to-design or expensive anti-alias filters, and do not
require external sample-and-hold amplifiers or a
voltage reference.
Very few external components are required to sup-
port the ADC. Normal power supply decoupling
components, voltage reference bypass capacitors
and a single resistor and capacitor on each input
for anti-aliasing are all that’s required, as shown
in Figure 1.
Master Clock Input
The master input clock (ICLKD) into the ADC
runs the digital filter, and is used to generate the
modulator sampling clock. ICLKD frequency is
determined by the desired Output Word Rate
(OWR) and the setting of the CMODE pin.
CMODE high will set the required ICLKD fre-
quency to 384 X OWR, while CMODE low will
set the required ICLKD frequency to 256 X
OWR. Table 1 shows some common clock fre-
quencies. The digital output clock (OCLKD) is
always equal to 128 X OWR, which is always
2 X the input sample rate. OCLKD should be
connected to ICLKA, which controls the input
sample rate.
An on-chip voltage reference provides for an in-
put signal range of ± 3.68 volts. Any zero offset is
internally calibrated out during a power-up self-
calibration cycle. Output data is available in serial
form, coded as 2’s complement 16-bit numbers.
Typical power consumption of only 400 mW can
be further reduced by use of the power-down
mode.
For more information on delta-sigma modulation
and the particular implementation inside these
ADCs, see the references at the end of this data
sheet.
The phase alignment between ICLKD and
OCLKD is determined as follows: when CMODE is
0
1
2
3
4
5
6
7
ICLKD
Input
DPD
*
Input
_
OCLKD/
L/ R
Input
1
1
L/R
CMODE
ICLKD
(MHz)
ICLKA
(MHz)
SCLK
(MHz)
**
(kHz)
OCLKD
32
low
high
low
8.192
4.096
4.096
2.048
2.048
2.8224
2.8224
3.072
3.072
Output
_
32
12.288
L/ R
Input
2
2
***
44.1
44.1
48
11.2896 5.6448
16.9344 5.6448
OCLKD
Output
high
low
12.288
18.432
6.144
6.144
* DPD low is recognized on the next ICLKD rising edge (#0)
** L/R rising before ICLKD rising #2 causes OCLKD -1
*** L/R rising after ICLKD rising #2 causes OCLKD - 2
48
high
Table 1. Common Clock Frequencies
Figure 2. ICLKD to OCLKD Timing with CMODE
high (384 X OWR)
DS23F1
3-45
CS5336, CS5338, CS5339
L/ R
Output
0
1
2
3
16 17 18 19 20 21
31
0
1
2
3
16 17 18 19 20 21
31
0
1
*
SCLK
Output
FSYNC
Output
SDATA
Output
15 14
1
0
T2 T1 T0
Tag Bits
15 14
1
0
T2 T1 T0
*
SCLK for CS5336/8.
SCLK inverted for
CS5339
Left Audio Data
Left Data Tag
Right Audio Data Tag Bits
Right Data Tag
Figure 3. Data Output Timing - MASTER mode
L/ R
Input
15
30
15 16
17 18 19 20 21
0
1
2
16 17 18 19 20
31
0
1
2
31
0
1
*
SCLK
Input
FSYNC
Input (high)
SDATA
15 14
1
0
T2 T1 T0
15 14
1
0
T2 T1 T0
Output
*
SCLK for CS5336/8.
SCLK inverted for
CS5339
Left Audio Data
Tag Bits
Left Data Tag
Right Audio Data Tag Bits
Right Data Tag
Figure 4. Data Output Timing - SLAVE Mode, FSYNC high
low, ICLKD is divided by 2 to generate OCLKD.
The phase relationship between ICLKD and
OCLKD is always the same, and is shown in the
Switching Characteristics Timing Diagrams.
When CMODE is high, OCLKD is ICLKD di-
vided by 3. There are two possible phase
relationships between ICLKD and OCLKD,
which depend on the start-up timing between
DPD and L/R, shown in Figure 2.
converter is driven from a master clock (ICLKD)
and outputs all other clocks, derived from ICLKD
(see Figure 3). Notice the one SCLK cycle delay
between L/R edges and FSYNC rising edges.
FSYNC brackets the 16 data bits for each chan-
nel.
In SLAVE mode, L/R and SCLK are inputs. L/R
must be externally derived from ICLKD, and
should be equal to the Output Word Rate. SCLK
should be equal to the input sample rate, which is
equal to OCLKD/2. Other SCLK frequencies are
possible, but may degrade dynamic range because
of interference effects. Data bits are clocked out
via the SDATA pin using the SCLK and L/R in-
puts. The rising edge of SCLK causes the ADC to
Serial Data Interface
The serial data output interface has 3 possible
modes of operation: MASTER mode, SLAVE
mode with FSYNC high, and SLAVE mode with
FSYNC controlled. In MASTER mode, the A/D
3-46
DS23F1
CS5336, CS5338, CS5339
L/ R
Input
0
1
2
15 16 17 18 19 20
0
1
2
15 16 17 18 19 20
*
SCLK
Input
FSYNC
Input
***
***
**
**
SDATA
Output
15
15 14
1
0
T2 T1 T0
Tag Bits
15
15 14
1
0
T2 T1 T0
Tag Bits
Left Audio Data
Left Data
Tag
Right Audio Data
Right Data
Tag
*
**
***
SCLK for CS5336/8.
SCLK inverted for CS5339
Rising FSYNC enables
SCLK to clock out SDATA
Falling FSYNC stops SCLK from
clocking out SDATA
Figure 5. Data Output Timing - SLAVE Mode, FSYNC controlled
output each bit, except the MSB, which is clocked
out by the L/R edge. As shown in Figure 4, when
FSYNC is high, serial data bits are clocked imme-
diately following the L/R edge.
position in time the data bits onto a common se-
rial bus.
The serial nature of the output data results in the
left and right data words being read at different
times. However, the words within an L/R cycle
represent simultaneously sampled analog inputs.
In SLAVE mode with FSYNC controlled, as
shown in Figure 5, when FSYNC is low, only the
MSB is clocked out after the L/R edge. With
FSYNC low, SCLK is ignored. When it is desired
to start clocking out data, bring FSYNC high
which enables SCLK to start clocking out data.
Bringing FSYNC low will stop the data being
clocked out. This feature is particularly useful to
In all modes, additional bits are output after the
data bits: 3 tag bits and a left/right indicator. The
tag bits indicate a near-to-clipping input condition
for the data word to which the tag bits are at-
tached. Table 2 shows the relationship between
input level and the tag bit values. The serial bit
immediately following the tag bits is 0 for the
left channel, and 1 for the right channel. The re-
maining bits before the next L/R edge will be 1’s
for the left channel and 0’s for the right channel.
Normally, the tag bits are separated from the
audio data by the digital signal processor. How-
ever, if the tag bits are interpreted as audio data,
their position below the LSB would result as a
very small dc offset.
Input Level
1.375 x FS
T2 T1 T0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1.250 x FS to 1.375 x FS
1.125 x FS to 1.250 x FS
1.000 x FS to 1.125 x FS
-1.006dB to 0.000dB
-3.060dB to -1.006dB
-6.000dB to -3.060dB
< -6.000dB
In all modes, SCLK is shown for the CS5336 and
CS5338, where data bits are clocked out on rising
edges. SCLK is inverted for the CS5339.
FS = Full Scale (0dB) Input
Table 2. Tag Bit Definition
DS23F1
3-47
CS5336, CS5338, CS5339
Certain serial modes align well with various inter-
face requirements. A CS5339 in MASTER mode,
with an inverted L/R signal, generates I S
(Philips) compatible timing. A CS5336 in MAS-
TER mode, using FSYNC, interfaces well with a
Motorola DSP56000. A CS5336 in SLAVE mode
emulates a CS5326 style interface, and also links
up to a DSP56000 in network mode.
mended that the above RC filter is placed between
the active circuitry and the AINR and AINL pins.
The above example frequencies scale linearly with
output word rate.
2
The on-chip voltage reference output is brought
out to the VREF pin. A 10 µF electrolytic capaci-
tor in parallel with a 0.1 µF ceramic capacitor
attached to this pin eliminates the effects of high
frequency noise. Note the negative value of VREF
when using polarized capacitors. No load current
may be taken from the VREF output pin.
Analog Connections
The analog inputs are presented to the modulators
via the AINR and AINL pins. The analog input
signal range is determined by the internal voltage
reference value, which is typically -3.68 volts.
The input signal range therefore is typically
± 3.68 volts.
The analog input level used as zero during the
offset calibration period (described later) is input
on the ZEROL and ZEROR pins. Typically, these
pins are directly attached to AGND. For the ulti-
mate in offset nulling, networks can be attached to
ZEROR and ZEROL whose impedances match
the impedances present on AINL and AINR.
The ADC samples the analog inputs at
3.072 MHz for a 12.288 MHz ICLKD (CMODE
low). For the CS5336, the digital filter rejects all
noise between 26 kHz and (3.072 MHz-26 kHz).
For the CS5338 and CS5339, the digital filter re-
jects all noise between 28 kHz and
(3.072 MHz-28 kHz). However, the filter will not
reject frequencies right around 3.072 MHz (and
multiples of 3.072 MHz). Most audio signals do
not have significant energy at 3.072 MHz. Never-
theless, a 51 Ω resistor in series with the analog
input, and a 10 nF NPO or COG capacitor to
ground will attenuate any noise energy at 3.072
MHz, in addition to providing the optimum
source impedance for the modulators. The use of
capacitors which have a large voltage coefficient
(such as general purpose ceramics) should be
avoided since these can degrade signal linearity. If
active circuitry precedes the ADC, it is recom-
Power-Down and Offset Calibration
The ADC has a power-down mode wherein typi-
cal consumption drops to 150 µW. In addition,
exiting the power-down state initiates an offset
calibration procedure.
APD and DPD are the analog and digital power-
down pins. When high, they place the analog and
digital sections in the power-down mode. Bring-
ing these pins low takes the part out of
power-down mode. DPD going low initiates a
calibration cycle. If not using the power down
feature, APD should be tied to AGND. When us-
ing the power down feature, DPD and APD may
be tied together if the capacitor on VREF is not
Cal Period
Filter Delay Time
(4096 x L/R clocks)
(85.33 ms @ 48kHz)
(~40 L/R periods)
(~2 ms @ 48 kHz)
DPD
Normal Operation
DCAL
Figure 6. Initial Calibration Cycle Timing
3-48
DS23F1
CS5336, CS5338, CS5339
Power-up Considerations
greater than 10 µF, as stated in the "Power-Up
Considerations" section.
Upon initial application of power to the supply
pins, the data in the calibration registers will be
indeterminate. A calibration cycle should always
be initiated after application of power to replace
potentially large values of data in these registers
with the correct values.
During the offset calibration cycle, the digital sec-
tion of the part measures and stores the value of
the calibration input of each channel in registers.
The calibration input value is subtracted from all
future outputs. The calibration input may be ob-
tained from either the analog input pins (AINL
and AINR) or the zero pins (ZEROL and
ZEROR) depending on the state of the ACAL pin.
With ACAL low, the analog input pin voltages are
measured, and with ACAL high, the zero pin volt-
ages are measured.
The modulators settle very quickly (a matter of
microseconds) after the analog section is powered
on, either through the application of power, or by
exiting the power-down mode. The voltage refer-
ence can take a much longer time to reach a final
value due to the presence of large external capaci-
tance on the VREF pin; allow approximately
5 ms/µF. The calibration period is long enough to
allow the reference to settle for capacitor values of
up to 10 µF. If a larger capacitor is used, addi-
tional time between APD going low and DPD
going low should be allowed for VREF settling
before a calibration cycle is initiated.
As shown in Figure 6, the DCAL output is high
during calibration, which takes 4096 L/R clock
cycles. If DCAL is connected to the ACAL input,
the calibration routine will measure the voltage on
ZEROR and ZEROL. These should be connected
directly to ground or through a network matched
to that present on the analog input pins. Internal
offsets of each channel will thus be measured and
subsequently subtracted.
Grounding and Power Supply Decoupling
As with any high resolution converter, the ADC
requires careful attention to power supply and
grounding arrangements if its potential perform-
ance is to be realized. Figure 1 shows the
recommended power arrangements, with VA+,
VA- and VL+ connected to a clean ± 5 V supply.
VD+, which powers the digital filter, may be run
from the system +5V logic supply, provided that
it is not excessively noisy (< ± 50 mV pk-to-pk).
Alternatively, VD+ may be powered from VA+ via
a ferrite bead. In this case, no additional devices
should be powered from VD+. Analog ground and
digital ground should be connected together near
to where the supplies are brought onto the printed
circuit board. Decoupling capacitors should be as
near to the ADC as possible, with the low value
ceramic capacitor being the nearest.
Alternatively, ACAL may be permanently con-
nected low and DCAL utilized to control a
multiplexer which grounds the user’s front end.
In this case, the calibration routine will measure
and store not only the internal offsets but also
any offsets present in the front end input circuitry.
During calibration, the digital output of both
channels is forced to a 2’s complement zero. Sub-
traction of the calibration input from conversions
after calibration substantially reduces any
power on click that might otherwise be experi-
enced. A short delay of approximately 40 output
words will occur following calibration for the
digital filter to begin accurately tracking audio
band signals.
The printed circuit board layout should have sepa-
rate analog and digital regions and ground planes,
DS23F1
3-49
CS5336, CS5338, CS5339
PERFORMANCE
with the ADC straddling the boundary. All sig-
nals, especially clocks, should be kept away from
the VREF pin in order to avoid unwanted cou-
pling into the modulators. The VREF decoupling
capacitors, particularly the 0.1 µF, must be posi-
tioned to minimize the electrical path from VREF
to Pin 1 AGND and to minimize the path between
VREF and the capacitors. An evaluation board is
available which demonstrates the optimum layout
and power supply arrangements, as well as allow-
ing fast evaluation of the ADC.
FFT Tests
For FFT based tests, a very pure sine wave is pre-
sented to the ADC, and an FFT analysis is
performed on the output data. The resulting spec-
trum is a measure of the performance of the ADC.
Figure 7 shows the spectral purity of the CS5336
with a 1 kHz, -10 dB input. Notice the low noise
floor, the absence of any harmonic distortion, and
the Dynamic Range value of 95.41 dB.
To minimize digital noise, connect the ADC digi-
tal outputs only to CMOS inputs.
Figure 8 shows the CS5336 high frequency per-
formance. The input signal is a -10 dB, 9 kHz
sine wave. Notice the small 2nd harmonic at
110 dB down.
Synchronization of Multiple CS5336/8/9
In systems where multiple ADC’s are required,
care must be taken to insure that the ADC internal
clocks are synchronized between converters to in-
sure simultaneous sampling. In the absence of this
synchronization, the sampling difference could be
one ICLKD period which is typically 81.4 nsec
for a 48 kHz sample rate.
Figure 9 shows the low-level performance of the
CS5336. Notice the lack of any distortion compo-
nents. Traditional R-2R ladder based ADC’s can
have problems with this test, since differential
non-linearities around the zero point become very
significant. Figure 10 shows the same very low
input amplitude performance, but at 9kHz input
frequency.
SLAVE MODE
Synchronous sampling in the slave mode is
achieved by connecting all DPD and APD pins to
a single control signal and supplying the same
ICLKD and L/R to all converters.
MASTER MODE
The internal counters of the CS5336/8/9 are reset
during DPD/APD high and will start simultane-
ously by insuring that the release of DPD/APD
for all converters is internally latched on the same
rising edge of ICLKD. This can be achieved by
connecting all DPD/APD pins to
the same
control signal and insuring that the DPD/APD
falling edge occurs outside a ±30 ns window
either side of an ICLKD rising edge.
3-50
DS23F1
CS5336, CS5338, CS5339
0
-10
-20
-30
-40
-50
-60
-70
-80
0
-10
-20
-30
-40
-50
-60
-70
-80
Output Word Rate: 48 kHz
Full Scale: 7.3 Vp-p
S/(N+D): 85.03 dB
Dynamic Range: 95.033 dB
(dc to 20 kHz)
Output Word Rate: 48 kHz
Full Scale: 7.3 Vp-p
S/(N+D): 85.41 dB
Dynamic Range: 95.41 dB
(dc to 20 kHz)
Signal
Signal
Amplitude
Relative to
Full Scale
(dB)
Amplitude
Relative to
Full Scale
(dB)
-90
-90
-100
-110
-120
-130
-100
-110
-120
-130
0
4
8
12
16
20
24
0
4
8
12
16
20
24
Input Frequency (kHz)
Input Frequency (kHz)
Figure 7. CS5336 FFT Plot with -10 dB, 1 kHz Input
Figure 8. CS5336 FFT Plot with -10 dB, 9 kHz Input
0
-10
-20
-30
-40
-50
-60
-70
-80
0
Output Word Rate: 48 kHz
-10
Output Word Rate: 48 kHz
Full Scale: 7.3 Vp-p
-20
Full Scale: 7.3 Vp-p
S/(N+D): 16.09 dB
Dynamic Range: 96.09 dB
(dc to 20 kHz)
S/(N+D): 15.72 dB
-30
Dynamic Range: 95.72 dB
-40
-50
-60
-70
-80
Signal
Signal
(dc to 20 kHz)
Amplitude
Relative to
Full Scale
(dB)
Amplitude
Relative to
Full Scale
(dB)
-90
-90
-100
-110
-120
-130
-100
-110
-120
-130
0
4
8
12
16
20
24
0
4
8
12
16
20
24
Input Frequency (kHz)
Input Frequency (kHz)
Figure 9. CS5336 FFT Plot with -80 dB, 1 kHz Input
Figure 10. CS5336 FFT Plot with -80 dB, 9 kHz Input
DNL Tests
displays the worst case positive and negative er-
rors in each of 512 groups of 128 codes.
Codewidths typically are within ± 0.2 LSB’s of
ideal. A delta-sigma modulator based ADC has no
inherent mechanism for generating DNL errors.
The residual small deviations shown in Figure 11
are a result of noise. Nevertheless, the perform-
ance shown is extremely good, and is superior to
typical R-2R ladder based designs.
A Differential Non-Linearity test is also shown.
Here, the converter is presented with a linear ramp
signal. The resulting output codes are counted to
yield a number which is proportional to the
codewidth. A plot of codewidth versus code
graphically illustrates the uniformity of the
codewidths. Figure 11 shows the excellent Differ-
ential Non-Linearity of the CS5336. This plot
DS23F1
3-51
CS5336, CS5338, CS5339
+1
+1/2
0
-1/2
-1
0
32,768
65,535
Codes
Figure 11. CS5336 Differential Non-Linearity Plot
Digital Filter
Figures 12 through 17 show the performance of
the digital filter included in the ADC. All the plots
assume an output word rate of 48 kHz. The filter
frequency response will scale precisely with
changes in output word rate. The passband ripple
is flat to ± 0.01 dB maximum. Stopband rejection
is greater than 80 dB.
Figures 12,14 &16 show the CS5338 and CS5339
filter characteristics. Figure 17 is an expanded
view of the transition band.
Figures 13,15 & 17 show the CS5336 filter char-
acteristics. Figure 17 is an expanded view of the
transition band.
3-52
DS23F1
CS5336, CS5338, CS5339
10
0
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
0
8
16
24
32
40
48
0
8
16
24
32
40
48
Input Frequency (kHz)
Input Frequency (kHz)
Figure 12. CS5338/9 Digital Filter Stopband Rejection
Figure 13. CS5336 Digital Filter Stopband Rejection
0.020
0.010
0.000
-0.010
-0.020
0.020
0.010
0.000
-0.010
-0.020
0
4
8
12
16
20
24
0
4
8
12
16
20
24
Input Frequency (kHz)
Input Frequency (kHz)
Figure 14. CS5338/9 Digital Filter Passband Ripple
Figure 15. CS5336 Digital Filter Passband Ripple
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
20
21
22
23
24
25
26
27
28
22
23
24
25
26
27
28
29
30
Input Frequency (kHz)
Input Frequency (kHz)
Figure 16. CS5338/9 Digital Filter Transition Band
DS23F1
Figure 17. CS5336 Digital Filter Transition Band
3-53
CS5336, CS5338, CS5339
PIN DESCRIPTIONS
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ANALOG GROUND AGND
LEFT CHANNEL ANALOG INPUT AINL
LEFT CHANNEL ZERO INPUT ZEROL
VREF VOLTAGE REFERENCE OUTPUT
2
AINR
ZEROR RIGHT CHANNEL ZERO INPUT
VL+ ANALOG SECTION LOGIC POWER
RIGHT CHANNEL ANALOG INPUT
3
4
POSITIVE ANALOG POWER
NEGATIVE ANALOG POWER
ANALOG POWER DOWN INPUT
VA+
VA-
APD
5
LGND ANALOG SECTION LOGIC GROUND
ICLKA ANALOG SECTION CLOCK INPUT
6
7
ANALOG CALIBRATE INPUT ACAL
NO CONNECT NC
DIGITAL CALIBRATE OUTPUT DCAL
NC
NO CONNECT
8
OCLKD DIGITAL SECTION OUTPUT CLOCK
ICLKD DIGITAL SECTION CLOCK INPUT
DGND DIGITAL GROUND
9
10
11
12
13
14
DIGITAL POWER DOWN INPUT
TEST
DPD
TST
VD+
DIGITAL SECTION POSITIVE POWER
SELECT CLOCK MODE CMODE
SELECT SERIAL I/O MODE SMODE
FSYNC FRAME SYNC SIGNAL
SDATA SERIAL DATA OUTPUT
SCLK SERIAL DATA CLOCK
LEFT/RIGHT SELECT
L/R
Power Supply Connections
VA+ - Positive Analog Power, PIN 4.
Positive analog supply. Nominally +5 volts.
VL+ - Positive Logic Power, PIN 25.
Positive logic supply for the analog section. Nominally +5 volts.
VA- - Negative Analog Power, PIN 5.
Negative analog supply. Nominally -5 volts.
AGND - Analog Ground, PIN 1.
Analog ground reference.
LGND - Logic Ground, PIN 24
Ground for the logic portions of the analog section.
VD+ - Positive Digital Power, PIN 18.
Positive supply for the digital section. Nominally +5 volts.
DGND - Digital Ground, PIN 19.
Digital ground for the digital section.
Analog Inputs
AINL, AINR - Left and Right Channel Analog Inputs, PINS 2, 27
Analog input connections for the left and right input channels. Nominally ±3.68 volts full
scale.
3-54
DS23F1
CS5336, CS5338, CS5339
ZEROL, ZEROR - Zero Level Inputs for Left and Right Channels, PINS 3, 26.
Analog zero level inputs for the left and right channels. The levels present on these pins
can be used as zero during the offset calibration cycle. Normally connected to AGND,
optionally through networks matched to the analog input networks.
Analog Outputs
VREF - Voltage Reference Output, PIN 28.
Nominally -3.68 volts. Normally connected to a 0.1µF ceramic capacitor in parallel with a
10µF or larger electrolytic capacitor. Note the negative output polarity.
Digital Inputs
ICLKA - Analog Section Input Clock, PIN 23.
This clock is internally divided by 2 to set the modulators’ sample rate. Sampling rates,
output rates, and digital filter characteristics scale to ICLKA frequency. ICLKA frequency
is 128 X the output word rate. For example, 6.144 MHz ICLKA corresponds to an output
word rate of 48 kHz per channel. Normally connected to OCLKD.
ICLKD - Digital Section Input Clock, PIN 20.
This is the clock which runs the digital filter. ICLKD frequency is determined by the
required output word rate and by the CMODE pin. If CMODE is low, ICLKD frequency
should be 256 X the desired output word rate. If CMODE is high, ICLKD should be
384 X the desired output word rate. For example, with CMODE low, ICLKD should be
12.288 MHz for an output word rate of 48 kHz. This clock also generates OCLKD,
which is always 128 X the output word rate.
APD - Analog Power Down, PIN 6.
Analog section power-down command. When high, the analog circuitry is in power-down
mode. APD is normally connected to DPD when using the power down feature. If power
down is not used, then connect APD to AGND.
DPD - Digital Power Down, PIN 10
Digital section power-down command. Bringing DPD high puts the digital section into
power-down mode. Upon returning low, the ADC starts an offset calibration cycle. This
takes 4096 L/R periods (85.33 ms with a 12.288 MHz ICLKD). DCAL is high during the
calibrate cycle and goes low upon completion. DPD is normally connected to APD when
using the power down feature. A calibration cycle should always be initiated after
applying power to the supply pins.
ACAL - Analog Calibrate, PIN 7.
Analog section calibration command. When high, causes the left and right channel
modulator inputs to be internally connected to ZEROL and ZEROR inputs respectively.
May be connected to DCAL.
DS23F1
3-55
CS5336, CS5338, CS5339
CMODE - Clock Mode Select, PIN 12.
CMODE should be tied low to select an ICLKD frequency of 256 X the output word rate.
CMODE should be tied high to select an ICLKD frequency of 384 X the output word
rate.
SMODE - Serial Interface Mode Select, PIN 13.
SMODE should be tied high to select serial interface master mode, where SCLK, FSYNC
and L/R are all outputs, generated by internal dividers operating from ICLKD. SMODE
should be tied low to select serial interface slave mode, where SCLK, FSYNC and L/R
are all inputs. In slave mode, L/R, FSYNC and SCLK need to be derived from ICLKD
using external dividers.
Digital Outputs
SDATA - Serial Data Output, PIN 16.
Audio data bits are presented MSB first, in 2’s complement format. Additional tag bits,
which indicate input overload and left/right channel data, are output immediately
following each audio data word.
DCAL - Digital Calibrate Output, PIN 9.
DCAL rises immediately upon entering the power-down state (DPD brought high). It
returns low 4096 L/R periods after leaving the power down state (DPD brought low),
indicating the end of the offset calibration cycle (which = 85.33 ms with a 12.288 MHz
ICLKD). May be connected to ACAL.
OCLKD - Digital Section Output Clock, PIN 21.
OCLKD is always 128 X the output word rate. Normally connected to ICLKA.
Digital Inputs or Outputs
SCLK - Serial Data Clock, PIN 15.
Data is clocked out on the rising edge of SCLK for the CS5336 and CS5338. Data is
clocked out on the falling edge of SCLK for the CS5339.
In master mode (SMODE high), SCLK is a continuous output clock at 64 X the output
word rate.
In slave mode (SMODE low), SCLK is an input, which requires a continuously supplied
clock at any frequency from 32 X to 128 X the output word rate (64 X is preferred).
When FSYNC is high, SCLK clocks out serial data, except for the MSB which appears on
SDATA when L/R changes.
3-56
DS23F1
CS5336, CS5338, CS5339
L/R - Left/Right Select, PIN 14.
In master mode (SMODE high), L/R is an output whose frequency is at the output word
rate. L/R edges occur 1 SCLK cycle before FSYNC rises. When L/R is high, left channel
data is on SDATA, except for the first SCLK cycle. When L/R is low, right channel data is
on SDATA, except for the first SCLK cycle. The MSB data bit appears on SDATA one
SCLK cycle after L/R changes.
In slave mode (SMODE low), L/R is an input which selects the left or right channel for
output on SDATA. The rising edge of L/R starts the MSB of the left channel data. L/R
frequency must be equal to the output word rate.
Although the outputs of each channel are transmitted at different times, the two words in
an L/R cycle represent simultaneously sampled analog inputs.
FSYNC - Frame Synchronization Signal, PIN 17.
In master mode (SMODE high), FSYNC is an output which goes high coincident with the
start of the first SDATA bit (MSB) and falls low immediately after the last SDATA audio
data bit (LSB).
In slave mode (SMODE low), FSYNC is an input which controls the clocking out of the
data bits on SDATA. FSYNC is normally tied high, which causes the data bits to be
clocked out immediately following L/R transitions. If it is desired to delay the data bits
from the L/R edge, then FSYNC must be low during the delay period. Bringing FSYNC
high will then enable the clocking out of the SDATA bits. Note that the MSB will be
clocked out based on the L/R edge, independent of the state of FSYNC.
Miscellaneous
NC - No Connection, PINS 8, 22.
These two pins are bonded out to test outputs. They must not be connected to any external
component or any length of PC trace.
TST -Test Input, PIN 11.
Allows access to the ADC test modes, which are reserved for factory use. Must be tied to
DGND.
DS23F1
3-57
CS5336, CS5338, CS5339
PARAMETER DEFINITIONS
N,
Resolution - The total number of possible output codes is equal to 2 where N = the number of bits
in the output word for each channel.
Dynamic Range - Full scale (RMS) signal to broadband noise ratio. The broadband noise is measured
over the specified bandwidth, and with an input signal 60dB below full-scale. Units in decibels.
Signal-to-(Noise plus Distortion) Ratio - The ratio of the rms value of the signal to the rms sum of all
other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including
distortion components. Expressed in decibels.
Total Harmonic Distortion - The ratio of the rms sum of all harmonics up to 20 kHz to the rms value
of the signal. Units in percent.
Interchannel Phase Deviation - The difference between the left and right channel sampling times.
Interchannel Isolation - A measure of crosstalk between the left and right channels. Measured for
each channel at the converter’s output with the input under test grounded and a full-scale signal
applied to the other channel. Units in decibels.
Interchannel Gain Mismatch - The gain difference between left and right channels. Units in
decibels.
Gain Error - The deviation of the measured full scale amplitude from the ideal full scale amplitude
value.
Gain Drift - The change in gain value with temperature. Units in ppm/°C.
Bipolar Offset Error - The deviation of the mid-scale transition (111...111 to 000...000) from the ideal
(1/2 LSB below AGND). Units in LSBs.
3-58
DS23F1
CS5336, CS5338, CS5339
REFERENCES
1) "A Stereo 16-bit Delta-Sigma A/D Converter for Digital Audio" by D.R. Welland, B.P. Del Sig-
nore, E.J. Swanson, T. Tanaka, K. Hamashita, S. Hara, K. Takasuka. Paper presented at the 85th
Convention of the Audio Engineering Society, November 1988.
2) " The Effects of Sampling Clock Jitter on Nyquist Sampling Analog-to-Digital Converters, and on
Oversampling Delta Sigma ADC’s" by Steven Harris. Paper presented at the 87th Convention of the
Audio Engineering Society, October 1989.
3) " An 18-Bit Dual-Channel Oversampling Delta-Sigma A/D Converter, with 19-Bit Mono Applica-
tion Example" by Clif Sanchez. Paper presented at the 87th Convention of the Audio Engineering
Society, October 1989.
Ordering Guide
Model
Resolution
16-bits
16-bits
16-bits
16-bits
16-bits
16-bits
16-bits
16-bits
16-bits
Passband
22 kHz
22 kHz
24 kHz
24 kHz
22 kHz
22 kHz
24 kHz
24 kHz
22 kHz
SCLK
↑ active
↑ active
↑ active
↓ active
↑ active
↑ active
↑ active
↓ active
↑ active
Temperature
0°C to 70 °C
-40 to +85 °C
0°C to 70 °C
0°C to 70 °C
0°C to 70 °C
-40 to +85 °C
0°C to 70 °C
0°C to 70 °C
-55 to +125 °C
Package
CS5336-KP
CS5336-BP
CS5338-KP
CS5339-KP
CS5336-KS
CS5336-BS
CS5338-KS
CS5339-KS
CS5336-TC
28-pin Plastic DIP
28-pin Plastic DIP
28-pin Plastic DIP
28-pin Plastic DIP
28-pin SOIC
28-pin SOIC
28-pin SOIC
28-pin SOIC
28-pin Sidebrazed Ceramic DIP
CDB5336
CDB5338
CDB5339
CS5336 Evaluation Board
CS5338 Evaluation Board
CS5339 Evaluation Board
DS23F1
3-59
CDB5336
CDB5338 CDB5339
Semiconductor Corporation
Evaluation Board for CS5336, CS5338 & CS5339
Features
General Description
The CDB5336, CDB5338 & CDB5339 evaluation
boards allow fast evaluation of the CS5336, CS5338
and CS5339 16-bit, stereo A/D converters. The boards
generate all converter timing signals and provide both
parallel and serial output interfaces. Evaluation re-
quires a digital signal processor, a low-distortion signal
source, and a power supply.
Demonstrates recommended layout
and grounding arrangements
•
•
CS8402 Generates AES/EBU, S/PDIF
& CP-340 Compatible Digital Audio
Also included is a CS8402 digital audio transmitter I.C.,
which can generate AES/EBU, S/PDIF & EIAJ CP-340
compatible audio data.
Buffered Serial Output Interface
16-Bit Parallel Output Interface
Digital and Analog Patch Areas
•
•
•
•
The evaluation boards may also be configured to ac-
cept external timing signals for operation in a user
application during system development.
ORDERING INFORMATION:
On-board or externally supplied system
timing
CDB5336, CDB5338, CDB5339
-15V GND +15V
GND +5V
EXTCLKIN
FSYNC
DIGITAL
PATCH
AREA
ANALOG
PATCH
AREA
POWER SUPPLY
REGULATION &
CONDITIONING
L/R
CLOCK / TIMING
GENERATOR
SCLK
SERIAL
OUTPUT
DATA
CS5336,
CS5338,
AINR
Input
Buffer
SDATA
OFFSET
CALIBRATION
NETWORK
OR
CS5339
A IN L
SERIAL TO
PARALLEL
CONVERTER
PARALLEL
OUTPUT
DATA
Input
Buffer
A/D CONVERTER
CS8402
DIGITAL
AUDIO
DATA
DIGITAL AUDIO
LINE DRIVER
AUG ’93
DS23DB5
3-60
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 FAX: (512) 445 7581
CDB5336,8,9
Power Supply Circuitry
ken before L1 may be installed. R5 and C7 low-
pass filter the analog logic power supply pin,
VL+. The evaluation board uses both an analog
and a digital ground plane which are connected
at a single point by J1. This ground plane ar-
rangement isolates the board’s digital logic from
the analog circuitry.
The schematic diagram in Figure 1 shows the
evaluation board power supply circuitry. Power
is supplied to the evaluation board by five bind-
ing posts. The ±5 Volt analog power supply
inputs of the converter are derived from ±15
Volts using the voltage regulators U10 and U11.
The +5 Volt digital supply for the converter and
the discrete logic on the board is provided by the
+5V and DGND binding posts. D1, D2 and D4
are transient suppressors which also provide pro-
tection from incorrectly connected power supply
leads. C25-C28, C30 and C31 provide general
power supply filtering for the analog supplies.
As shown in Figure 2, C10-C13 provide local-
ized decoupling for the converter VA+ and VA-
pins. Note that C13 is connected between VA-
and VA+ and not VA- and AGND. Space for a
ferrite bead inductor, L1, has been provided so
that the board may be modified to power the
converter’s VD+ input directly from the VA+
supply. Note that the trace connecting the VD+
power to the VD+ of the converter must be bro-
Offset Calibration & Reset Circuit
Figure 1, shows the optional offset calibration
circuit provided on the evaluation board. Upon
power-up, this circuit provides a pulse on the
Analog-to-Digital Converter’s DPD pin initiating
an offset calibration cycle. Releasing SW1 also
initiates an offset calibration cycle. P6 (see Fig-
ure 2) selects the signal source used during
offset calibration. In the "AIN" position, the
AINL and AINR inputs are selected during cali-
bration, while in the "ZERO" position, the
ZEROL and ZEROR inputs are selected.
U10
78L05
COM
IN
OUT
VA+
+15V
C27
C25
C30
+
+
D2
D4
0.47 uF
0.22 uF
47 uF
J1
AGND
C31
C26
C28
AGND
DGND
47 uF
0.22 uF
0.47 uF
COM
79L05
U11
VA-
IN
-15V
OUT
9
8
D2 = D4 = 1N6276A 1.5KE
D1 = P6KE-6V8P from Thomson
RST
CS8402
U7E
VD+
VD+
+5V
C8
C9
R26
10k
+
D3
1N4148
D1
47 uF
0.1 uF
11
10
Cal
DGND
(DPD CS5336)
SW1
CAL
0.1uF
C15
U7D
Figure 1. Power Supply and Reset Circuitry
DS23DB5
3-61
CDB5336,8,9
0.1 uF
C16
10 uF
C17
+
28
VREF
22
8
VD+
NC
NC
18
6
VD+
VD+
APD
DPD
1 uF
C6
0.1 uF
C5
+
10
Cal
L1
Cal
VL+
P6
R5
51
AIN
ZERO
7
9
25
4
VL+
VA+
ACAL
DCAL
0.1 uF
VA+
C7
VD+
DCAL
20 k
12
U1
VA+
CMODE
0.1 uF
1 uF
C10
+
+
R7
C12
CS5336
CS5338
CS5339
13
11
Pins 1,13
U9
SMODE
1
5
AGND
TST
1 uF
C11
0.1 uF
C13
L/R
VA-
14
L/R
L/R
VA-
VA-
SDATA
SCLK
24
19
LGND
DGND
16
15
SDATA
SDATA
SCLK
R1
51
SCLK
27
2
AINR
FSYNC
10 nF
NPO
C1
From
Buffers
Fig 3
17
FSYNC
ICLKD
FSYNC
R2
51
20
AINL
ICLKD
10 nF
NPO
C2
OCLKD
21
ICLKA
23
ZEROL
ZEROR
26
3
P7
ICLKA
C3*
C4*
10 nF
R3*
51
R4*
51
EXT
INT
10 nF
NC
1
VD+
U3
R6*
75
* Optional
VD+
12.288 MHz
Oscillator
Module
2
1
8
7
14
14
C14
0.1 uF
C15
7
3
U8A
0.1 uF
MCK
8402
EXT
CLKIN
Figure 2 ADC Connections
3-62
DS23DB5
CDB5336,8,9
Analog Inputs
tance. Also remove U13 op-amp, to remove the
1kΩ load impedance.
As shown in Figure 2, the analog input signals
are connected to the CS5336 via an RC network.
R1 and C1 provide antialiasing and optimum
source impedance for the right analog input
channel while R2 and C2 do so for the left chan-
nel. The ZEROR and ZEROL inputs are tied to
the analog ground plane on the board as shipped
from the factory, but space is provided for an op-
tional RC section on each. These RC sections
may be added to model the output impedance of
the analog signal source to minimize offset error
during calibration.
Timing Generator
P7 selects the master clock source supplied to
the ICLKD pin of the converter. As shipped from
the factory, P7 is set to the "INT" position to
select the 12.288 MHz clock signal provided by
U3. An external master clock signal may be con-
nected to the EXTCLKIN connector and selected
by placing P7 in the "EXT" position. Note that
R6, tied between EXTCLKIN and GND, is
available for impedance matching an external
clock source. The board is shipped with SMODE
high, which selects MASTER timing mode. In
this mode, SCLK, L/R and FSYNC are all out-
puts, generated by the converter from ICLKD.
Figure 3 shows the optional input buffer circuit.
This can be used as an example input buffer cir-
cuit for your application. If the ADC is driven
from a 50Ω source impedance signal generator,
the input buffer amplifiers may be bypassed.
Place P8 and P9 jumpers in the OUT position,
and short circuit R1 and R2. This ensures that
the ADC is driven from a 50Ω source resis-
Serial Output Interface
The serial output interface is provided by the
SDATA, SCLK, FSYNC and L/R BNC
connectors on the evaluation board. These out-
1 k
VA+
8
R22
0.1 uF
C32
1 k
_
2
3
AINL
IN
R1, Fig 2
U13A
R21
1
+
OUT
4
0.1 uF
C33
P8
VA-
1 k
R24
1 k
_
6
5
MC33078P
7
AINR
IN
R2, Fig 2
U13B
R23
+
OUT
P9
Figure 3. Input Buffer Circuit
DS23DB5
3-63
CDB5336,8,9
VD+
10 k
SIP
8
1
4
2
5
6
7
9 3
P4
OCLKD
DIPSW 8
SW 2
5
6
____
14
15
13
12
11
9
3
2
4
5
6
8
7
1
2
1
19
MCK
SCK
VD+
PRO
__ __
C7/C3
VD+
+
C34
1 uF
C24
0.1 uF
18
15
__
GND
CBL
3
4
P3
C1/FC0
__ __
C6/C2
CBL
V
__ ___
12
13
14
24
CS8402
U2
9
10
11
C9/C15
V
__
EM1/C8
__
EM0/C9
R16 20 k
R17 20 k
C
C
U
10
16
U
CRE/FC1
___
RST
____
RST
R18 20 k
16
20
21
22
23
M0
M1
M2
R19
110
3
1
TXP
R20
17
TXN
SDATA
8
FSYNC
2
4
VD+
7
SCHOTT 67125450
PULSE PE65612
13
12
13
FSYNC
SDATA
11
_
CS5336
RESET2
U8D
12
9
8
L/R CS5336
Q2
D2
74HC08
74HC74
U12B
11
__
Q2
CLK
FSYNC CS5336
SET2
10
R11
47 k
+5 V
Figure 4. CS8402 Digital Audio Line Driver Connections
puts are buffered, as shown in Figure 5, in order
to isolate the converter from the digital signal
processor. If slave mode is selected by pulling
SMODE low, then U9 (74HC243) will change to
the opposite direction, and act as an input buffer.
U9 is provided to protect against inadvertent ex-
ternal driving of SCLK, L/R and FSYNC while
in MASTER mode. U9 is not necessary in your
application circuit.
Jumper P4 allows the board to be configured for
either the CS5336/38, or the CS5339, which
have opposite polarities of SCLK.
Parallel Output Interface
Figure 6 depicts the parallel output interface on
the evaluation board. 16-bit words are assembled
from the serial data output of the converter. Each
bit of serial data is clocked out of the converter
3-64
DS23DB5
CDB5336,8,9
VD+
20 k
1
R8
A-to-B
Enable
13
SMODE
VD+
13
11
14
B-to-A
Enable
VCC
0.1 uF
C20
SCLK
15
17
7
3
B1
GND
A1
SCLK
U9
SCLK
FSYNC
L/R
FSYNC
74HC243
10
B2
B3
A4
FSYNC
4
5
L/R
14
16
A2
A3
9
6
L/R
SDATA
SDATA
SDATA
B4
VD+
10
R10
20 k
8
4
5
R9
20 k
9
6
U8B
U8C
CS8402
Pin 6
74HC08
U7B
8
3
4
5336/38
5337/39
SDATA
Pin 11
U4, U5
595’s
P4
Figure 5. Serial Output Interface
on the rising edge of SCLK and shifted into the
16-bit shift register formed by U4 and U5 on
SCLK’s falling edge. After all data bits for the
selected channel have been shifted into U4 and
U5 the data is latched onto P1 by a delayed ver-
sion of FSYNC.
processor. (Set jumper P2 to the DRDY posi-
tion.) The fall of DRDY informs the digital
signal processor that a new data word is avail-
able. The processor then reads the port and
acknowledges the transfer by asserting DACK.
Note that DRDY will not be asserted again un-
less DACK is momentarily brought high
although new data will continue to be latched
onto the port.
P5 selects the channel whose output data will be
converted to parallel form and presented on P1.
With P5 in the "B" (both) position, parallel data
from one channel will be presented first with
data from the other channel presented sub-
sequently. In the "L" (left) position, only left
channel conversions will be presented, while in
the "R" (right) position only right channel con-
versions are presented.
Digital Audio Standard Interface
Included on the evaluation board is a CS8402
Digital Audio Line Driver. This device can im-
plement AES/EBU, S/PDIF and EIAJ CP-340
interface standards. Figure 4 shows the sche-
matic for the CS8402. P3 allows the C, U and V
bits to be driven from external logic using the
CBL output for block synchronization. SW2 pro-
vides 8 DIP switches to select various modes
and bits for the CS8402. Table 3 lists the settings
for the professional mode which is the default
setting for the evaluation board from the factory.
The third switch selects between professional
Two interface mechanisms are provided for read-
ing the data from this port. With the first, the
edges of L/R may be used to clock the parallel
data into the digital signal processor. (Set jumper
P2 into the L/R position.) Alternatively, a hand-
shake protocol implemented with DACK and
DRDY may be used to transfer data to the signal
DS23DB5
3-65
CDB5336,8,9
X
Y
Z
P1
Z
Y
X
L/R
PIN14
U1
VD+
RP3
DIP Resistor
68
P5
9
VD+
B
L
R
DOUT
VCC
16
7
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
D15 (MSB)
D14
Q
Q
Q
Q
H
G
F
U7C
C16
6
6
5
0.1uF
8
5
D13
GND
1
R15
47 k
4
D12
U4
CLR
VD+
E
D
C
B
A
FSYNC
PIN17
U1
2
3
3
D11
5
74HC595 Q
D
Q
Q
10
12
2
D10
Q
Q
Q
SRCLR
6
1
D9
Latch CLK
U12A
CLK
15
D8
11
Shift CLK
DIN
ICLKD
PIN20
U1
14
OE
13
VD+
0.1 uF
VCC
14
PRE GND
4
7
C29
R11
VD+
47 k
RP2
P4
DIP Resistor
68
9
13
OE
VD+
DOUT
VCC
16
7
1
16
15
14
13
12
11
10
9
D7
Q
H
G
F
C17
6
2
3
4
5
6
7
8
D6
Q
Q
Q
Q
Q
Q
Q
0.1uF
8
5
D5
GND
U5
4
D4
E
D
C
B
A
74HC595
SRCLR
3
D3
10
12
2
D2
1
D1
Latch CLK
11
15
D0 (LSB)
Shift CLK
DIN
DACK
DRDY
VD+
14
VD+
0.1uF
C18
R12 47k
VD+ SDATA
0.1 uF
R14
68
14
2
68
1
C19
1
CLR
14
Q
U7A
74HC14
7
R13
L/R
7
6
L/R
DRDY
3
2
CLK
U6A
74HC74
P2
13
5
CLR
D
Q
12
11
8
9
PRE
4
D
Q
U6B
74HC74
CLK
PRE
Q
47k
10
R11
VD+
Figure 6. Parallel Output Interface
3-66
DS23DB5
CDB5336,8,9
CONNECTOR
INPUT/OUTPUT
SIGNAL PRESENT
+15
-15
input
input
input
input
input
input
input
input
+15 Volts from power supply
-15 Volts from power supply
AGND
+5
analog ground connection from power supply
+5V for ADC VD+ and discrete logic
digital ground connection from power supply
left channel analog input
DGND
AINL
AINR
right channel analog input
EXTCLKIN
external master clock input
L/R
output/input
output
left /right channel signal
serial output data
SDATA
SCLK
output/input
output/input
output
serial output clock
FSYNC
data framing signal
DIGITAL OUTPUT
CS8402 digital output via transformer
CS8402 C,U,V inputs; CBL output
parallel output data
P3
P1
output/input
output
Table 1. System Connections
POSITION
JUMPER
PURPOSE
FUNCTION SELECTED
P6
selects offset calibration
input source
AIN
AINL and AINR selected during
offset calibration
*ZERO
ZEROL and ZEROR selected during
offset calibration
P7
P5
selects master clock source
for CS5326 CLKIN
*INT
EXT
CLKIN provided by U3
CLKIN provided by EXTCLKIN BNC
selects channel for serial to
parallel conversion
*L
R
left channel data presented on P1
right channel data presented on P1
B
left then right channel data
alternately presented on P1
selects L/R or DRDY as the
output status signal presented
on P1
*DRDY
DRDY selected to signal the arrival of
new data for the selected channel
P2
L/R
*IN
L/R selected
P8, P9
P4
selects optional input buffers
Buffer amplifier in circuit
Buffer amplifier bypassed
OUT
selects device type
Correct SCLK for CS5337 & CS5339
Correct SCLK for CS5336 & CS5338
5337/39
5336/38
* Default setting from factory
Table 2. Jumper Selectable Options
DS23DB5
3-67
CDB5336,8,9
Switch#
0=Closed, 1=Open
Comment
Professional Mode, C0=1 (default)
3
1
PRO=0
CRE
Local Sample Address Counter & Reliability Flags
default
0
1
Disabled
Internally Generated (channel status bytes 14-17 and byte 22)
C6,C7 - Sample Frequency
5, 2
C6, C7
1
1
0
0
1
0
1
0
00 - Not Indicated - Default to 48 kHz
01 - 48 kHz
10 - 44.1 kHz
default
11 - 32 kHz
4
C1
C1 - Audio
default
1
0
0 - Normal Audio
1 - Non-Audio
6
C9
C8,C9,C10,C11 - Channel Mode (1 of 4 bits)
1
0
0000 - Not indicated - Default to 2-channel
0100 - Stereophonic
default
8, 7
EM1, EM0
C2,C3,C4 - Emphasis
default
1
1
0
0
1
0
1
0
000 - Not Indicated - default to none
100 - No emphasis
110 - 50/15 µs
111 - CCITT J.17
Table 3. CS8402 Switch Definitions - Professional Mode
and consumer modes; however, the CS8402 out-
put to the transformer must be modified, as
shown below Table 4, to be compatible with the
consumer interface. Table 4 lists the switch set-
tings for consumer mode. If the C input of
connector P3 is used, the input bits are logically
OR’ed with the appropriate DIP switch bits. In
Tables 3 and 4, the ’C’ bits listed in the com-
ment section are taken from the Digital Audio
Interface specifications. As an example, switch 6
in the professional mode (Table 3) controls C9
which is the inverse of channel status bit 9 (also
listed as byte 1, bit 1 in the CS8402 data sheet).
Channel status bit 9 is one of four bits indicating
channel mode. Therefore, using DIP switch 6,
only two of the available channel modes may be
selected. The C input port on connector P3 may
be used to select other channel modes. See the
CS8401 & CS8402 part data sheet for more in-
formation on the operation of the CS8402.
3-68
DS23DB5
CDB5336,8,9
Switch#
0=Closed, 1=Open
Comment
Consumer Mode, C0=0 (Note 1)
3
PRO=1
1, 4
FC1, FC0
C24,C25,C26,C27 - Sample Frequency (encoded 2 of 4 bits)
0
0
1
1
0
1
0
1
0000 - 44.1 kHz
0100 - 48 kHz
1100 - 32 kHz
0000 - 44.1 kHz, CD Mode
2
5
C3
C3,C4,C5 - Emphasis (1 of 3 bits)
1
0
000 - None
100 - 50/15 µs
C2
C2 - Copy/Copyright
1
0
0 - Copy Inhibited/Copyright Asserted
1 - Copy Permitted/Copyright Not Asserted
6
C15
C15 - Generation Status
1
0
0 - Definition is based on category code.
1 -
See CS8402 Data Sheet, Appendix A
8, 7
C8, C9
C8-C14 - Category Code (2 of 7 bits)
1
1
0
0
1
0
1
0
0000000 - General
0100000 - PCM encoder/decoder
1000000 - Compact Disk - CD
1100000 - Digital Audio Tape - DAT
Note: 1. The evaluation board is shipped from the factory in the Professional mode. Changing switch 3 to
open places the CS8402 in Consumer mode; however, the hardware is not set up for consumer
mode. To modify the hardware for Consumer mode, change R19 to 374Ω and add R20 at 90.9Ω.
Then, as shown in the figure below, cut the trace connecting TXN to the transformer, and connect
the transformer side to the ground hole provided. For a full explanation of the consumer hardware
interface, see the CS8402 data sheet, Appendix B.
Table 4. CS8402 Switch Definitions - Consumer Mode
R19
20
3
1
TXP
374
90.9
CS8402
U2
TXN
R20
17
2
4
SCHOTT 67125450
PULSE PE65612
DS23DB5
3-69
CDB5336,8,9
Figure 7. Top Ground Plane Layer (NOT TO SCALE)
3-70
DS23DB5
CDB5336,8,9
Figure 8. Bottom Trace Layer (NOT TO SCALE)
DS23DB5
3-71
CDB5336,8,9
Figure 9. Component Layout (NOT TO SCALE)
3-72
DS23DB5
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