CS5340-DZ [CIRRUS]
ADC, Delta-Sigma, 24-Bit, 1 Func, 2 Channel, Serial Access, PDSO16, 4.40 MM, MO-153, TSSOP-16;
| 型号： | CS5340-DZ |
| 厂家： | 
CIRRUS LOGIC |
| 描述： | ADC, Delta-Sigma, 24-Bit, 1 Func, 2 Channel, Serial Access, PDSO16, 4.40 MM, MO-153, TSSOP-16 转换器 |
| 文件： | 总22页 (文件大小：385K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Confidential Draft
3/11/08
CS5340
101 dB, 192 kHz, Multi-Bit Audio A/D Converter
Features
General Description
Advanced Multi-bit Delta-Sigma Architecture
24-bit Conversion
The CS5340 is a complete analog-to-digital converter
for digital audio systems. It performs sampling, analog-
to-digital conversion, and anti-alias filtering, generating
24-bit values for both left and right inputs in serial form
at sample rates up to 200 kHz per channel.
Supports All Audio Sample Rates Including
192 kHz
The CS5340 uses a 5th-order, multi-bit Delta-Sigma
modulator followed by digital filtering and decimation,
which removes the need for an external anti-alias filter.
101 dB Dynamic Range at 5 V
-94 dB THD+N
The CS5340 is available in a 16-pin TSSOP package
for Commercial (-10° to +70° C) and Automotive grades
(-40° to +85° C). The CDB5340 Customer Demonstra-
tion Board is also available for device evaluation and
implementation suggestions. Please refer to “Ordering
Information” on page 22 for complete ordering
information.
90 mW Power Consumption
High-Pass Filter to Remove DC Offsets
Analog/Digital Core Supplies from 3.3 V to 5 V
Supports Logic Levels between 1.8 V and 5 V
Auto-detect Mode Selection in Slave Mode
Auto-Detect MCLK Divider
The CS5340 is ideal for audio systems requiring wide
dynamic range, negligible distortion and low noise, such
as set-top boxes, DVD-karaoke players, DVD record-
ers, A/V receivers, and automotive applications.
Pin Compatible with CS5341
VA
VD
VL
3.3 V to 5 V
3.3 V to 5 V
1.8 V to 5 V
Auto-detect
MCLK Divider
Master Clock
Single-Ended
Analog Input
Switch-Cap
ADC
Low-Latency
Digital Filters
AINL
High-Pass
Filter
SCLK
LRCK
FILT+
VQ
Slave Mode
Auto-detect
Internal
Reference
Voltages
SDOUT
M0
M1
Mode
Configuration
AINR Switch-Cap
ADC
Low-Latency
Digital Filters
Single-Ended
Analog Input
High-Pass
Filter
Reset
Copyright © Cirrus Logic, Inc. 2008
March '08
DS601F2
(All Rights Reserved)
http://www.cirrus.com
Confidential Draft
3/11/08
CS5340
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 4
SPECIFIED OPERATING CONDITIONS ............................................................................................... 4
ABSOLUTE MAXIMUM RATINGS ......................................................................................................... 4
ANALOG CHARACTERISTICS - COMMERCIAL GRADE .................................................................... 5
ANALOG CHARACTERISTICS - AUTOMOTIVE GRADE ..................................................................... 6
DIGITAL FILTER CHARACTERISTICS ................................................................................................. 7
DC ELECTRICAL CHARACTERISTICS .............................................................................................. 10
DIGITAL CHARACTERISTICS ............................................................................................................. 10
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT ............................................................... 11
2. PIN DESCRIPTION .............................................................................................................................. 13
3. TYPICAL CONNECTION DIAGRAM ................................................................................................... 14
4. APPLICATIONS ................................................................................................................................... 15
4.1 Single-, Double-, and Quad-Speed Modes ..................................................................................... 15
4.2 Operation as Either a Clock Master or Slave ................................................................................. 15
4.2.1 Operation as a Clock Master ................................................................................................. 16
4.2.2 Operation as a Clock Slave with Auto-Detect ....................................................................... 16
4.2.3 Master Clock ......................................................................................................................... 17
4.3 Serial Audio Interface ..................................................................................................................... 17
4.4 Power-Up Sequence ...................................................................................................................... 18
4.5 Analog Connections ....................................................................................................................... 18
4.6 Grounding and Power Supply Decoupling ...................................................................................... 18
4.7 Synchronization of Multiple Devices ............................................................................................... 18
4.8 Capacitor Size on the Reference Pin (FILT+) ................................................................................ 19
5. PARAMETER DEFINITIONS ................................................................................................................ 20
6. PACKAGE DIMENSIONS ................................................................................................................... 21
THERMAL CHARACTERISTICS .......................................................................................................... 21
7. ORDERING INFORMATION ................................................................................................................ 22
8. REVISION HISTORY ............................................................................................................................ 22
2
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Confidential Draft
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CS5340
LIST OF FIGURES
Figure 1.Single-Speed Mode Stopband Rejection ...................................................................................... 8
Figure 2.Single-Speed Mode Stopband Rejection ...................................................................................... 8
Figure 3.Single-Speed Mode Transition Band (Detail) ................................................................................ 8
Figure 4.Single-Speed Mode Passband Ripple .......................................................................................... 8
Figure 5.Double-Speed Mode Stopband Rejection ..................................................................................... 8
Figure 6.Double-Speed Mode Stopband Rejection ..................................................................................... 8
Figure 7.Double-Speed Mode Transition Band (Detail) .............................................................................. 9
Figure 8.Double-Speed Mode Passband Ripple ......................................................................................... 9
Figure 9.Quad-Speed Mode Stopband Rejection ....................................................................................... 9
Figure 10.Quad-Speed Mode Stopband Rejection ..................................................................................... 9
Figure 11.Quad-Speed Mode Transition Band (Detail) ............................................................................... 9
Figure 12.Quad-Speed Mode Passband Ripple ......................................................................................... 9
Figure 13.Master Mode, Left-Justified SAI ................................................................................................ 12
Figure 14.Slave Mode, Left-Justified SAI .................................................................................................. 12
Figure 15.Master Mode, I²S SAI ................................................................................................................ 12
Figure 16.Slave Mode, I²S SAI .................................................................................................................. 12
Figure 17.Typical Connection Diagram ..................................................................................................... 14
Figure 18.CS5340 Master Mode Clocking ................................................................................................ 16
Figure 19.I²S Serial Audio Interface .......................................................................................................... 17
Figure 20.Left-Justified Serial Audio Interface .......................................................................................... 17
Figure 21.CS5340 Recommended Analog Input Buffer ............................................................................ 18
Figure 22.CS5340 THD+N versus Frequency .......................................................................................... 19
LIST OF TABLES
Table 1. Speed Modes and the Associated Output Sample Rates (Fs) .................................................... 15
Table 2. CS5340 Mode Control ................................................................................................................. 15
Table 3. Master Clock (MCLK) Ratios ....................................................................................................... 17
Table 4. Master Clock (MCLK) Frequencies for Standard Audio Sample Rates ...................................... 17
DS601F2
3
Confidential Draft
3/11/08
CS5340
1. CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical
performance characteristics and specifications are derived from measurements taken at typical supply voltages
and T = 25°C.)
A
SPECIFIED OPERATING CONDITIONS
(GND = 0 V, all voltages with respect to 0 V.)
Parameter
Symbol
Min
Typ
Max
Unit
Power Supplies
Analog
Digital
Logic
VA
VD
VL
3.1
3.1
1.7
(Note 1)
3.3
3.3
5.25
5.25
5.25
V
V
V
Ambient Operating Temperature
Commercial
Automotive
TAC
TAC
-10
-40
-
-
70
85
°C
°C
Notes:
1. This part is specified at typical analog voltages of 3.3 V and 5.0 V. See Analog Characteristics - Com-
mercial Grade and Analog Characteristics - Automotive Grade, below, for details.
ABSOLUTE MAXIMUM RATINGS
(GND = 0 V, All voltages with respect to ground.) (Note 2)
Parameter
Symbol
Min
Max
Units
DC Power Supplies:
Analog
Logic
Digital
VA
VL
VD
-0.3
-0.3
-0.3
+6.0
+6.0
+6.0
V
V
V
Input Current
(Note 3)
(Note 4)
(Note 4)
I
-10
GND-0.7
-0.7
+10
VA+0.7
VL+0.7
+95
mA
V
in
Analog Input Voltage
Digital Input Voltage
V
IN
V
V
IND
Ambient Operating Temperature (Power Applied)
Storage Temperature
TA
°C
°C
-50
T
-65
+150
stg
2. Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
3. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SRC latch-up.
4. The maximum over/under voltage is limited by the input current.
4
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Confidential Draft
3/11/08
CS5340
ANALOG CHARACTERISTICS - COMMERCIAL GRADE
Test Conditions (unless otherwise specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is
10 Hz to 20 kHz.
Dynamic Performance for Commercial Grade
VA = 5 V
VA = 3.3 V
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
Single-Speed Mode
Fs = 48 kHz
Dynamic Range
A-weighted
unweighted
95
92
101
98
-
-
92
89
98
95
-
-
dB
dB
Total Harmonic Distortion + Noise
(Note 5)
-1 dB
THD+N
-
-
-
-94
-78
-38
-88
-
-
-
-
-
-91
-75
-35
-85
-
-
dB
dB
dB
-20 dB
-60 dB
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
Double-Speed Mode
Fs = 96 kHz
Dynamic Range
A-weighted
unweighted
95
92
-
101
98
95
-
-
-
92
89
-
98
95
92
-
-
-
dB
dB
dB
40 kHz bandwidth unweighted
Total Harmonic Distortion + Noise
(Note 5)
-1 dB
THD+N
-
-
-
-
-94
-78
-38
-91
-88
-
-
-
-
-91
-75
-35
-85
-85
dB
dB
dB
dB
-20 dB
-60 dB
-
-
-
-
-
-
40 kHz bandwidth
-1 dB
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
Quad-Speed Mode
Fs = 192 kHz
Dynamic Range
A-weighted
unweighted
95
92
-
101
98
95
-
-
-
92
89
-
98
95
92
-
-
-
dB
dB
dB
40 kHz bandwidth unweighted
Total Harmonic Distortion + Noise
(Note 5)
-1 dB
THD+N
-
-
-
-
-94
-78
-38
-91
-88
-
-
-
-
-91
-75
-35
-85
-85
dB
dB
dB
dB
-20 dB
-60 dB
-
-
-
-
-
-
40 kHz bandwidth
-1 dB
Min
Typ
Max
Dynamic Performance All Modes
Interchannel Isolation
DC Accuracy
Unit
-
90
-
dB
Interchannel Gain Mismatch
Gain Error
-
-5
-
0.1
-
-
+5
-
dB
%
Gain Drift
100
ppm/°C
Analog Input Characteristics
Full-Scale Input Voltage
Input Impedance
0.53*VA
-
0.56*VA
25
0.59*VA
-
Vpp
kΩ
5. Referred to the typical full-scale input voltage
DS601F2
5
Confidential Draft
3/11/08
CS5340
ANALOG CHARACTERISTICS - AUTOMOTIVE GRADE
Test Conditions (unless otherwise specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is
10 Hz to 20 kHz.
Dynamic Performance for Automotive Grade
VA = 5 V
VA = 3.3 V
Symbol Min
Typ
Max
Min
Typ
Max
Unit
Single-Speed Mode
Fs = 48 kHz
Dynamic Range
A-weighted
unweighted
93
90
101
98
-
-
90
87
98
95
-
-
dB
dB
Total Harmonic Distortion + Noise
(Note 5)
-1 dB
THD+N
-
-
-
-94
-78
-38
-86
-
-
-
-
-
-91
-75
-35
-83
-
-
dB
dB
dB
-20 dB
-60 dB
Symbol Min
Typ
Max
Min
Typ
Max
Unit
Double-Speed Mode
Fs = 96 kHz
Dynamic Range
A-weighted
unweighted
93
90
-
101
98
95
-
-
-
90
87
-
98
95
92
-
-
-
dB
dB
dB
40 kHz bandwidth unweighted
Total Harmonic Distortion + Noise
(Note 5)
-1 dB
THD+N
-
-
-
-
-94
-78
-38
-91
-86
-
-
-
-
-91
-75
-35
-85
-83
dB
dB
dB
dB
-20 dB
-60 dB
-
-
-
-
-
-
40 kHz bandwidth
-1 dB
Symbol Min
Typ
Max
Min
Typ
Max
Unit
Quad-Speed Mode
Fs = 192 kHz
Dynamic Range
A-weighted
unweighted
93
90
-
101
98
95
-
-
-
90
87
-
98
95
92
-
-
-
dB
dB
dB
40 kHz bandwidth unweighted
Total Harmonic Distortion + Noise
(Note 5)
-1 dB
THD+N
-
-
-
-
-94
-78
-38
-91
-86
-
-
-
-
-91
-75
-35
-85
-83
dB
dB
dB
dB
-20 dB
-60 dB
-
-
-
-
-
-
40 kHz bandwidth
-1 dB
Min
Typ
Max
Dynamic Performance All Modes
Interchannel Isolation
DC Accuracy
Unit
-
90
-
dB
Interchannel Gain Mismatch
Gain Error
-
-10
-
0.1
-
-
+10
-
dB
%
Gain Drift
100
ppm/°C
Analog Input Characteristics
Full-Scale Input Voltage
Input Impedance
0.50*VA
-
0.56*VA
25
0.62*VA
-
Vpp
kΩ
6. Referred to the typical full-scale input voltage
6
DS601F2
Confidential Draft
3/11/08
CS5340
DIGITAL FILTER CHARACTERISTICS
Parameter
Symbol Min
Typ
Max
Unit
Single-Speed Mode
Passband
(-0.1 dB)
(Note 7)
(Note 7)
0
-
0.4895
Fs
dB
Fs
dB
s
Passband Ripple
Stopband
-0.035
0.5687
70
-
0.035
-
-
-
-
-
Stopband Attenuation
Total Group Delay (Fs = Output Sample Rate)
tgd
tgd
tgd
-
12/Fs
Double-Speed Mode
Passband
(-0.1 dB)
(Note 7)
(Note 7)
0
-0.025
0.5604
69
-
0.4895
Fs
dB
Fs
dB
s
Passband Ripple
Stopband
-
0.025
-
-
-
-
-
Stopband Attenuation
Total Group Delay (Fs = Output Sample Rate)
-
9/Fs
Quad-Speed Mode
Passband
(-0.1 dB)
(Note 7)
(Note 7)
0
-0.025
0.5
60
-
0.2604
Fs
dB
Fs
dB
s
Passband Ripple
Stopband
-
0.025
-
-
-
-
-
Stopband Attenuation
Total Group Delay (Fs = Output Sample Rate)
-
5/Fs
High-Pass Filter Characteristics
Frequency Response
-3.0 dB
-0.13 dB
-
1
20
-
-
Hz
Hz
(Note 8)
(Note 8)
Phase Deviation
Passband Ripple
@ 20 Hz
-
-
10
-
-
Deg
dB
0
7. Filter characteristics scale precisely with Fs
8. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs.
DS601F2
7
Confidential Draft
3/11/08
CS5340
0
-10
0
-10
-20
-30
-40
-50
-20
-30
-40
-50
-60
-70
-60
-70
-80
-90
-100
-110
-120
-130
-140
-80
-90
-100
-110
-120
-130
-140
0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60
0.0
0.1
0.2
0.3
0.4
0.5 0.6
0.7 0.8
0.9
1.0
Frequency (normalized to Fs)
Frequency (normalized to Fs)
Figure 1. Single-Speed Mode Stopband Rejection
Figure 2. Single-Speed Mode Stopband Rejection
0.10
0.08
0.06
0.04
0.02
0.00
-0.02
-0.04
-0.06
-0.08
-0.10
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55
Frequency (normalized to Fs)
Frequency (normalized to Fs)
Figure 3. Single-Speed Mode Transition Band (Detail)
Figure 4. Single-Speed Mode Passband Ripple
0
-10
0
-10
-20
-30
-40
-50
-20
-30
-40
-50
-60
-70
-60
-70
-80
-90
-100
-110
-120
-130
-140
-80
-90
-100
-110
-120
-130
-140
0.0
0.1
0.2
0.3
0.4
0.5 0.6
0.7 0.8
0.9
1.0
0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60
Frequency (normalized to Fs)
Frequency (normalized to Fs)
Figure 5. Double-Speed Mode Stopband Rejection
Figure 6. Double-Speed Mode Stopband Rejection
8
DS601F2
Confidential Draft
3/11/08
CS5340
0
0.10
0.08
0.06
0.04
0.02
0.00
-0.02
-0.04
-0.06
-0.08
-0.10
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
0.46
0.47
0.48
0.49
0.50
0.51
0.52
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Frequency (normalized to Fs)
Frequency (normalized to Fs)
Figure 7. Double-Speed Mode Transition Band (Detail)
Figure 8. Double-Speed Mode Passband Ripple
0
-10
0
-10
-20
-30
-40
-50
-20
-30
-40
-50
-60
-70
-60
-70
-80
-90
-100
-110
-120
-130
-140
-80
-90
-100
-110
-120
-130
-140
0.0
0.1
0.2
0.3
0.4
0.5 0.6
0.7 0.8
0.9
1.0
0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85
Frequency (normalized to Fs)
Frequency (normalized to Fs)
Figure 9. Quad-Speed Mode Stopband Rejection
Figure 10. Quad-Speed Mode Stopband Rejection
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
0.10
0.08
0.06
0.04
0.02
0.00
-0.02
-0.04
-0.06
-0.08
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
-0.10
0.00 0.03 0.05 0.08 0.10 0.13 0.15 0.18 0.20 0.23 0.25 0.28
Frequency (normalized to Fs)
Frequency (normalized to Fs)
Figure 11. Quad-Speed Mode Transition Band (Detail)
Figure 12. Quad-Speed Mode Passband Ripple
DS601F2
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Confidential Draft
3/11/08
CS5340
DC ELECTRICAL CHARACTERISTICS
(GND = 0 V, all voltages with respect to 0 V. MCLK=12.288 MHz; Master Mode)
Parameter
Symbol
Min
Typ
Max
Unit
DC Power Supplies:
Positive Analog
Positive Digital
Positive Logic
VA
VD
VL
3.1
3.1
1.7
-
-
-
5.25
5.25
5.25
V
V
V
Power Supply Current
(Normal Operation)
VA = 5 V
VA = 3.3 V
VL,VD = 5 V
IA
IA
ID
ID
-
-
-
-
21
18.2
15
25.5
22.5
18.5
10
mA
mA
mA
mA
9
VL,VD = 3.3 V
Power Supply Current
(Power-Down Mode) (Note 9)
VA = 5 V
VL,VD=5 V
IA
ID
-
-
1.5
0.4
-
-
mA
mA
Power Consumption
(Normal Operation)
VL, VD, VA = 5 V
VL, VD, VA = 3.3 V
(Power-Down Mode)
-
-
-
-
-
-
180
90
9.5
220
107.2
-
mW
mW
mW
PSRR
-
65
-
dB
Power Supply Rejection Ratio (1 kHz)
Q Nominal Voltage
(Note 10)
V
-
-
VA÷2
-
-
V
kΩ
25
Output Impedance
Filt+ Nominal Voltage
Output Impedance
Maximum allowable DC current source/sink
-
-
-
VA
36
0.01
-
-
-
V
kΩ
mA
9. Power Down Mode is defined as RST = Low, with all clocks and data lines held static at a valid logic
levels.
10. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection
Diagram, Figure 17 on page 14.
DIGITAL CHARACTERISTICS
Parameter
Symbol
VIH
Min
70%
-
Typ
Max
Units
High-Level Input Voltage
Low-Level Input Voltage
(% of VL)
(% of VL)
-
-
-
-
30%
-
V
V
V
VIL
VOH
70%
High-Level Output Voltage at Io = 100 µA
(% of VL)
(% of VL)
VOL
Iin
-
-
-
15%
V
Low-Level Output Voltage at Io =100 µA
Input Leakage Current
-10
+10
µA
10
DS601F2
Confidential Draft
3/11/08
CS5340
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT
(Logic "0" = GND = 0 V; Logic "1" = VL, C = 20 pF)
L
Parameter
MCLK Specifications
MCLK Period
Symbol
Min
Typ
Max
Unit
tclkw
39
78
40
-
-
-
45
1953
60
ns
ns
%
MCLK Pulse Duty Cycle
Master Mode
tmslr
-20
-20
-8
-
-
-
20
20
8
ns
ns
ns
SCLK falling to LRCK
Single-Speed
Double-Speed
Quad-Speed
SCLK falling to SDOUT valid.
SCLK Duty Cycle.
tsdo
-
-
-
-
32
-
ns
%
%
Single-Speed
Double-Speed
50
50
-
-
33
-
%
Quad-Speed
Slave Mode
Single-Speed (Note 11)
LRCK Duty Cycle
40
156
45
10
5
50
-
60
-
%
ns
%
tsclkw
SCLK Period
50
-
55
-
SCLK Duty Cycle
tstp
thld
tslrd
ns
ns
ns
SDOUT valid before SCLK rising
SDOUT valid after SCLK rising
-
-
-20
-
20
SCLK falling to LRCK edge
Double-Speed (Note 11)
LRCK Duty Cycle
40
156
45
10
5
50
-
60
-
%
ns
%
tsclkw
SCLK Period
50
-
55
-
SCLK Duty Cycle
tstp
thld
tslrd
ns
ns
ns
SDOUT valid before SCLK rising
-
-
SDOUT valid after SCLK rising
SCLK falling to LRCK edge.
Quad-Speed (Note 11)
LRCK Duty Cycle
-20
-
20
40
78
29.7
10
5
50
-
60
-
%
ns
%
tsclkw
SCLK Period
33
-
50
-
SCLK Duty Cycle
tstp
thld
tslrd
ns
ns
ns
SDOUT valid before SCLK rising
SDOUT valid after SCLK rising
SCLK falling to LRCK edge.
-
-
-8
-
8
11. For a description of speed modes, please refer to Table on page 15.
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SCLK output
LRCK output
SDOUT
LRCK input
SCLK input
t
t
t
mslr
sclkw
slrd
t
t
t
sdo
stp hld
MSB
MSB-1
MSB
MSB-1
SDOUT
Figure 13. Master Mode, Left-Justified SAI
Figure 14. Slave Mode, Left-Justified SAI
SCLK output
LRCK input
t
t
t
mslr
sclkw
slrd
LRCK output
SDOUT
SCLK input
SDOUT
t
t
t
sdo
stp hld
MSB
MSB
Figure 15. Master Mode, I²S SAI
Figure 16. Slave Mode, I²S SAI
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2. PIN DESCRIPTION
M0
MCLK
VL
SDOUT
GND
VD
SCLK
LRCK
M1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FILT+
REF_GND
VA
AINR
VQ
AINL
RST
Pin Name
#
Pin Description
M0
M1
1
16
Mode Selection (Input) - Determines the operational mode of the device.
MCLK
VL
2
3
Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
Logic Power (Input) - Positive power for the digital input/output.
SDOUT
GND
VD
4
Serial Audio Data Output (Output) - Output for two’s complement serial audio data.
Ground (Input) - Ground reference. Must be connected to analog ground.
Digital Power (Input) - Positive power supply for the digital section.
Serial Clock (Input/Output) - Serial clock for the serial audio interface.
5,14
6
SCLK
7
Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently
active on the serial audio data line.
LRCK
RST
8
9
Reset (Input) - The device enters a low power mode when low.
AINL
AINR
10
12
Analog Input (Input) - The full-scale analog input level is specified in the Analog Charac-
teristics specification table.
Quiescent Voltage (Output) - Filter connection for the internal quiescent
reference voltage.
VQ
11
13
15
VA
Analog Power (Input) - Positive power supply for the analog section.
Positive Voltage Reference (Output) - Positive reference voltage for the internal
sampling circuits.
FILT+
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3. TYPICAL CONNECTION DIAGRAM
3.3V to 5V
+
1.8 V to 5V
µ
1 F
µ
0.1 F
+
µ
µ
1 F
0.1 F
**
3.3V to 5V
+
Ω
5.1
µ
1 F
µ
0.1 F
µ
0.1 F
VA
VD
VL
FILT+
µ ***
+
µ
0.1 F
1 F
REFGND
VQ
µ
0.1 F
1µ
F
+
RST
M0
M1
Power Down
and Mode
Settings
CS5340
VL or GND
*
A/D CONVERTER
10k
Ω
AINL
AINR
Audio Data
Processor
SDOUT
Analog Input Buffer
Figure 21
MCLK
LRCK
Timing Logic
and Clock
SCLK
* Pull-up to VL for I2S
*** Capacitor value affects
Pull-down to GND for LJ low frequency distortion
performance as described
GND
** Resistor may only be
in Section 4.8
used if VD is derived from
VA. If used, do not drive
any other logic from VD
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4. APPLICATIONS
4.1
Single-, Double-, and Quad-Speed Modes
The CS5340 can support output sample rates from 2 kHz to 200 kHz. The proper speed mode can be de-
termined by the desired output sample rate and the external MCLK/LRCK ratio, as shown in Table 1.
MCLK/LRCK
Speed Mode
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
Output Sample Rate Range (kHz)
Ratio
512x
256x
256x
128x
128x
64x*
43 - 50
2 - 50
86 - 100
4 - 100
172 - 200
100 - 200
* Quad-Speed Mode, 64x only available in Master Mode.
Table 1. Speed Modes and the Associated Output Sample Rates (Fs)
4.2
Operation as Either a Clock Master or Slave
The CS5340 supports operation as either a clock master or slave. As a clock master, the LRCK and SCLK
pins are outputs with the left/right and serial clocks synchronously generated on-chip. As a clock slave, the
LRCK and SCLK pins are inputs and require the left/right and serial clocks to be externally generated. The
selection of clock master or slave is made via the Mode pins as shown in Table 2.
M1 (Pin 16) M0 (Pin 1)
MODE
Clock Master, Single-Speed Mode
Clock Master, Double-Speed Mode
Clock Master, Quad-Speed Mode
Clock Slave, All Speed Modes
0
0
1
1
0
1
0
1
Table 2. CS5340 Mode Control
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4.2.1
Operation as a Clock Master
As a clock master, LRCK and SCLK operate as outputs. The left/right and serial clocks are internally de-
rived from the master clock with the left/right clock equal to Fs and the serial clock equal to 64x Fs, as
shown in Figure 18.
Single
Speed
÷ 256
÷ 128
÷ 64
00
Double
Speed
LRCK Output
(Equal to Fs)
01
10
Quad
Speed
÷ 1
÷ 2
0
1
M1 M0
MCLK
Single
Speed
÷ 4
00
Auto-Select
Double
Speed
SCLK Output
÷ 2
÷ 1
01
10
Quad
Speed
Figure 18. CS5340 Master Mode Clocking
4.2.2
Operation as a Clock Slave with Auto-Detect
LRCK and SCLK operate as inputs in clock slave mode. It is recommended that the left/right clock be
synchronously derived from the master clock and must be equal to Fs. It is also recommended that the
serial clock be synchronously derived from the master clock and be equal to 64x Fs to maximize system
performance.
A unique feature of the CS5340 is the automatic selection of either Single-, Double- or Quad-Speed mode
when operating as a clock slave. The auto-mode select feature negates the need to configure the Mode
pins to correspond to the desired mode. The auto-mode selection feature supports all standard audio
sample rates from 2 to 200 kHz. However, there are ranges of non-standard audio sample rates that are
not supported when operating with a fast MCLK (512x, 256x, 128x for Single-, Double-, and Quad-Speed
Modes, respectively). Please refer to Table for supported sample rate ranges.
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4.2.3
Master Clock
The CS5340 requires a Master clock (MCLK) which runs the internal sampling circuits and digital filters.
There is also an internal MCLK divider which is automatically activated based on the speed mode and
frequency of the MCLK. Table 3 shows a listing of the external MCLK/LRCK ratios that are required.
Table 4 lists some common audio output sample rates and the required MCLK frequency. Please note
that not all of the listed sample rates are supported when operating with a fast MCLK (512x, 256x, 128x
for Single-, Double-, and Quad-Speed Modes, respectively).
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
MCLK/LRCK Ratio
256x, 512x
128x, 256x
64x*,128x
* Quad Speed, 64x only available in Master Mode.
Table 3. Master Clock (MCLK) Ratios
SAMPLE RATE (kHz)
MCLK (MHz)
8.192
32
44.1
11.2896
22.5792
12.288
48
24.576
64
8.192
88.2
11.2896
22.5792
12.288
96
24.576
192
12.288
24.576
Table 4. Master Clock (MCLK) Frequencies for Standard Audio Sample Rates
4.3
Serial Audio Interface
The CS5340 supports both I²S and Left-Justified serial audio formats. Upon start-up, the CS5340 will detect
the logic level on SDOUT (pin 4). A 10 kΩ pull-up to VL is needed to select I²S format, and a 10 kΩ pull-
down to GND is needed to select Left-Justified format. Figures 19 and 20 illustrate the I²S and Left-Justified
audio formats. Please see Figures 13 through 16, for more information on the required timing for the two
serial audio interface formats. Also see Application Note AN282 for a detailed discussion of the serial audio
interface formats.
LR CK
Left Channel
R ight Channel
SCLK
SD ATA
23 22
9
8
7
6
5
4
3
2
1
0
23 22
9
8
7
6
5
4
3
2
1
0
23 22
Figure 19. I²S Serial Audio Interface
LRCK
SCLK
Left C hannel
R ight Channel
SD ATA
23 22
9
8
7
6
5
4
3
2
1
0
23 22
9
8
7
6
5
4
3
2
1
0
23 22
Figure 20. Left-Justified Serial Audio Interface
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4.4
4.5
Power-Up Sequence
Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and
configuration pins are stable. It is also recommended that reset be enabled if the analog or digital supplies
drop below the minimum specified operating voltages to prevent power-glitch-related issues.
Analog Connections
The analog modulator samples the input at half of the MCLK frequency, or nominally 6.144 MHz. The digital
filter will reject signals within the stopband of the filter. However, there is no rejection for input signals which
are multiples of the input sampling frequency (n × 6.144 MHz), where n=0,1,2,... Refer to Figure 21 which
shows the suggested filter that will attenuate any noise energy at 6.144 MHz, in addition to providing the
optimum source impedance for the modulators. The use of capacitors which have a large voltage coefficient
(such as general purpose ceramics) must be avoided since these can degrade signal linearity.
634 Ω
VA
470 pF
100 kΩ
C0G
91 Ω
4.7 µF
CS5340 AINx
AINx
2700 pF
100 kΩ
Figure 21. CS5340 Recommended Analog Input Buffer
4.6
4.7
18
Grounding and Power Supply Decoupling
As with any high-resolution converter, achieving optimal performance from the CS5340 requires careful at-
tention to power supply and grounding arrangements. Figure 17 shows the recommended power arrange-
ments, with VA and VL connected to clean supplies. VD, which powers the digital filter, may be run from the
system logic supply or may be powered from the analog supply via a resistor. In this case, no additional
devices should be powered from VD. Decoupling capacitors should be as near to the ADC as possible, with
the low-value ceramic capacitor being the nearest. All signals, especially clocks, should be kept away from
the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decou-
pling capacitors, particularly the 0.01 µF, must be positioned to minimize the electrical path from FILT+ and
REF_GND. Furthermore, all ground pins on CS5340 should be referenced to the same ground reference.
The CDB5340 evaluation board demonstrates the optimum layout and power supply arrangements. To min-
imize digital noise, connect the ADC digital outputs only to CMOS inputs.
Synchronization of Multiple Devices
In systems where multiple ADCs are required, the user can achieve simultaneous sampling if the MCLK and
LRCK signals are the same for all of the CS5340’s in the system. If only one master clock source is needed,
one solution is to place one CS5340 in Master mode, and slave all of the other CS5340’s to the one master.
If multiple master clock sources are needed, a possible solution would be to supply all clocks from the same
external source and time the CS5340 reset with the inactive (falling) edge of MCLK. This will ensure that all
converters begin sampling on the same clock edge.
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CS5340
4.8
Capacitor Size on the Reference Pin (FILT+)
The CS5340 requires an external capacitance on the internal reference voltage pin, FILT+. The size of this
decoupling capacitor will affect the low frequency distortion performance as shown in Figure 22, with larger
capacitor values used to optimize low frequency distortion performance. This plot was taken using the
CDB5340 evaluation platform, with the device running in Single-Speed Mode and VA=VD=VL=5 V.
1 uF
2.2 uF
3.3 uF
4.7 uF
5.6 uF
6.8 uF
10 uF
22 uF
47 uF
100 uF
Figure 22. CS5340 THD+N versus Frequency
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5. PARAMETER DEFINITIONS
Dynamic Range
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with
a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This
technique ensures that the distortion components are below the noise level and do not affect the measure-
ment. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991,
and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.
Total Harmonic Distortion + Noise
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured
at -1 and -20 dBFS as suggested in AES17-1991 Annex A.
Frequency Response
A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at
1 kHz. Units in decibels.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with no signal to the input under test and a full-scale signal applied to the other channel. Units in deci-
bels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full-scale analog input for a full-scale digital output.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
Offset Error
The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.
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CS5340
6. PACKAGE DIMENSIONS
16L TSSOP (4.4 mm BODY) PACKAGE DRAWING
N
D
E11
A2
A
E
∝
A1
b2
e
L
END VIEW
SEATING
PLANE
SIDE VIEW
1
2 3
TOP VIEW
INCHES
NOM
MILLIMETERS
NOM
NOTE
DIM
MIN
MAX
MIN
MAX
A
A1
A2
b
D
E
E1
e
L
--
0.002
0.03346
0.00748
0.193
0.248
0.169
--
--
0.004
0.043
0.006
0.037
0.012
0.201
0.256
0.177
--
--
--
--
1.10
0.15
0.95
0.30
5.10
6.50
4.50
--
0.05
0.85
0.19
4.90
6.30
4.30
--
0.0354
0.0096
0.1969
0.2519
0.1732
0.026 BSC
0.024
0.90
0.245
5.00
6.40
4.40
0.65 BSC
0.60
4°
2,3
1
1
0.020
0°
0.028
8°
0.50
0°
0.70
8°
µ
4°
JEDEC #: MO-153
Controlling Dimension is Millimeters
1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold
mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.
2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be
0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not re-
duce dimension “b” by more than 0.07 mm at least material condition.
3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
THERMAL CHARACTERISTICS
Parameter
Allowable Junction Temperature
Symbol
Min
Typ
-
Max
135
-
Unit
°C
°C/W
-
-
Junction to Ambient Thermal Impedance
θJA
75
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7. ORDERING INFORMATION
Product
Description
Package Pb-Free
Grade
Temp Range Container
Order #
CS5340-CZZ
Bulk
101 dB, 192 kHz, Multi-Bit
Audio A/D Converter
CS5340
16-TSSOP
YES
Commercial -10° to +70° C
Automotive -40° to +85° C
Tape & Reel CS5340-CZZR
Bulk
Tape & Reel CS5340-DZZR
CDB5340
CS5340-DZZ
101 dB, 192 kHz, Multi-Bit
Audio A/D Converter
CS5340
16-TSSOP
-
YES
-
CDB5340 CS5340 Evaluation Board
-
-
-
8. REVISION HISTORY
Release
Changes
Remove CS5340-CZ from Ordering Information
Redefine Serial Audio Port Switching Characteristics
Correct dimension “e” under Package Dimensions
Update Output Sample Rate Range
PP3
Update maximum current and power specifications
Update Filt+ output impedance specification
F1
F2
Reduced minimum sample rate to 4 kHz for Double-Speed Mode 128x in Table 1 on page 15
Updated Legal Text
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find the one nearest to you, go to www.cirrus.com.
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
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CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY
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CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO
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Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
22
DS601F2
相关型号：
CS5341-CZ
ADC, Delta-Sigma, 24-Bit, 1 Func, 2 Channel, Serial Access, PDSO16, 4.40 MM, MO-153, TSSOP-16
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