CDB4329_技术文档

CS4329

20-Bit, Stereo D/A Converter for Digital Audio

Features

Description

The CS4329 is a complete stereo digital-to-analog out-

put system. In addition to the traditional D/A function, the

CS4329 includes a digital interpolation filter followed by

an 128X oversampled delta-sigma modulator. The mod-

ulator output controls the reference voltage input to an

ultra-linear analog low-pass filter. This architecture al-

lows for infinite adjustment of sample rate between 1 and

50 kHz while maintaining linear phase response simply

by changing the master clock frequency.

20-Bit Conversion

115 dB Signal-to-Noise-Ratio (EIAJ)

Complete Stereo DAC System

- 128X Interpolation Filter

- Delta-Sigma DAC

- Analog Post Filter

106 dB Dynamic Range

Low Clock Jitter Sensitivity

Filtered Line-Level Outputs

- Linear Phase Filtering

The CS4329 also includes an extremely flexible serial

port utilizing mode select pins to support multiple inter-

face formats.

- Zero Phase Error Between Channels

Adjustable System Sampling Rates

- including 32 kHz, 44.1 kHz & 48 kHz

The master clock can be either 256, 384, or 512 times

the input sample rate, supporting various audio

environments.

Digital De-emphasis for 32 kHz, 44.1 kHz, &

48 kHz

Pin-compatible with the CS4390

ORDERING INFORMATION

CS4329-KP -10° to 70° C 20-pin Plastic DIP

CS4329-KS -10° to 70° C 20-pin Plastic SSOP

CDB4329

Evaluation Board

I

DIF0 DIF1 DIF2

DEM0

1

DEM1

2

VA

3

VD

6

20

19

12

7

9

LRCK

SCLK

Serial Input

Interface

De-emphasis

Voltage Reference

MUTE_L

16

10

SDATA

AOUTL+

18

Analog

Low-Pass

Filter

Delta-Sigma

Modulator

Interpolator

DAC

AOUTL-

17

AOUTR+

14

AUTO_MUTE 11

Analog

Low-Pass

Filter

Delta-Sigma

Modulator

AOUTR-

13

5

8

4

15

DGND

MCLK

AGND

MUTE_R

Cirrus Logic, Inc.

Copyright Cirrus Logic, Inc. 1998

Crystal Semiconductor Products Division

P.O. Box 17847, Austin, Texas 78760

(512) 445 7222 FAX: (512) 445 7581

http://www.crystal.com

APR ‘98

DS153F1

1

CS4329

ANALOG CHARACTERISTICS (T_A= 25°C; Full-Scale Differential Output Sine wave, 997 Hz; Fs =

48 kHz; Input Data = 20 Bits; SCLK = 3.072 MHz; MCLK = 12.288 MHz; R_L= 20 kΩ differential; VD = VA = 5 V;

Logic "1" = VD; Logic "0" = DGND; Measurement Bandwidth is 10 Hz to 20 kHz, unweighted unless otherwise

specified.)

Parameter

Specified Temperature Operating Range

Dynamic Performance

Symbol

Min

Typ

Max

Unit

T_A

-10

-

70

°C

Dynamic Range

20-Bit

18-Bit

16-Bit

(Note 1)

(A-Weighted)

98

101

-

103

106

101

104

94

-

dB

(A-Weighted)

96

Total Harmonic Distortion + Noise

(Note 1) THD+N

0 dB

-20 dB

-60 dB

0 dB

-20 dB

-60 dB

0 dB

20-Bit

18-Bit

16-Bit

-90

-78

-38

-

-97

-83

-43

-96

-81

-41

-93

-74

-34

-

dB

-20 dB

-60 dB

Idle Channel Noise / Signal-to-Noise-Ratio

Interchannel Isolation (1 kHz)

Combined Digital and Analog Filter Characteristics

(Note 2)

-

115

-

dBFS

dB

-110

Frequency Response 10 Hz to 20 kHz

Deviation from linear phase

Passband: to -0.1 dB corner

Passband Ripple

(Note 3)

-

±0.1

-

dB

deg

kHz

dB

-

±0.5

-

(Note 3)

0

-

21.77

-

26.23

75

-

±0.001

StopBand

(Note 3)

(Note 4)

-

kHz

dB

StopBand Attenuation

Group Delay

-

25/Fs

s

De-emphasis Error (referenced to 1 kHz)

Fs = 32 kHz

Fs = 44.1 kHz

Fs = 48 kHz

-

+0.3/-0.3

+0.2/-0.4

+0.1/-0.45

dB

dc Accuracy

Interchannel Gain Mismatch

Gain Error

-

0.1

±2

-

±5

-

dB

%

Gain Drift

200

ppm/°C

Power Supplies

Power Supply Current:

Normal Operation

Power-down

I_A

I_D

I_A+I_D

-

30

12

42

-

45

-

mA

µA

500

Power Dissipation

Normal Operation

Power-down

-

185

2.5

22.5

-

mW

Power Supply Rejection Ratio (1 kHz)

PSRR

-

60

-

dB

2

DS153F1

CS4329

ANALOG CHARACTERISTICS (CONTINUED)

Parameter

Symbol

Min

Typ

Max

Unit

Analog Output

Differential Full Scale Output Voltage

Output Common Mode Voltage

Differential Offset

(Note 5)

1.90

2.0

2.2

3

2.10

-

Vrms

V

-

15

-

mV

kΩ

pf

AC Load Resistance

R

C

4

-

L

Load Capacitance

-

100

L

Notes: 1. Triangular PDF Dithered Data

2. AUTO-MUTE active. See parameter definitions

3. The passband and stopband edges scale with frequency. For input sample rates, Fs, other than 48 kHz,

the passband edge is 0.4535×Fs and the stopband edge is 0.5465×Fs.

4. Group Delay for Fs=48 kHz 25/48 kHz=520 µs

5. Specified for a fully differential output ±((AOUT+)-(AOUT-)). See Figure 12.

SWITCHING CHARACTERISTICS (T_A= -10 to 70°C; Logic 0 = AGND = DGND; Logic 1 = VD = VA = 5.25

to 4.75 Volts; C_L= 20 pF)

Parameter

MCLK / LRCK = 512

Symbol

Min

1

Typ

Max

Unit

kHz

ns

Input Sample Rate

Fs

-

50

-

MCLK Pulse Width High

MCLK Pulse Width Low

MCLK Pulse Width High

MCLK Pulse Width Low

MCLK Pulse Width High

MCLK Pulse Width Low

External SCLK Mode

SCLK Pulse Width Low

SCLK Pulse Width High

SCLK Period

10

21

31

32

MCLK / LRCK = 512

MCLK / LRCK = 384

MCLK / LRCK = 256

-

ns

-

ns

-

ns

-

ns

-

ns

t

20

-

ns

sclkl

t

sclkh

1

sclkw

-------------------

128(Fs)

SCLK rising to LRCK edge delay

t

20

-

ns

slrd

SCLK rising to LRCK edge setup time

SDATA valid to SCLK rising setup time

SCLK rising to SDATA hold time

Internal SCLK Mode

t

20

slrs

t

20

sdlrs

t

20

sdh

1

SCLK Period

SCLK / LRCK = 64

t

-

ns

sclkw

----------------

64(Fs)

1

SDATA valid to SCLK rising setup time

SCLK rising to SDATA hold time MCLK / LRCK = 256 or 512

SCLK rising to SDATA hold time MCLK / LRCK = 384

t

sdlrs

-------------------

+ 10

512(Fs)

t

1

sdh

-------------------

+ 15

512(Fs)

t

1

sdh

-------------------

384(Fs)

DS153F1

3

CS4329

LRCK

t

slrs

t

sclkl sclkh

slrd

SCLK

t

sdh

t

sdlrs

SDATA

External Serial Mode Input Timing

LRCK

SDATA

t

sclkw

t

sdlrs sdh

*INTERNAL SCLK

Internal Serial Mode Input Timing

* The SCLK pin must be terminated to ground.

The SCLK pulses shown are internal to the CS4329.

4

DS153F1

CS4329

DIGITAL CHARACTERISTICS (T = 25°C; VD = 5 V ±5%)

A

Parameter

Symbol

Min

Typ

Max

Unit

V

High-Level Input Voltage

Low-Level Input Voltage

Input Leakage Current

V

2.0

-

0.8

±10.0

-

IH

V

-

V

IL

V

-

µA

pF

in

Digital Input Capacitance

10

ABSOLUTE MAXIMUM RATINGS (AGND = 0 V, all voltages with respect to ground.)

Parameter

Symbol

Min

Max

Unit

DC Power Supply:

Positive Analog

Positive Digital

|VA - VD|

VA

VD

-0.3

0.0

6.0

0.4

V

Input Current, Any Pin Except Supplies

Digital Input Voltage

I

-

±10

(VD)+0.4

125

mA

V

in

V

-0.3

-55

-65

IND

Ambient Operating Temperature (power applied)

Storage Temperature

T

°C

A

T

150

stg

WARNING: Operation at or beyond these limits may result in permanent damage to the device.Normal operation is

not guaranteed at these extremes.

RECOMMENDED OPERATING CONDITIONS (DGND = 0V; all voltages with respect to ground)

Parameter

Symbol

Min

Typ

Max

Unit

DC Power Supply:

Positive Digital

Positive Analog

|VA - VD|

VD

VA

4.75

-

5.0

-

5.25

0.4

V

DS153F1

5

CS4329

Ω

10

+5V

Analog

µ

1 F

µ

µ µ

1 F 0.1 F

+

0.1 F

+

6

3

VD

VA

20

19

12

DIF0

DIF1

DIF2

Mode

Select

17

18

AOUTL-

AOUTL+

CS4329

Analog

Conditioning

7

9

LRCK

SCLK*

SDATA

10

1

Audio

Data

DEM0

DEM1

2

Processor

13

14

AOUTR-

AOUTR+

15

16

11

MUTE_R

MUTE_L

Analog

Conditioning

AUTO_MUTE

8

MCLK

DGND AGND

External Clock

5

4

* SCLK must be connected to DGND

for operation in Internal SCLK Mode

Figure 1. Typical Connection Diagram

6

DS153F1

CS4329

of the input signal at multiples of 128× the input

sample rate. These images are removed by the ex-

ternal analog filter.

GENERAL DESCRIPTION

The CS4329 is a complete stereo digital-to-analog

system including 128× digital interpolation, fourth-

order delta-sigma digital-to-analog conversion,

128× oversampled one-bit delta-sigma modulator

and analog filtering. This architecture provides a

high insensitivity to clock jitter. The DAC converts

digital data at any input sample rate between 1 and

50 kHz, including the standard audio rates of 48,

44.1 and 32 kHz.

Delta-Sigma Modulator

The interpolation filter is followed by a fourth-or-

der delta-sigma modulator which converts the 24-

bit interpolation filter output into 1-bit data at

128× Fs.

Switched-Capacitor Filter

The primary purpose of using delta-sigma modula-

tion techniques is to avoid the limitations of laser

trimmed resistive DAC architectures by using an

inherently linear 1-bit DAC. The advantages of a 1-

bit DAC include: ideal differential linearity, no dis-

tortion mechanisms due to resistor matching errors

and no linearity drift over time and temperature due

to variations in resistor values.

The delta-sigma modulator is followed by a digital-

to-analog converter which translates the 1-bit data

into a series of charge packets. The magnitude of

the charge in each packet is determined by sam-

pling of a voltage reference onto a switched capac-

itor, where the polarity of each packet is controlled

by the 1-bit signal. This technique greatly reduces

the sensitivity to clock jitter and is a major im-

provement over earlier generations of 1-bit digital-

to-analog converters where the magnitude of

charge in the D-to-A process is determined by

switching a current reference for a period of time

defined by the master clock.

Digital Interpolation Filter

The digital interpolation filter increases the sample

rate by a factor of 4 and is followed by a 32× digital

sample-and hold to effectively achieve a 128× in-

terpolation filter. This filter eliminates images of

the baseband audio signal which exist at multiples

of the input sample rate, Fs. This allows for the se-

lection of a less complex analog filter based on out-

of-band noise attenuation requirements rather than

anti-image filtering. Following the interpolation

filter, the resulting frequency spectrum has images

The CS4329 incorporates a differential output to

maximize the output level to minimize the amount

of gain required in the output analog stage. The dif-

ferential output also allows for the cancellation of

common mode errors in the differential to singled-

ended converter.

Analog

Low-Pass

Filter

AOUTL+

Delta-Sigma

Interpolator

DAC

Modulator

AOUTL-

Figure 2. Block Diagram

DS153F1

7

CS4329

in 2's-complement format with the MSB-first in all

seven formats.

SYSTEM DESIGN

Master Clock

Formats 0, 1 and 2 are shown in Figure 3. The audio

data is right-justified, LSB aligned with the trailing

edge of LRCK, and latched into the serial input

data buffer on the rising edge of SCLK. Formats 0,

1 and 2 are 16, 18 and 20-bit versions and differ

only in the number of data bits required.

The Master Clock, MCLK, is used to operate the

digital interpolation filter and the delta-sigma mod-

ulator. MCLK must be either 256×, 384× or 512×

the desired Input Sample Rate, Fs. Fs is the fre-

quency at which digital audio samples for each

channel are input to the DAC and is equal to the

LRCK frequency. The MCLK to LRCK frequency

ratio is detected automatically during the initializa-

tion sequence by counting the number of MCLK

transitions during a single LRCK period. Internal

dividers are then set to generate the proper clocks

for the digital filter, delta-sigma modulator and

switched-capacitor filter. LRCK must be synchro-

nous with MCLK. Once the MCLK to LRCK fre-

quency ratio has been detected, the phase and

frequency relationship between the two clocks

must remain fixed. If during any LRCK this rela-

tionship is changed, the CS4329 will reset. Table 1

illustrates the standard audio sample rates and the

required MCLK frequencies.

Formats 3 and 4 are 20-bit left justified, MSB

aligned with the leading edge of LRCK, and are

identical with the exception of the SCLK edge used

to latch data. Data is latched on the falling edge of

SCLK in Format 3 and the rising edge of SCLK in

Format 4. Both formats will support 16 and 18-bit

inputs if the data is followed by four or two zeros to

simulate a 20-bit input as shown in Figures 4 and 5.

A very small offset will result if the 18 or 16-bit

data is followed by static non-zero data.

2

Formats 5 and 6 are compatible with the I S serial

data protocol and are shown in Figures 6 and 7. No-

tice that the MSB is delayed 1 period of SCLK fol-

lowing the leading edge of LRCK and LRCK is

inverted compared to the previous formats. Data is

latched on the rising edge of SCLK. Format 5 is 16-

Fs

(kHz)

MCLK (MHz)

384x

256x

512x

2

bit I S while Format 6 is 20-bit I S. 18-bit I S can

be implemented in Format 6 if the data is followed

by two zeros to simulate a 20-bit input as shown in

Figure 7. A very small offset will result if the 18-bit

data is followed by static non-zero data.

32

44.1

48

8.1920

11.2896

12.2880

16.9344

18.4320

16.3840

22.5792

24.5760

Table 1. Common Clock Frequencies

Serial Data Interface

DIF2

DIF1

DIF0

Format

Figure

The Serial Data interface is accomplished via the

serial data input, SDATA, serial data clock, SCLK,

and the left/right clock, LRCK. The CS4329 sup-

ports seven serial data formats which are selected

via the digital input format pins DIF0, DIF1 and

DIF2. The different formats control the relation-

ship of LRCK to the serial data and the edge of

SCLK used to latch the data into the input buffer.

Table 2 lists the seven formats, along with the asso-

ciated figure number. The serial data is represented

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

3

4

5

6

7

-

Calibrate

Table 2. Digital Input Formats

8

DS153F1

CS4329

Serial Clock

De-Emphasis

The serial clock controls the shifting of data into

the input data buffers. The CS4329 supports both

external and internal serial clock generation modes.

Implementation of digital de-emphasis requires re-

configuration of the digital filter to maintain the fil-

ter response shown in Figure 8 at multiple sample

rates. The CS4329 is capable of digital de-empha-

sis for 32, 44.1 or 48kHz sample rates. Table 3

shows the de-emphasis control inputs for DEM 0

and DEM 1.

External Serial Clock

The CS4329 will enter the external serial clock

mode if 15 or more high\low transitions are detect-

ed on the SCLK pin during any phase of the LRCK

period. When this mode is enabled, internal serial

clock mode cannot be accessed without returning

to the power down mode.

DEM 1

DEM 0

De-emphasis

32 kHz

0

1

0

1

0

1

44.1 kHz

48 kHz

OFF

Internal Serial Clock

In the Internal Serial Clock Mode, the serial clock

is internally derived and synchronous with MCLK.

The internal SCLK / LRCK ratio is always 64 and

operation in this mode is identical to operation with

an external serial clock synchronized with LRCK.

The SCLK pin must be connected to DGND for

proper operation.

Table 3. De-Emphasis Filter Selection

Gain

dB

µ

T1=50 s

0dB

The internal serial clock mode is advantageous in

that there are situations where improper serial

clock routing on the printed circuit board can de-

grade system performance. The use of the internal

serial clock mode simplifies the routing of the

printed circuit board by allowing the serial clock

trace to be deleted and avoids possible interference

effects.

T2 = 15µs

-10dB

F1

3.183 kHz

F2

Frequency

10.61 kHz

Figure 8. De-emphasis Filter Response

Initialization, Calibration and Power-Down

Mute Functions

Upon initial power-up, the DAC enters the power-

down mode. The interpolation filters and delta-sig-

ma modulators are reset, and the internal voltage

reference, one-bit D/A converters and switched-ca-

pacitor low-pass filters are powered down. The de-

vice will remain in the power-down mode until

MCLK and LRCK are presented. Once MCLK and

LRCK are detected, MCLK occurrences are count-

ed over one LRCK period to determine the

MCLK/LRCK frequency ratio. The phase and fre-

quency relationship between the two clocks must

remain fixed. If during any LRCK this relationship

The CS4329 includes an auto-mute function which

will initiate a mute if 8192 consecutive 0’s or 1’s are

input on both the Left and Right channels. The

mute will be released when non-static input data is

applied to the DAC. The auto-mute function is use-

ful for applications, such as compact disk players,

where the idle channel noise must be minimized.

This feature is active only if the AUTO_MUTE pin

is low and is independent of the status of MUTE_L

and MUTE_R. Either channel can also be muted

instantaneously with the MUTE_L or MUTE_R.

DS153F1

11

CS4329

is changed, the CS4390 will reset. Power is applied

to the internal voltage reference, the D/A convert-

ers, switched-capacitor filters and the DAC will

then enter a calibration mode to properly set the

common mode bias voltage and minimize the dif-

ferential offset. This initialization and calibration

sequence requires approximately 2700 cycles of

LRCK.

0

-10

-20

-30

-40

-50

-60

-70

-80

A offset calibration can also be invoked by taking

the Format select pins, DIF0, DIF1 and DIF2, to a

logic 1 as shown in Table 2. During calibration, the

differential outputs are shorted together and the

common-mode voltage appears at the output with

approximately an 8 kohm output impedance. Fol-

lowing calibration, the analog output impedance

becomes less than 10 ohms and the common mode

voltage will move to approximately 2.2 V .

-90

-100

0.7

0.0 0.1 0.2 0.3 0.4 0.5 0.6

Frequency (x Fs)

0.8 0.9 1.0

Figure 9. CS4329 Combined Digital and Analog Filter

Stopband Rejection

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

The CS4329 will enter the power-down mode,

within 1 period of LRCK, if either MCLK or

LRCK is removed. The initialization sequence, as

described above, occurs when MCLK and LRCK

are restored.

Combined Digital and Analog Filter

Response

0.45

0.48

0.51

0.54

0.57

0.60

Frequency (x Fs)

The frequency response of the combined analog

switched-capacitor and digital filters is shown in

Figures 9, 10 and 11. The overall response is clock

dependent and will scale with Fs. Note that the re-

sponse plots have been normalized to Fs and can be

de-normalized by multiplying the X-axis scale by

Fs, such as 48 kHz.

Figure 10. CS4329 Combined Digital and Analog

Filter

0

-1

-2

-3

-4

-5

Analog Output and Filtering

The analog output should be operated in a differen-

tial mode which allows for the cancellation of com-

mon mode errors including noise, distortion and

offset voltage. Each output will produce a nominal

2.83 Vpp (1 Vrms) output for a full scale digital in-

put which equates to a 5.66 Vpp (2Vrms) differen-

tial signal as shown in Figure 12.

-6

-7

-8

-9

-10

0.46

0.47

0.48

0.49

0.50

0.51

0.52

Frequency (x Fs)

Figure 11. Combined Digital and Analog Filter

12

DS153F1

CS4329

Figure 13 displays the CS4329 output noise spec- Figure 1 shows the recommended power arrange-

trum. The noise beyond the audio band can be fur-

ther reduced with additional analog filtering. The

applications note "Design Notes for a 2-Pole Filter

with Differential Input " discusses the second-order

Butterworth filter and differential to signal-ended

converter which was implemented on the CS4329

evaluation board, CDB4329. The CS4329 filter is a

linear phase design and does not include phase or

amplitude compensation for an external filter.

ments with VA connected to a clean +5volt supply.

VD should be derived from VA through a 10 Ω re-

sistor. VD should not be used to power additional

digital circuitry. All mode pins which require VD

should be connected to pin 6 of the CS4329. All

mode pins which require DGND should be con-

nected to pin 5 of the CS4329. Pins 4 and 5, AGND

and DGND, should be connected together at the

CS4329. DGND for the CS4329 should not be con-

Therefore, the DAC system phase and amplitude fused with the ground for the digital section of the

response will be dependent on the external analog

circuitry.

system. The CS4329 should be positioned over the

analog ground plane near the digital/analog ground

plane split. The analog and digital ground planes

must be connected elsewhere in the system. The

CS4329 evaluation board, CDB4329, demonstrates

this layout technique. This technique minimizes

digital noise and insures proper power supply

matching and sequencing. Decoupling capacitors

should be located as near to the CS4329 as possi-

ble.

CS4329

(2.2 + 1.4)V

2.2V

AOUT+

AOUT-

(2.2 - 1.4)V

(2.2 + 1.4)V

2.2V

(2.2 - 1.4)V

Full Scale Input level= (AIN+) - (AIN-)= 5.66 Vpp

Performance Plots

Figure 12. Full Scale Input Voltage

The following collection of CS4329 measurement

plots were taken from the CDB4329 evaluation

board using the Audio Precision Dual Domain Sys-

tem Two.

0

-20

-40

-60

Figure 14 shows the frequency response at a

48 kHz sample rate. The response is flat to 20 kHz

+/-0.1 dB as specified.

-80

-100

-120

-140

Figure 15 shows THD+N versus signal amplitude

for a 1 kHz 20-bit dithered input signal. Notice that

the there is no increase in distortion as the signal

level decreases. This indicates very good low-level

linearity, one of the key benefits of delta-sigma

digital to analog conversion.

-160

0

.25 .50 .75 1.00 1.25 1.50 1.75 2.00 2.25 2.50

Frequency (x Fs)

Figure 13. CS4329 Output Noise Spectrum

Figure 16 shows a 16 k FFT of a 1 kHz full-scale

input signal. The signal has been filtered by a notch

filter within the System Two to remove the funda-

mental component of the signal. This minimizes

the distortion created in the analyzer analog-to-dig-

ital converter. This technique is discussed by Audio

Grounding and Power Supply Decoupling

As with any high resolution converter, the CS4329

requires careful attention to power supply and

grounding arrangements to optimize performance.

DS153F1

13

CS4329

Precision in the 10th anniversary addition of AU-

DIO.TST.

level inputs. The gradual shift of the plot away

from zero at signals levels < -110 dB is caused by

the background noise starting to dominate the mea-

surement.

Figure 17 shows a 16 k FFT of a 1 kHz -20 dBFS

input signal. The signal has been filtered by a notch

filter within the System Two to remove the funda-

mental component of the signal.

Figure 18 shows a 16 k FFT of a 1 kHz -60 dBFS

input signal.

Figure 19 shows the fade-to-noise linearity. The in-

put signal is a dithered 20-bit 500 Hz sine wave

which fades from -60 to -120 dBFS. During the

fade, the output from the CS4329 is measured and

compared to the ideal level. Notice the very close

tracking of the output level to the ideal, even at low

14

DS153F1

CS4329

-60

-65

+1

+0.8

+0.6

+0.4

+0.2

+0

-70

-75

-80

-85

d

B

r

d

B

r

-90

A

-95

-0.2

-0.4

-0.6

-0.8

-1

-100

-105

-110

-115

-120

-60

-50

-40

-30

-20

-10

+0

20

50

100 200

500 1k

Hz

2k

5k

10k 20k

dBFS

Figure 14. Frequency Response

Figure 15. THD+N vs. Amplitude

+0

-10

-20

-30

-40

-50

-60

-10

-20

-30

-40

-50

-60

d

B

r

-70

-80

d

B

r

-80

A

-90

A

-100

-110

-120

-130

-140

-150

-160

-100

-110

-120

-130

-140

-150

-160

2.5k

5k

7.5k

10k

Hz

12.5k

15k

17.5k 20k

2.5k

5k

7.5k

10k

Hz

12.5k

15k

17.5k 20k

Figure 16. 0 dBFS FFT

Figure 17. -20 dBFS FFT

+0

+5

+4

+3

+2

+1

-0

-10

-20

-30

-40

-50

-60

d

B

r

d

B

r

-70

-80

A

-1

-90

-100

-110

-120

-130

-140

-150

-2

-3

-4

-5

-120

-100

-80

-60

dBFS

-40

-20

+0

2k

4k

6k

8k

10k 12k 14k 16k 18k 20k

Hz

Figure 18. -60 dBFS FFT

Figure 19. Fade-to-Noise Linearity

DS153F1

15

CS4329

PIN DESCRIPTIONS

PDIP and SSOP

DEM0

DEM1

VA

AGND

DGND

VD

DIF0

DIF11

AOUTL+

AOUTL-

MUTE_L

1

2

3

4

5

6

20

19

18

17

16

15 MUTE_R

7

8

9

10

14

13

12

11

LRCK

MCLK

SCLK

SDATA

AOUTR+

AOUTR-

DIF2

AUTO-MUTE

Power Supply Connections

VA - Positive Analog Power, PIN 3.

Positive analog supply. Nominally +5 volts.

VD - Positive Digital Power, PIN 6.

Positive supply for the digital section. Nominally +5 volts.

AGND - Analog Ground, PIN 4.

Analog ground reference.

DGND - Digital Ground, PIN 5.

Digital ground for the digital section.

Analog Outputs

AOUTR+,AOUTR- - Differential Right Channel Analog Outputs, PIN 14, PIN 13.

Analog output connections for the Right channel differential outputs. Nominally 2 Vrms

(differential) for full-scale digital input signal.

AOUTL+,AOUTL- - Differential Left Channel Analog Outputs, PIN 18, PIN 17.

Analog output connections for the Left channel differential outputs. Nominally 2 Vrms

(differential) for full-scale digital input signal.

16

DS153F1

CS4329

Digital Inputs

MCLK - Clock Input, PIN 8.

The frequency must be either 256×, 384× or 512× the input sample rate (Fs).

LRCK - Left/Right Clock, PIN 7.

This input determines which channel is currently being input on the Serial Data Input pin,

SDATA. The format of LRCK is controlled by DIF0, DIF1 and DIF2.

SCLK - Serial Bit Input Clock, PIN 9.

Clocks the individual bits of the serial data in from the SDATA pin. The edge used to latch

SDATA is controlled by DIF0, DIF1 and DIF2.

SDATA - Serial Data Input, PIN 10.

Two's complement MSB-first serial data of either 16, 18 or 20 bits is input on this pin. The

data is clocked into the CS4329 via the SCLK clock and the channel is determined by the

LRCK clock. The format for the previous two clocks is determined by the Digital Input Format

pins, DIF0, DIF1 and DIF2.

DIF0, DIF1, DIF2 - Digital Input Format, PINS 20, 19, 12

These three pins select one of seven formats for the incoming serial data stream. These pins set

the format of the SCLK and LRCK clocks with respect to SDATA. The formats are listed in

Table 2.

DEM0, DEM1 - De-Emphasis Select, PINS 1, 2.

Controls the activation of the standard 50/15us de-emphasis filter for either 32, 44.1 or 48 kHz

sample rates.

AUTO-MUTE - Automatic Mute on Zero-Data, PIN 11.

When Auto-Mute is low the analog outputs are muted following 8192 consecutive LRCK

cycles of static 0 or 1 data. Mute is canceled with the return of non-static input data.

MUTE_R , MUTE_L Mute, PINS 15, 16.

MUTE_L low activates a muting function for the Left channel. MUTE_R low activates a

muting function for the Right channel.

DS153F1

17

CS4329

PARAMETER DEFINITIONS

Dynamic Range

The ratio of the full scale rms value of the signal to the rms sum of all other spectral

components over the specified bandwidth. Dynamic range is a signal-to-noise measurement

over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting

measurement to refer the measurement to full scale. This technique ensures that the distortion

components are below the noise level and do not effect the measurement. This measurement

technique has been accepted by the Audio Engineering Society, AES17-1991, and the

Electronic Industries Association of Japan, EIAJ CP-307.

Total Harmonic Distortion + Noise

The ratio of the rms value of the signal to the rms sum of all other spectral components over

the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components.

Expressed in decibels.

Idle Channel Noise / Signal-to-Noise-Ratio

The ratio of the rms analog output level with 1kHz full scale digital input to the rms analog

output level with all zeros into the digital input. Measured A-weighted over a 10 Hz to 20 kHz

bandwidth. Units in decibels. This specification has been standardized by the Audio

Engineering Society, AES17-1991, and referred to as Idle Channel Noise. This specification has

also been standardized by the Electronic Industries Association of Japan, EIAJ CP-307, and

referred to as Signal-to-Noise-Ratio.

Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel at the

converter’s output with all zeros to the input under test and a full-scale signal applied to the

other channel. Units in decibels.

Frequency Response

A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude

response at 1 kHz. Units in decibels.

De-Emphasis Error

A measure of the difference between the ideal de-emphasis filter and the actual de-emphasis

filter response. Measured from 10 Hz to 20 kHz relative to 1 kHz. Units in decibels.

Interchannel Gain Mismatch

The gain difference between left and right channels. Units in decibels.

Gain Error

The deviation from the nominal full scale analog output for a full scale digital input.

Gain Drift

The change in gain value with temperature. Units in ppm/°C.

18

DS153F1

CS4329

PACKAGE DIMENSIONS

20L SSOP PACKAGE DRAWING

N

D

E1¹

A2

A

E

A1

b²

e

L

END VIEW

SEATING

PLANE

SIDE VIEW

1

2

3

TOP VIEW

INCHES

MILLIMETERS

MIN MAX

NOTE

DIM

A

MIN

--

MAX

0.084

0.010

0.074

0.015

0.295

0.323

0.220

0.030

0.041

8°

--

2.13

0.25

1.88

0.38

7.50

8.20

5.60

0.75

1.03

8°

A1

A2

b

D

E

E1

e

L

0.002

0.064

0.009

0.272

0.291

0.197

0.022

0.025

0°

0.05

1.62

0.22

6.90

7.40

5.00

0.55

0.63

0°

2,3

1

Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold

mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per

side.

2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be

0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not

reduce dimension “b” by more than 0.07 mm at least material condition.

3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.

DS153F1

19

CS4329

20 PIN PLASTIC (PDIP) PACKAGE DRAWING

eB

D

eC

E

E1

1

A2

A1

A

SEATING

PLANE

TOP VIEW

L

c

e

eA

b1

b

SIDE VIEW

BOTTOM VIEW

INCHES

MILLIMETERS

DIM

A

A1

A2

b

b1

c

D

E

E1

e

eA

eB

eC

L

MIN

MAX

0.210

0.025

0.195

0.022

0.070

0.014

1.060

0.325

0.280

0.110

0.320

0.430

0.060

0.150

15°

MIN

0.00

0.38

2.92

0.36

1.14

0.20

24.89

7.62

6.10

2.29

7.11

7.62

0.00

2.92

0°

MAX

5.33

0.64

4.95

0.56

1.78

0.36

26.92

8.26

7.11

2.79

8.13

10.92

1.52

3.81

15°

0.000

0.015

0.115

0.014

0.045

0.008

0.980

0.300

0.240

0.090

0.280

0.300

0.000

0.115

0°

20

DS153F1

CDB4329

CDB4390

Evaluation Board for CS4329 and CS4390

Features

Description

The CDB4329/90 evaluation board is an excellent

means for quickly evaluating the CS4329 or CS4390 24-

bit, stereo D/A converter. Evaluation requires an analog

signal analyzer, a digital signal source and a power sup-

ply. Analog outputs are provided via RCA connectors for

both channels.

Demonstrates recommended layout

and grounding arrangements

CS8412 Receives AES/EBU, S/PDIF,

& EIAJ-340 Compatible Digital Audio

Digital and Analog Patch Areas

Requires only a digital signal source

and power supplies for a complete Digital-to-

Analog-Converter system

The CS8412 digital audio receiver I.C. provides the sys-

tem timing necessary to operate the CS4329/90 and will

accept AES/EBU, S/PDIF, and EIAJ-340 compatible

audio data. The evaluation board may also be config-

ured to accept external timing signals for operation in a

user application during system development.

ORDERING INFO

CDB4329

CDB4390

I

I/O for

Clocks

and Data

CS8412

Digital

Audio

CS4329

Analog

or

CS4390

Filter

Interface

This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.

Preliminary Product Information

Cirrus Logic, Inc.

Crystal Semiconductor Products Division

P.O. Box 17847, Austin, Texas 78760

(512) 445 7222 FAX: (512) 445 7581

http://www.crystal.com

NOV ‘97

DS153DB3

21

CDB4329 CDB4390

control for the CS4329/90 will be erroneous and

produce an incorrect audio output.

CDB4329/90 SYSTEM OVERVIEW

The CDB4329/90 evaluation board is an excellent

means of quickly evaluating the CS4329/90. The

CS8412 digital audio interface receiver provides an

easy interface to digital audio signal sources in-

cluding the majority of digital audio test equip-

ment. The evaluation board also allows the user to

supply clocks and data through a 10-pin header for

system development.

Encoded sample frequency information can be dis-

played provided a proper clock is being applied to

the FCK pin of the CS8412. When an LED is lit,

this indicates a "1" on the corresponding pin locat-

ed on the CS8412. When an LED is off, this indi-

cates a "0" on the corresponding pin. Neither the L

or R option of CSLR/FCK should be selected if the

FCK pin is being driven by a clock signal.

The CDB4329/90 schematic has been partitioned

into 8 schematics shown in Figures 2 through 9.

Each partitioned schematic is represented in the

system diagram shown in Figure 1. Notice that the

system diagram also includes the interconnections

between the partitioned schematics.

The evaluation board has been designed such that

the input can be either optical or coax, Figure 8. It

is not necessary to select the active input. However,

both inputs can not be driven simultaneously.

Data Format

CS4329/90 Digital to Analog Converter

The CS4329/90 must be configured to be compati-

ble with the incoming data and can be set with

DIF0, DIF1, and DIF2. The CS8412 data format

can be set with the M0, M1, M2 and M3. There are

several data formats which the CS8412 can pro-

duce that are compatible with CS4329/90. Refer to

Table 2 for one possibility.

A description of the CS4329 or CS4390 is included

in the CS4329 and CS4390 data sheets.

CS8412 Digital Audio Receiver

The system receives and decodes the standard

S/PDIF data format using a CS8412 Digital Audio

Receiver, Figure 9. The outputs of the CS8412 in-

clude a serial bit clock, serial data, left-right clock

(FSYNC), de-emphasis control and a 256Fs master

clock.

Power Supply Circuitry

Power is supplied to the evaluation board by four

binding posts, Figure 10. The +5 Volt input sup-

plies power to the CS4329/90 (through VA+), the

CS8412 (through VA+ and VD+), and the +5 Volt

digital circuitry (through VD+). The ±12 volt input

supplies power to the analog filter circuitry.

During normal operation, the CS8412 operates in

the Channel Status mode where the LED’s display

channel status information for the channel selected

by the CSLR/FCK jumper. This allows the CS8412

to decode and supply the de-emphasis bit from the

digital audio interface for control of the CS4329/90

de-emphasis filter via pin 3, CC/F0, of the CS8412.

Input/Output for Clocks and Data

The evaluation board has been designed to allow

the interface to external systems via the 10-pin

header, J1. This header allows the evaluation board

to accept externally generated clocks and data. The

schematic for the clock/data I/O is shown in Figure

7. The 74HC243 transceiver functions as an I/O

buffer where the CLK SOURCE jumper deter-

mines if the transceiver operates as a transmitter or

receiver.

When the Error Information Switch is activated,

the CS8412 operates in the Error and Frequency in-

formation mode. The information displayed by the

LED’s can be decoded by consulting the CS8412

data sheet. If the Error Information Switch is acti-

vated, the CC/F0 output has no relation to the de-

emphasis bit and it is likely that the de-emphasis

22

DS153DB3

CDB4329 CDB4390

The transceiver operates as a transmitter with the

CLK SOURCE jumper in the 8412 position.

LRCK, SDATA, and SCLK from the CS8412 will

be available on J1. J22 must be in the 0 position and

J23 must be in the 1 position for MCLK to be an

output and to avoid bus contention on MCLK.

Grounding and Power Supply Decoupling

The CS4329/90 requires careful attention to power

supply and grounding arrangements to optimize

performance. The recommended power arrange-

ments would be VA+ connected to a clean +5 Volt

supply. The voltage VD+ (pin 6 of the CS4329/90)

should be derived from VA+ through a 2 ohm resis-

tor and should not used for any additional digital

circuitry. Ideally, mode pins which require this

voltage should be connected directly to VD+ (pin 6

of the CS4329/90) and mode pins which require

DGND should be connected directly to pin 5 of the

CS4329/90. AGND and DGND, Pins 4 and 5, are

connected together at the CS4329/90. However, it

was not possible to connect VD+ (pin 6 of the

CS4329/90) and DGND to the mode pins on the

CDB4329/90 due to layout complications resulting

from the hardware selected to exercise the features

of the CS4329/90.

The transceiver operates as a receiver with the CLK

SOURCE jumper in the EXTERNAL position.

LRCK, SDATA and SCLK on J1 become inputs.

The CS8412 must be removed from the evaluation

board for operation in this mode.

There are 2 options for the source of MCLK in the

EXT CLK source mode. MCLK can be an input

with J23 in the 1 position and J22 in the 0 position.

However, the recommended mode of operation is

to generate MCLK on the evaluation board. MCLK

becomes an output with LRCK, SCLK and SDA-

TA inputs. This technique insures that the

CS4329/90 receives a jitter free clock to maximize

performance. This can be accomplished by install-

ing a crystal oscillator into U4, see Figure 9 (the

socket for U4 is located within the footprint for the

CS8412) and placing J22 in the 1 position and J23

in the 0 position.

Figure 2 shows the CS4329/90 and connections.

The evaluation board has separate analog and digi-

tal regions with individual ground planes. DGND

for the CS4329/90 should not be confused with the

ground for the digital section of the system (GND).

The CS4329/90 is positioned over the analog

ground plane near the digital/analog ground plane

split. These ground planes are connected elsewhere

on the board. This layout technique is used to min-

imize digital noise and to insure proper power sup-

ply matching/sequencing. The decoupling

capacitors are located as close to the CS4329/90 as

possible. Extensive use of ground plane fill on both

the analog and digital sections of the evaluation

board yield large reductions in radiated noise ef-

fects.

Analog Filter

The design of the second-order Butterworth low-

pass filter, Figure 6, is discussed in the CS4329 and

CS4390 data sheets and the applications note "De-

sign Notes for a 2-pole Filter with Differential In-

put."

DS153DB3

23

CDB4329 CDB4390

CONNECTOR

+5V

INPUT/OUTPUT

input

SIGNAL PRESENT

+5 Volts for the CS4329/90, CS8412 and digital section

±12 volts for analog filter section

±12V

input

GND

input

ground connection from power supply

digital audio interface input via coax

digital audio interface input via optical

I/O for system clocks and digital audio data

left channel analog output

Digital input

Optical input

J1

input/output

output

AOUTL

AOUTR

output

right channel analog output

Table 1. System Connections

JUMPER

PURPOSE

POSITION

FUNCTION SELECTED

CSLR/FCK

Selects channel for

CS8412 channel status

information

L

R

See CS8412 data sheet for details

Clock Select

Selects source of system

clocks and data

*8412

EXT

0

CS8412 clock/data source

External clock/data source

See Input/Output for Clocks and Data section of

text

J22

J23

Selects MCLK as

input or output

1

M0

M1

M2

M3

CS8412 mode select

*Low

High

*High

*Low

*High

*Low

*INT

EXT

*Low

High

See CS8412 data sheet for details

auto_mute

CS4329/90 Auto Mute

De-emphasis select

On

Off

DEM0

DEM1

DIF0

DIF1

DIF2

See CS4329 and CS4390 data sheets for details

set for 44.1 kHz

See CS4329 and CS4390 data sheets for details

CS4329/90 digital input

format

SCLK

CS4329/90 SCLK Mode

Internal SCLK Mode

External SCLK Mode

CS8412 de-emphasis

DEM_8412

Selects source of de-

emphasis control

De-emphasis input static high

Notes: 1. * Default setting from factory

Table 2. CDB4329/90 Jumper Selectable Options

24

DS153DB3

CDB4329 CDB4390

Digital

Audio

Input

I/O for

Clocks

and Data

Fig 8

Fig 7

MCLK

LRCK

SCLK

AOUTL-

AOUTL+

SDATA

CS8412

Digital

Audio

Analog

Filter

CS4329

or

CS4390

AOUTR-

AOUTR+

Interface

Fig 6

Fig 9

Fig 2

Mute

Section

De-emphasis

Mode

Calibration and

Format Select

Section

Fig 3

Fig 4

Fig 5

Figure 1. System Block Diagram and Signal Flow

DS153DB3

25

CDB4329 CDB4390

Figure 3. De-emphasis Circuitry

Figure 4. Mute Circuitry

Figure 5. Calibration and Format Select Circuitry

DS153DB3

27

CDB4329 CDB4390

NOTE: Rigth channel components in parentheses.

Figure 6. 2-pole Analog Filter

Figure 7. I/O Interface for Clocks and DATA

28

DS153DB3

CDB4329 CDB4390

OPTI Toshiba TORX173 optical receiver available from Insight Electronics

Figure 8. Digital Audio Input Circuit

DS153DB3

29

CDB4329 CDB4390

Figure 10. Power Supply Connections

DS153DB3

31

CDB4329 CDB4390

Figure 11. CDB4329/90 Component Side Silkscreen

32

DS153DB3

CDB4329 CDB4390

Figure 12. CDB4329/90 Component Side (top)

DS153DB3

33

CDB4329 CDB4390

Figure 13. CDB4329/90 Solder Side (bottom)

34

DS153DB3


型号：	CDB4329
厂家：	CIRRUS LOGIC
描述：	20-Bit, Stereo D/A Converter for Digital Audio 20位，立体声D / A转换器，用于数字音频转换器
文件：	总36页 (文件大小：1538K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CDB4329 [CIRRUS]

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