CEP02N6 [CET]
N-CHANNEL LOGIC LEVEL ENHANCEMENT MODE FIELD EFFECT TRANSISTOR; N沟道逻辑电平增强模式场效应晶体管
| 型号： | CEP02N6 |
| 厂家： | 
CHINO-EXCEL TECHNOLOGY |
| 描述： | N-CHANNEL LOGIC LEVEL ENHANCEMENT MODE FIELD EFFECT TRANSISTOR |
| 文件： | 总5页 (文件大小：76K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CEP02N6/CEB02N6
ELECTRICAL CHARACTERISTICS (T
C
=25 C unless otherwise noted)
4
Typ Max
Unit
Parameter
DYNAMIC CHARACTERISTICSb
Condition
Min
Symbol
250
50
Input Capacitance
P
F
C
ISS
OSS
RSS
V
DS =25V, VGS = 0V
P
P
F
F
Output Capacitance
C
f =1.0MH
Z
Reverse Transfer Capacitance
DRAIN-SOURCE DIODE CHARACTERISTICS a
C
30
4
Diode Forward Voltage
V
V
SD
V
GS = 0V, Is =2A
1.5
Notes
ś
ś
a.Pulse Test:Pulse Width 300ijs, Duty Cycle 2%.
b.Guaranteed by design, not subject to production testing.
c. L=60mH, IAS=2.0A, VDD=50V, R
G
=25Ω, Starting T =25 C
J
3.0
VGS=10,9,8,7V
2.5
2.0
150 C
1
1.5
1.0
VGS=6V
VGS=5V
-55 C
1.VDS=40V
2.Pulse Test
0.5
0
25 C
0.1
2
4
10
8
6
0
2
4
6
8
10
12
VDS, Drain-to-Source Voltage (V)
VGS, Gate-to-Source Voltage (V)
Figure 1. Output Characteristics
Figure 2. Transfer Characteristics
4-4
CEP02N6/CEB02N6
2.2
600
ID=1A
VGS=10V
1.9
500
400
300
4
1.6
1.3
Ciss
200
100
0
1.0
Coss
Crss
0.7
0.4
25
0
5
10
15
20
-100
-50
0
50
100
200
150
TJ, Junction Temperature( C)
VDS, Drain-to Source Voltage (V)
Figure 4. On-Resistance Variation with
Temperature
Figure 3. Capacitance
1.15
1.30
ID=250ӴA
V
DS=VGS
=250ӴA
1.10
1.20
1.10
I
D
1.05
1.00
1.00
0.90
0.95
0.90
0.85
0.80
0.70
0.60
-50 -25
0
25 50 75 100 125 150
-50 -25
0
25 50 75 100 125 150
Tj, Junction Temperature ( C)
Tj, Junction Temperature ( C)
Figure 5. Gate Threshold Variation
with Temperature
Figure 6. Breakdown Voltage Variation
with Temperature
20
4
V
GS=0V
10
V
DS=50V
3
2
1
1
0
0.1
1
4
0
2
3
0.4
1.2
0.6
1.0
0.8
IDS, Drain-Source Current (A)
VSD, Body Diode Forward Voltage (V)
Figure 7. Transconductance Variation
with Drain Current
Figure 8. Body Diode Forward Voltage
Variation with Source Current
4-5
CEP02N6/CEB02N6
10
15
V
=480V
IDS
D
=2A
10
ij
12
9
s
t
4
imi
L
1
S(ON)
RD
6
0.1
3
0
T
C
=25C
Tj=25 C
Single Pulse
0.01
500
1000
24
100
0
6
12
18
1
10
Qg, Total Gate Charge (nC)
VDS, Drain-Source Voltage (V)
Figure 9. Gate Charge
Figure 10. Maximum Safe
Operating Area
VDD
on
t
toff
d(off)
t
r
t
d(on)
RL
t
f
t
VIN
90%
10%
90%
D
OUT
V
OUT
V
VGS
10%
INVERTED
RGEN
G
90%
50%
50%
S
IN
V
10%
PULSE WIDTH
Figure 12. Switching Waveforms
Figure 11. Switching Test Circuit
2
1
D=0.5
0.2
0.1
DM
P
0.1
0.05
1
t
2
t
0.02
1. RįJC (t)=r (t) * RįJC
2. RįJC=See Datasheet
3. TJM-TC = P* RįJC (t)
4. Duty Cycle, D=t1/t2
0.01
Single Pulse
0.01
0.01
0.1
1
10
100
1000
10000
Square Wave Pulse Duration (msec)
Figure 13. Normalized Thermal Transient Impedance Curve
4-6
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