CEM3407L [CET]

Dual P-Channel Enhancement Mode Field Effect Transistor; 双P沟道增强型场效应晶体管
CEM3407L
型号: CEM3407L
厂家: CHINO-EXCEL TECHNOLOGY    CHINO-EXCEL TECHNOLOGY
描述:

Dual P-Channel Enhancement Mode Field Effect Transistor
双P沟道增强型场效应晶体管

晶体 晶体管 场效应晶体管
文件: 总4页 (文件大小:228K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
CEM3407L  
Dual P-Channel Enhancement Mode Field Effect Transistor  
FEATURES  
-30V, -5.1A, RDS(ON) = 48m@VGS = -10V.  
RDS(ON) = 65m@VGS = -4.5V.  
RDS(ON) = 115m@VGS = -2.5V.  
Super high dense cell design for extremely low RDS(ON)  
.
High power and current handing capability.  
Lead free product is acquired.  
Surface mount Package.  
D1  
8
D1  
7
D2  
6
D2  
5
SO-8  
1
2
3
4
1
S1  
G1  
S2  
G2  
ABSOLUTE MAXIMUM RATINGS TA = 25 C unless otherwise noted  
Parameter  
Symbol  
VDS  
VGS  
ID  
Limit  
Units  
Drain-Source Voltage  
-30  
±12  
-5.1  
V
V
A
A
Gate-Source Voltage  
Drain Current-Continuous  
Drain Current-Pulsed a  
IDM  
-20.4  
Maximum Power Dissipation  
PD  
2.0  
W
C
Operating and Store Temperature Range  
TJ,Tstg  
-55 to 150  
Thermal Characteristics  
Parameter  
Symbol  
Limit  
Units  
Thermal Resistance, Junction-to-Ambient b  
RθJA  
62.5  
C/W  
Rev 1. 2010.Nov  
http://www.cetsemi.com  
Details are Subject to change without notice  
1
CEM3407L  
Electrical Characteristics TA = 25 C unless otherwise noted  
Parameter  
Off Characteristics  
Symbol  
Test Condition  
Min  
Typ  
Max  
Units  
Drain-Source Breakdown Voltage  
Zero Gate Voltage Drain Current  
Gate Body Leakage Current, Forward  
Gate Body Leakage Current, Reverse  
On Characteristics c  
BVDSS  
IDSS  
VGS = 0V, ID = -250µA  
VDS = -30V, VGS = 0V  
VGS = 12V, VDS = 0V  
VGS = -12V, VDS = 0V  
-30  
V
-1  
µA  
nA  
nA  
IGSSF  
IGSSR  
100  
-100  
Gate Threshold Voltage  
VGS(th)  
RDS(on)  
VGS = VDS, ID = -250µA -0.6  
VGS = -10V, ID = -5.1A  
-1.4  
48  
V
40  
50  
85  
m  
mΩ  
mΩ  
Static Drain-Source  
On-Resistance  
VGS = -4.5V, ID = -4.6A  
VGS = -2.5V, ID = -3.7A  
65  
115  
Dynamic Characteristics d  
Input Capacitance  
Ciss  
Coss  
Crss  
905  
200  
160  
pF  
pF  
pF  
VDS = -15V, VGS = 0V,  
f = 1.0 MHz  
Output Capacitance  
Reverse Transfer Capacitance  
Switching Characteristics d  
Turn-On Delay Time  
Turn-On Rise Time  
td(on)  
tr  
td(off)  
tf  
10  
4
20  
8
ns  
ns  
VDD = -15V, ID= -5.1A,  
VGS = -10V, RGEN = 6Ω  
Turn-Off Delay Time  
Turn-Off Fall Time  
40  
5
80  
10  
11  
ns  
ns  
Total Gate Charge  
Qg  
8.5  
2.5  
1.5  
nC  
nC  
nC  
VDS = -15V, ID = -5.1A,  
VGS = -4.5V  
Gate-Source Charge  
Gate-Drain Charge  
Qgs  
Qgd  
Drain-Source Diode Characteristics and Maximun Ratings  
Drain-Source Diode Forward Current b  
Drain-Source Diode Forward Voltage c  
IS  
-2  
-1  
A
V
VSD  
VGS = 0V, IS = -1A  
Notes :  
a.Repetitive Rating : Pulse width limited by maximum junction temperature.  
b.Surface Mounted on FR4 Board, t < 5 sec.  
c.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%.  
d.Guaranteed by design, not subject to production testing.  
2
CEM3407L  
50  
40  
30  
20  
10  
8
25 C  
-VGS=10,8,6V  
-VGS=5V  
6
-VGS=4V  
4
2
10  
0
-VGS=3V  
TJ=125 C  
-55 C  
2.0  
0
0
2
4
6
8
10  
0
0.5  
10  
1.5  
2.5  
3.0  
-VDS, Drain-to-Source Voltage (V)  
-VGS, Gate-to-Source Voltage (V)  
Figure 1. Output Characteristics  
Figure 2. Transfer Characteristics  
2.2  
1.9  
1.6  
1.3  
1.0  
0.7  
0.4  
1500  
1250  
1000  
750  
500  
250  
0
ID=-5.1A  
VGS=-10V  
C
iss  
C
rss  
0
5
10  
15  
20  
25  
-100  
-50  
0
50  
100  
150  
200  
-VDS, Drain-to-Source Voltage (V)  
TJ, Junction Temperature( C)  
Figure 3. Capacitance  
Figure 4. On-Resistance Variation  
with Temperature  
1.3  
1.2  
1.1  
1.0  
0.9  
0.8  
0.7  
0.6  
VDS=VGS  
V
GS=0V  
ID=-250µA  
101  
100  
10-1  
-50 -25  
0
25 50 75 100 125 150  
0.6  
0.7  
0.8  
0.9  
1.0  
1.1  
TJ, Junction Temperature( C)  
-VSD, Body Diode Forward Voltage (V)  
Figure 5. Gate Threshold Variation  
with Temperature  
Figure 6. Body Diode Forward Voltage  
Variation with Source Current  
3
CEM3407L  
10  
8
VDS=-15V  
ID=-4.9A  
RDS(ON)Limit  
101  
100  
10-1  
10ms  
100ms  
1s  
DC  
6
4
2
TA=25 C  
TJ=150 C  
Single Pulse  
0
10-1  
100  
101  
0
4
8
12  
16  
Qg, Total Gate Charge (nC)  
-VDS, Drain-Source Voltage (V)  
Figure 7. Gate Charge  
Figure 8. Maximum Safe  
Operating Area  
VDD  
on  
t
toff  
d(off)  
t
r
t
d(on)  
OUT  
RL  
t
f
t
VIN  
90%  
10%  
90%  
D
OUT  
V
V
VGS  
10%  
INVERTED  
RGEN  
G
90%  
50%  
50%  
S
IN  
V
10%  
PULSE WIDTH  
Figure 10. Switching Waveforms  
Figure 9. Switching Test Circuit  
100  
D=0.5  
0.2  
PDM  
10-1  
0.1  
t1  
t2  
0.05  
1. RθJA (t)=r (t) * RθJA  
2. RθJA=See Datasheet  
3. TJM-TA = P* RθJA (t)  
4. Duty Cycle, D=t1/t2  
0.02  
Single Pulse  
10-2  
10-4  
10-3  
10-2  
10-1  
100  
101  
102  
Square Wave Pulse Duration (sec)  
Figure 11. Normalized Thermal Transient Impedance Curve  
4

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