CEB730G [CET]
N-Channel Enhancement Mode Field Effect Transistor; N沟道增强型网络场效晶体管
| 型号： | CEB730G |
| 厂家： | 
CHINO-EXCEL TECHNOLOGY |
| 描述： | N-Channel Enhancement Mode Field Effect Transistor |
| 文件： | 总4页 (文件大小：416K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CEP730G/CEB730G
CEF730G
N-Channel Enhancement Mode Field Effect Transistor
PRELIMINARY
FEATURES
Type
VDSS
400V
400V
400V
RDS(ON)
1Ω
1Ω
ID
@VGS
10V
CEP730G
CEB730G
CEF730G
5.5A
5.5A
5.5A e
10V
1Ω
10V
D
Super high dense cell design for extremely low RDS(ON)
.
High power and current handing capability.
Lead free product is acquired.
G
S
CEB SERIES
TO-263(DD-PAK)
CEP SERIES
TO-220
CEF SERIES
TO-220F
ABSOLUTE MAXIMUM RATINGS T = 25 C unless otherwise noted
c
Limit
Parameter
Symbol
Units
TO-220/263
TO-220F
Drain-Source Voltage
VDS
VGS
ID
400
V
V
Gate-Source Voltage
±30
5.5
22
5.5 e
22 e
41
Drain Current-Continuous
Drain Current-Pulsed a
A
f
IDM
A
Maximum Power Dissipation @ TC = 25 C
- Derate above 25 C
83
W
PD
0.66
0.32
W/ C
C
Operating and Store Temperature Range
TJ,Tstg
-55 to 150
Thermal Characteristics
Parameter
Symbol
RθJC
Limit
Units
C/W
C/W
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
1.5
2.5
65
RθJA
62.5
This is preliminary information on a new product in development now .
Details are subject to change without notice .
Rev 1. 2009.Nov.
http://www.cetsemi.com
1
CEP730G/CEB730G
CEF730G
Electrical Characteristics T = 25 C unless otherwise noted
c
Parameter
Off Characteristics
Symbol
Test Condition
Min
Typ
Max
Units
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate Body Leakage Current, Forward
Gate Body Leakage Current, Reverse
On Characteristics b
BVDSS
IDSS
VGS = 0V, ID = 250µA
VDS = 400V, VGS = 0V
VGS = 30V, VDS = 0V
VGS = -30V, VDS = 0V
400
V
10
µA
nA
nA
IGSSF
IGSSR
100
-100
Gate Threshold Voltage
Static Drain-Source
VGS(th)
RDS(on)
gFS
VGS = VDS, ID = 250µA
VGS = 10V, ID = 3A
2
4
1
V
Ω
S
0.8
6
On-Resistance
Forward Transconductance
Dynamic Characteristics c
Input Capacitance
VDS = 50V, ID = 5A
Ciss
Coss
Crss
590
105
20
pF
pF
pF
VDS = 25V, VGS = 0V,
f = 1.0 MHz
Output Capacitance
Reverse Transfer Capacitance
Switching Characteristics c
Turn-On Delay Time
td(on)
tr
td(off)
tf
15
7
30
14
60
10
18
ns
ns
VDD = 200V, ID = 3.5A,
VGS = 10V, RGEN =12Ω
Turn-On Rise Time
Turn-Off Delay Time
30
5
ns
Turn-Off Fall Time
ns
Total Gate Charge
Qg
14
2.5
6
nC
nC
nC
VDS = 320V, ID =3.5A,
VGS = 10V
Gate-Source Charge
Qgs
Qgd
Gate-Drain Charge
Drain-Source Diode Characteristics and Maximun Ratings
f
Drain-Source Diode Forward Current
Drain-Source Diode Forward Voltage b
IS
5.5
1.5
A
V
VSD
VGS = 0V, IS = 3A
Notes :
a.Repetitive Rating : Pulse width limited by maximum junction temperature .
b.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2% .
c.Guaranteed by design, not subject to production testing.
d.Limited only by maximum temperature allowed .
e.Pulse width limited by safe operating area .
f.Full package I
= 5A .
S(max)
2
CEP730G/CEB730G
CEF730G
6
5
4
3
2
1
0
12
10
8
VGS=10,8,7,6V
6
4
V
GS=4V
25 C
2
0
TJ=125C
-55 C
5
0
1
2
3
4
5
6
1
2
3
4
6
VDS, Drain-to-Source Voltage (V)
VGS, Gate-to-Source Voltage (V)
Figure 1. Output Characteristics
Figure 2. Transfer Characteristics
2.6
2.2
1.8
1.4
1.0
0.6
0.2
900
750
600
450
300
150
0
ID=3A
VGS=10V
C
iss
C
oss
C
rss
0
5
10
15
20
25
-100
-50
0
50
100
150
200
VDS, Drain-to-Source Voltage (V)
TJ, Junction Temperature( C)
Figure 3. Capacitance
Figure 4. On-Resistance Variation
with Temperature
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
VDS=VGS
ID=250µA
V
GS=0V
101
100
10-1
-50 -25
0
25 50 75 100 125 150
0.4
0.6
0.8
1.0
1.2
1.4
TJ, Junction Temperature( C)
VSD, Body Diode Forward Voltage (V)
Figure 5. Gate Threshold Variation
with Temperature
Figure 6. Body Diode Forward Voltage
Variation with Source Current
3
CEP730G/CEB730G
CEF730G
102
10
8
VDS=320V
ID=3.5A
RDS(ON)Limit
100µs
101
1ms
6
10ms
DC
4
100
2
TC=25 C
TJ=150 C
Single Pulse
10-1
0
100
101
102
103
0
4
8
12
16
Qg, Total Gate Charge (nC)
VDS, Drain-Source Voltage (V)
Figure 7. Gate Charge
Figure 8. Maximum Safe
Operating Area
VDD
on
t
toff
d(off)
t
r
t
d(on)
OUT
RL
t
f
t
VIN
90%
10%
90%
D
OUT
V
V
VGS
10%
INVERTED
RGEN
G
90%
50%
50%
S
IN
V
10%
PULSE WIDTH
Figure 10. Switching Waveforms
Figure 9. Switching Test Circuit
100
D=0.5
0.2
0.1
10-1
0.05
0.02
0.01
PDM
t1
t2
Single Pulse
10-2
1. Rθ JC (t)=r (t) * Rθ JC
2. Rθ JC=See Datasheet
3. TJM-TC = P* Rθ JC (t)
4. Duty Cycle, D=t1/t2
10-3
10-2
10-1
100
101
102
103
104
Square Wave Pulse Duration (msec)
Figure 11. Normalized Thermal Transient Impedance Curve
4
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