CEB50P03 [CET]

P-Channel Enhancement Mode Field Effect Transistor; P沟道增强型场效应晶体管
CEB50P03
型号: CEB50P03
厂家: CHINO-EXCEL TECHNOLOGY    CHINO-EXCEL TECHNOLOGY
描述:

P-Channel Enhancement Mode Field Effect Transistor
P沟道增强型场效应晶体管

晶体 晶体管 场效应晶体管
文件: 总4页 (文件大小:104K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
CEP50P03/CEB50P03  
P-Channel Enhancement Mode Field Effect Transistor  
FEATURES  
-30V, -47A, RDS(ON) =20m@VGS = -10V.  
RDS(ON) =32m@VGS = -4.5V.  
Super high dense cell design for extremely low RDS(ON)  
.
High power and current handing capability.  
Lead free product is acquired.  
D
TO-220 & TO-263 package.  
G
CEB SERIES  
TO-263(DD-PAK)  
CEP SERIES  
TO-220  
S
ABSOLUTE MAXIMUM RATINGS T = 25 C unless otherwise noted  
c
Parameter  
Symbol  
VDS  
VGS  
ID  
Limit  
Units  
V
Drain-Source Voltage  
-30  
Gate-Source Voltage  
±20  
-47  
V
Drain Current-Continuous  
A
Drain Current-Pulsed a  
IDM  
-188  
79  
A
Maximum Power Dissipation @ TC = 25 C  
- Derate above 25 C  
W
PD  
0.53  
W/ C  
C
Operating and Store Temperature Range  
TJ,Tstg  
-55 to 175  
Thermal Characteristics  
Parameter  
Symbol  
RθJC  
Limit  
1.9  
Units  
C/W  
C/W  
Thermal Resistance, Junction-to-Case  
Thermal Resistance, Junction-to-Ambient  
RθJA  
62.5  
Rev 2. 2005.May  
Specification and data are subject to change without notice .  
http://www.cetsemi.com  
1
CEP50P03/CEB50P03  
Electrical Characteristics TA = 25 C unless otherwise noted  
Parameter  
Off Characteristics  
Symbol  
Test Condition  
Min  
Typ  
Max  
Units  
Drain-Source Breakdown Voltage  
Zero Gate Voltage Drain Current  
Gate Body Leakage Current, Forward  
Gate Body Leakage Current, Reverse  
On Characteristics c  
BVDSS  
IDSS  
VGS = 0V, ID = -250µA  
VDS = -24V, VGS = 0V  
VGS = 20V, VDS = 0V  
VGS = -20V, VDS = 0V  
-30  
V
5
5
-1  
µA  
nA  
nA  
IGSSF  
IGSSR  
100  
-100  
Gate Threshold Voltage  
Static Drain-Source  
VGS(th)  
RDS(on)  
gFS  
VGS = VDS, ID = -250µA  
VGS = -10V, ID = -25A  
VGS = -4.5V, ID = -20A  
VDS = -15V, ID = -25A  
-1  
-3  
20  
32  
V
mΩ  
mΩ  
S
17  
25  
20  
On-Resistance  
Forward Transconductance  
Dynamic Characteristics d  
Input Capacitance  
Ciss  
Coss  
Crss  
2220  
550  
pF  
pF  
pF  
VDS = -15V, VGS = 0V,  
f = 1.0 MHz  
Output Capacitance  
Reverse Transfer Capacitance  
Switching Characteristics d  
Turn-On Delay Time  
230  
td(on)  
tr  
td(off)  
tf  
12  
6
24  
18  
ns  
ns  
VDD = -15V, ID = -1A,  
VGS = -10V, RGEN = 6Ω  
Turn-On Rise Time  
Turn-Off Delay Time  
110  
35  
22  
7
140  
70  
ns  
Turn-Off Fall Time  
ns  
Total Gate Charge  
Qg  
28  
nC  
nC  
nC  
VDS = -15V, ID = -25A,  
VGS = -5V  
Gate-Source Charge  
Qgs  
Qgd  
Gate-Drain Charge  
8
Drain-Source Diode Characteristics and Maximun Ratings  
Drain-Source Diode Forward Current b  
Drain-Source Diode Forward Voltage c  
IS  
-2.1  
-1.2  
A
V
VSD  
VGS = 0V, IS = -2.1A  
Notes :  
a.Repetitive Rating : Pulse width limited by maximum junction temperature.  
b.Surface Mounted on FR4 Board, t < 10 sec.  
c.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%.  
d.Guaranteed by design, not subject to production testing.  
2
CEP50P03/CEB50P03  
25  
20  
15  
10  
100  
25 C  
-VGS=10,8,7,6,5V  
80  
60  
40  
-VGS=4V  
-55 C  
TJ=125 C  
20  
0
5
0
-VGS=3V  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
0
1
2
3
4
5
6
-VDS, Drain-to-Source Voltage (V)  
-VGS, Gate-to-Source Voltage (V)  
Figure 1. Output Characteristics  
Figure 2. Transfer Characteristics  
2.2  
1.9  
1.6  
1.3  
1.0  
0.7  
0.4  
3000  
2500  
2000  
1500  
1000  
500  
ID=-25A  
VGS=-10V  
C
iss  
C
oss  
C
rss  
0
0
5
10  
15  
20  
25  
-100  
-50  
0
50  
100  
150  
200  
-VDS, Drain-to-Source Voltage (V)  
TJ, Junction Temperature( C)  
Figure 3. Capacitance  
Figure 4. On-Resistance Variation  
with Temperature  
1.3  
1.2  
1.1  
1.0  
0.9  
0.8  
0.7  
0.6  
VDS=VGS  
V
GS=0V  
ID=-250µA  
102  
101  
100  
-50 -25  
0
25 50 75 100 125 150  
0.4  
0.6  
0.8  
1.0  
1.2  
1.4  
TJ, Junction Temperature( C)  
-VSD, Body Diode Forward Voltage (V)  
Figure 5. Gate Threshold Variation  
with Temperature  
Figure 6. Body Diode Forward Voltage  
Variation with Source Current  
3
CEP50P03/CEB50P03  
103  
10  
8
VDS=-15V  
ID=-25A  
RDS(ON)Limit  
102  
100ms  
6
1ms  
5
10ms  
4
101  
DC  
2
TC=25 C  
TJ=175 C  
Single Pulse  
100  
0
10-1  
100  
101  
102  
0
5
10  
15  
20  
25  
30  
Qg, Total Gate Charge (nC)  
-VDS, Drain-Source Voltage (V)  
Figure 7. Gate Charge  
Figure 8. Maximum Safe  
Operating Area  
VDD  
on  
t
toff  
d(off)  
t
r
t
d(on)  
OUT  
RL  
t
f
t
VIN  
90%  
10%  
90%  
D
OUT  
V
V
VGS  
10%  
INVERTED  
RGEN  
G
90%  
50%  
50%  
S
IN  
V
10%  
PULSE WIDTH  
Figure 10. Switching Waveforms  
Figure 9. Switching Test Circuit  
100  
D=0.5  
0.2  
10-1  
0.1  
PDM  
t1  
t2  
0.05  
0.02  
0.01  
1. RθJC (t)=r (t) * RθJC  
2. RθJC=See Datasheet  
3. TJM-TC = P* RθJC (t)  
4. Duty Cycle, D=t1/t2  
Single Pulse  
10-2  
10-4  
10-3  
10-2  
10-1  
100  
101  
102  
Square Wave Pulse Duration (sec)  
Figure 11. Normalized Thermal Transient Impedance Curve  
4

相关型号:

CEB51A3

N-Channel Enhancement Mode Field Effect Transistor
CET

CEB540A

N-Channel Enhancement Mode Field Effect Transistor
CET

CEB540L

N-Channel Enhancement Mode Field Effect Transistor
CET

CEB540N

N-Channel Enhancement Mode Field Effect Transistor
CET

CEB6020P

Single P-Channel Enhancement Mode MOSFET
CET

CEB603

N-Channel Logic Level Enhancement Mode Field Effect Transistor
CET

CEB6030AL

N-Channel Logic Level Enhancement Mode Field Effect Transistor
CET

CEB6030L

N-Channel Logic Level Enhancement Mode Field Effect Transistor
CET

CEB6030LS2

N-Channel Logic Level Enhancement Mode Field Effect Transistor
CET

CEB6031L

N-Channel Logic Level Enhancement Mode Field Effect Transistor
CET

CEB6031LS2

N-Channel Logic Level Enhancement Mode Field Effect Transistor
CET

CEB603AL

N-Channel Logic Level Enhancement Mode Field Effect Transistor
CET