CEB540L [CET]
N-Channel Enhancement Mode Field Effect Transistor; N沟道增强型网络场效晶体管型号: | CEB540L |
厂家: | CHINO-EXCEL TECHNOLOGY |
描述: | N-Channel Enhancement Mode Field Effect Transistor |
文件: | 总4页 (文件大小:677K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CEP540L/CEB540L
CEF540L
N-Channel Enhancement Mode Field Effect Transistor
FEATURES
100V, 36A, RDS(ON) = 50mΩ @VGS = 10V.
RDS(ON) = 53mΩ @VGS = 5V.
Super high dense cell design for extremely low RDS(ON)
.
High power and current handing capability.
Lead free product is acquired.
D
TO-220 & TO-263 package.
G
CEF SERIES
TO-220F
CEB SERIES
TO-263(DD-PAK)
CEP SERIES
TO-220
S
ABSOLUTE MAXIMUM RATINGS T = 25 C unless otherwise noted
c
Parameter
Symbol
VDS
VGS
ID
Limit
Units
V
Drain-Source Voltage
100
Gate-Source Voltage
±20
36
V
Drain Current-Continuous
A
Drain Current-Pulsed a
IDM
120
A
Maximum Power Dissipation @ TC = 25 C
- Derate above 25 C
Single Pulsed Avalanche Energy d
Single Pulsed Avalanche Current d
Operating and Store Temperature Range
140
W
PD
0.91
310
W/ C
mJ
A
EAS
IAS
18
TJ,Tstg
-55 to 175
C
Thermal Characteristics
Parameter
Symbol
RθJC
Limit
1.1
Units
C/W
C/W
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
RθJA
62.5
Rev .1 2010.April.
.
http://www.cetsemi.com
Details are subject to change without notice .
1
CEP540L/CEB540L
CEF540L
Electrical Characteristics T = 25 C unless otherwise noted
c
Parameter
Off Characteristics
Symbol
Test Condition
Min
Typ
Max
Units
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate Body Leakage Current, Forward
Gate Body Leakage Current, Reverse
On Characteristics b
BVDSS
IDSS
VGS = 0V, ID = 250µA
VDS = 100V, VGS = 0V
VGS = 20V, VDS = 0V
VGS = -20V, VDS = 0V
100
V
25
100
-100
µA
nA
nA
IGSSF
IGSSR
Gate Threshold Voltage
VGS(th)
VGS = VDS, ID = 250µA
VGS = 10V, ID = 18A
VGS = 5V, ID = 15A
VDS = 25V, ID = 18A
1
3
V
Static Drain-Source
mΩ
mΩ
S
40
43
50
53
RDS(on)
gFS
On-Resistance
Forward Transconductance
14
Dynamic Characteristics c
Input Capacitance
Ciss
Coss
Crss
1295
199
40
pF
pF
pF
VDS = 25V, VGS = 0V,
f = 1.0 MHz
Output Capacitance
Reverse Transfer Capacitance
Switching Characteristics c
Turn-On Delay Time
Turn-On Rise Time
td(on)
tr
td(off)
tf
13
3.1
55
5
26
7
ns
ns
VDD = 50V, ID = 18A,
VGS = 10V, RGEN = 5.1Ω
Turn-Off Delay Time
Turn-Off Fall Time
110
10
80
ns
ns
Total Gate Charge
Qg
40
3.7
10
nC
nC
nC
VDS = 80V, ID = 18A,
VGS = 10V
Gate-Source Charge
Gate-Drain Charge
Qgs
Qgd
Drain-Source Diode Characteristics and Maximun Ratings
Drain-Source Diode Forward Current
Drain-Source Diode Forward Voltage b
Notes :
IS
36
A
V
VSD
VGS = 0V, IS = 18A
1.3
a.Repetitive Rating : Pulse width limited by maximum junction temperature.
b.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%.
c.Guaranteed by design, not subject to production testing.
d.L = 1mH, I = 15A, V = 50V, R = 25Ω, Starting T = 25 C
AS
DD
G
J
2
CEP540L/CEB540L
CEF540L
40
30
20
40
25 C
VGS=10,8,6,5V
30
20
VGS=4.0
V
10
10
0
TJ=125 C
1.0
-55 C
0
0
1
2
3
4
5
0.0
2.0
3.0
4.0
5.0
VDS, Drain-to-Source Voltage (V)
VGS, Gate-to-Source Voltage (V)
Figure 1. Output Characteristics
Figure 2. Transfer Characteristics
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2400
2000
1600
1200
800
400
0
ID=18A
VGS=10V
C
iss
C
oss
C
rss
0
5
10
15
20
25
-100
-50
0
50
100
150
200
VDS, Drain-to-Source Voltage (V)
TJ, Junction Temperature( C)
Figure 3. Capacitance
Figure 4. On-Resistance Variation
with Temperature
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
VDS=VGS
ID=250µA
V
GS=0V
102
101
100
-50 -25
0
25 50 75 100 125 150
0.4
0.6
0.8
1.0
1.2
1.4
TJ, Junction Temperature( C)
VSD, Body Diode Forward Voltage (V)
Figure 5. Gate Threshold Variation
with Temperature
Figure 6. Body Diode Forward Voltage
Variation with Source Current
3
CEP540L/CEB540L
CEF540L
103
10
8
VDS=80V
ID=18A
RDS(ON)Limit
102
10µs
6
100µs
101
1ms
4
10ms
100
2
TC=25 C
TJ=175 C
Single Pulse
10-1
0
100
101
102
103
0
10
20
30
40
Qg, Total Gate Charge (nC)
VDS, Drain-Source Voltage (V)
Figure 7. Gate Charge
Figure 8. Maximum Safe
Operating Area
VDD
on
t
toff
d(off)
t
r
t
d(on)
OUT
RL
t
f
t
VIN
90%
10%
90%
D
OUT
V
V
VGS
10%
INVERTED
RGEN
G
90%
50%
50%
S
IN
V
10%
PULSE WIDTH
Figure 10. Switching Waveforms
Figure 9. Switching Test Circuit
100
D=0.5
0.2
PDM
0.1
10-1
0.05
0.02
t1
t2
0.01
1. Rθ JC (t)=r (t) * Rθ JC
2. Rθ JC=See Datasheet
3. TJM-TC = P* Rθ JC (t)
4. Duty Cycle, D=t1/t2
Single Pulse
10-2
10-2
10-1
100
101
102
103
104
Square Wave Pulse Duration (msec)
Figure 11. Normalized Thermal Transient Impedance Curve
4
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