PACDN002Q/T [CALMIRCO]

Trans Voltage Suppressor Diode, Unidirectional, 34 Element, Silicon, MO-137AD, QSOP-20;


型号：	PACDN002Q/T
厂家：	CALIFORNIA MICRO DEVICES CORP
描述：	Trans Voltage Suppressor Diode, Unidirectional, 34 Element, Silicon, MO-137AD, QSOP-20 局域网光电二极管
文件：	总3页 (文件大小：292K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PAC DN002

CALIFORNIA MICRO DEVICES

17 CHANNEL ESD PROTECTION ARRAY

Features

Applications

17-channel ESD protection

8kV contact discharge ESD protection per

IEC 61000-4-2

Parallel printer port protection

ESD protection for sensitive

electronic equipment

15kV ESD protection (HBM)

Low loading capacitance, 5.5pF typ.

20-pin SOIC or QSOP package

Drop-in replacement for PDN 002

Product Description

The PAC DN002 is a diode array designed to provide 17 channels of ESD protection for electronic components or

sub-systems. Each channel consists of a pair of diodes which steers the ESD current pulse either to the positive (V_P) or

negative (V_N) supply. The PAC DN002 will protect against ESD pulses up to 15KV Human Body Model.

This device is particularly well-suited to provide additional ESD protection for parallel printer ports. It exhibits low

loading capacitance for all signal lines.

ABSOLUTE MAXIMUM RATINGS

SCHEMATIC CONFIGURATION

Diode Forward DC Current (Note 1)

Storage Temperature

Operating Temperature Range

20mA

-65^°C to 150^°C

-20°C to 85°C

DC Voltage at any Channel Input V_N-0.5V to V_P+0.5V

Note 1: Only one diode conducting at a time.

S TA N D A R D S P E C IF IC A TIO N S

Param eter

Min.

Typ.

Max.

Param eter

Min.

Max.

Operating Supply Voltage (V_P- V_N)

12.0V

Operating Supply Voltage (V - V_N)

12.0V

Supply Current (V_P- V_N) = 1^P2.0V, T= 25°C

10 µA

Supply Current (V - V_N) = 12.0V, T= 25°C

10 µA

1.0 V

Diode Forward Vo^Pltage, I_F= 20mA, T = 25°C

0.65 V

Diode Forward Voltage, I_F= 20mA, T = 25°C

ESD Protection

1.0 V

ESD Protection

Voltage at any Channel Input

Human Body Model, Method 3015 (See Note 2, 3)

± 15KV

± 8KV

Human Body Model, Method 3015 (See Note 2, 3)

Contact Discharge per IEC 1000-4-2 (See Note 4)

± 8KV

Channel Clamp Voltage under ESD test conditions

specified above, T = 25°C (Notes 2,3,4)

Positive transients

V_P+ 13.0 V

Positive transients

00 Negative transients

V_N- 13.0 V

00 Negative transients

V_N- 13.0 V

Channel Leakage Current, T = 25°C

± 0.1 µA

± 1.0 µA

Channel Input Capacitance (Measured @ 1 MHz)

V_P= 12V, V_N= 0V, V_IN= 6V (See Note 4)

5.5pF

12pF

Package Power Rating

1.00W

Note 2: From I/O pins to V_Por V_Nonly. V_Pbypassed to V_Nwith 0.2 µF ceramic capacitor.

Note 3: Human Body Model per MIL-STD-883, Method 3015, C_Discharge=100pF, R_Discharge=1.5KΩ, V_P=12V, V_N=GND.

Note 4: This parameter is guaranteed by characterization.

P/Active and PAC are trademarks of California Micro Devices.

C0270498D

11/99

215 Topaz Street, Milpitas, California 95035

Tel: (408) 263-3214

Fax: (408) 263-7846

www.calmicro.com

CALIFORNIA MICRO DEVICES

PAC DN002

Input Capacitance vs. Input Voltage

Input Voltage (V)

Typical variation of C_INwith V_IN

(V_P= 12V, V_N= 0V, 0.1µF chip capacitor between V_P& V_N)

S TA N D A R D P A R T O R D E R IN G IN F O R M A TIO N

Package

Ordering Part Num ber

Part Marking

Pins

Style

SOIC

QSOP

PACDN002S

PACDN002Q

When placing an order please specify desired shipping: Tubes or Tape & Reel.

Application Information

See also California Micro Devices Application note AP209, Design Considerations for ESD protection.

In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize

parasitic series inductances to the Supply and Ground rails. Refer to Figure 1, which illustrates the case of a positive

ESD pulse applied between an input channel and Chassis Ground. The parasitic series inductance back to the power

supply is represented by L₁. The voltage V_Zon the line being protected is:

V_Z= Forward voltage drop of D₁+ L₁x d(I_esd)/dt + V_Supply

where I_esdis the ESD current pulse, and V_Supplyis the positive supply voltage.

Figure 1

An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge

per the IEC 61000-4-2 standard results in a current pulse that rises from zero to 30 Amps in 1nS. Here d(I_esd)/dt can be

approximated by ∆I_esd/∆t, or 30/(1x10^-9). So just 10nH of series inductance (L₁) will lead to a 300V increment in V_Z!

11/99

215 Topaz Street, Milpitas, California 95035

Tel: (408) 263-3214

Fax: (408) 263-7846

www.calmicro.com

PAC DN002

CALIFORNIA MICRO DEVICES

Similarly for negative ESD pulses, parasitic series inductance from the V_Npin to the ground rail will lead to drastically

increased negative voltage on the line being protected.

Another consideration is the output impedance of the power supply for fast transient currents. Most power supplies

exhibit a much higher output impedance to fast transient current spikes. In the V_Zequation above, the V_Supplyterm, in

reality, is given by (V_DC+ I_esdx R_out), where V_DCand R_outare the nominal supply DC output voltage and effective output

impedance of the power supply respectively. As an example, a R_outof 1 ohm would result in a 10V increment in V_Zfor a

peak I_esdof 10A.

To mitigate these effects, a high frequency bypass capacitor should be connected between the V_Ppin of the ESD Protection

Array and the ground plane. The value of this bypass capacitor should be chosen such that it will absorb the charge

transferred by the ESD pulse with minimal change in V_P. Typically a value in the 0.1 µF to 0.2 µF range is adequate for

IEC-61000-4-2 level 4 contact discharge protection (8KV). For higher ESD voltages, the bypass capacitor should be

increased accordingly. Ceramic chip capacitors mounted with short printed circuit board traces are good choices for this

application. Electrolytic capacitors should be avoided as they have poor high frequency characteristics. For extra protection,

connect a zener diode in parallel with the bypass capacitor to mitigate the effects of the parasitic series inductance

inherent in the capacitor. The breakdown voltage of the zener diode should be slightly higher than the maximum supply

voltage.

As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected

electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the V_Ppin of the

Protection Array as possible, with minimum PCB trace lengths to the power supply and ground planes to minimize stray

series inductance.

11/99

215 Topaz Street, Milpitas, California 95035

Tel: (408) 263-3214

Fax: (408) 263-7846

www.calmicro.com

PACDN002Q/T [CALMIRCO]

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