PACDN004 [ONSEMI]
2-Channel ESD Protection Array; 2通道ESD保护阵列
| 型号： | PACDN004 |
| 厂家： | 
ONSEMI |
| 描述： | 2-Channel ESD Protection Array |
| 文件： | 总9页 (文件大小：102K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2-Channel ESD Protection Array
PACDN004
Features
Product Description
•
•
Two channels of ESD protection
The PACDN004 is a diode array designed to provide
two channels of ESD protection for electronic
components or sub-systems. Each channel consists
of a pair of diodes which steers the ESD current
pulse either to the positive (VP) or negative (VN)
supply. The PACDN004 will protect against ESD
pulses up to 15kV Human Body Model, and 8kV
contact discharge per International Standard IEC
61000-4-2.
+8kV contact, +15kV air ESD protection
per channel (IEC 61000-4-2 standard)
+15kV of ESD protection per channel (HBM)
Low loading capacitance of 3 pF typical
Low leakage current is ideal for battery-powered
devices
•
•
•
•
•
Miniature 4-pin SOT-143 package
RoHS compliant (lead-free) finishing
Applications
This device has identical characteristics as the
PACDN006 (6-channel array). They can be used
together in order to provide a larger number of
protected inputs if required. This device is particularly
well-suited for a wide range of portable electronics
(e.g. cellular phones, PDAs, notebook computers)
because of its small package footprint, high ESD
protection level and low loading capacitance. It is
also suitable for protecting video output lines and I/O
ports in computers and peripherals.
•
•
•
•
•
•
•
Consumer electronic products
Cellular phones
PDAs
Notebook computers
Desktop PCs
Digital cameras and camcorders
VGA (video) port protection for desktop
and portable PCs
The PACDN004 is available with RoHS compliant
lead-free finishing.
©2010 SCILLC. All rights reserved.
May 2010 Rev. 3
Publication Order Number:
PACDN004/D
PACDN004
Rev. 3 | Page 2 of 9 | www.onsemi.com
PACDN004
PIN DESCRIPTIONS
PIN
NAME
TYPE
DESCRIPTION
1
VN
CH1
CH2
VP
Gnd
Negative voltage supply rail or ground reference rail
ESD Channel 1
2
3
4
I/O
I/O
ESD Channel 2
Supply
Positive voltage supply rail
Ordering Information
PART NUMBERING INFORMATION
Pins
Package
SOT-143
Ordering Part Number1
Part Marking
4
PACDN004SR
D014
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.
Specifications
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
UNITS
Supply Voltage (VP - VN)
6.0
V
Diode Forward DC Current (Note 1)
Operating Temperature Range
Storage Temperature Range
DC Voltage at any channel input
Package Power Rating
20
mA
°C
-40 to +85
-65 to +150
°C
(VN - 0.5) to (VP + 0.5)
225
V
mW
Note 1: Only one diode conducting at a time.
Rev. 3 | Page 3 of 9 | www.onsemi.com
PACDN004
STANDARD OPERATING CONDITIONS
PARAMETER
RATING
UNITS
Operating Temperature Range
-40 to +85
0 to 5.5
°C
Operating Supply Voltage (VP - VN)
V
ELECTRICAL OPERATING CHARACTERISTICS(SEE NOTE 1)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
IP
Supply Current
(VP-VN)=5.5V
10
μA
VF
Diode Forward Voltage
Channel Leakage Current
Channel Input Capacitance
IF = 20mA
0.65
0.95
+1.0
5
V
ILEAK
CIN
+0.1
3
μA
pF
@ 1 MHz, VP=5V,
VN=0V, VIN=2.5V
VESD
ESD Protection
Peak Discharge Voltage at any
channel input, in system
a) Human Body Model, MIL-STD-
883, Method 3015
b) Contact discharge per
IEC 61000-4-2 standard
c) Air discharge per IEC 61000-4-2
Note 2
Notes 2 and 3
Notes 2 and 4
Notes 2 and 4
+15
+8
kV
kV
kV
+15
VCL
Channel Clamp Voltage
@15kV ESD HBM;
Notes 2 and 3
Positive Transients
Negative Transients
VP + 13.0
VN - 13.0
V
V
Note 1: All parameters specified at TA=25°C unless otherwise noted. VP = 5V, VN = 0V unless noted.
Note 2: From I/O pins to VP or VN only. VP bypassed to VN with a 0.22μF ceramic capacitor (see Application Information for
more details).
Note 3: Human Body Model per MIL-STD-883, Method 3015, CDischarge = 100pF, RDischarge = 1.5KΩ, VP = 5.0V, VN grounded.
Note 4: Standard IEC 61000-4-2 with CDischarge = 150pF, RDischarge = 330Ω, VP = 5.0V, VN grounded.
Rev. 3 | Page 4 of 9 | www.onsemi.com
PACDN004
Performance Information
Input Capacitance vs. Input Voltage
Rev. 3 | Page 5 of 9 | www.onsemi.com
PACDN004
Application Information
Design Considerations
In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to
minimize parasitic series inductances on the Supply/Ground rails as well as the signal trace segment
between the signal input (typically a connector) and the ESD protection device. Refer to Application of
Positive ESD Pulse between Input Channel and Ground, which illustrates an example of a positive ESD
pulse striking an input channel. The parasitic series inductance back to the power supply is represented
by L1 andL2. The voltage VCL on the line being protected is:
VCL = Fwd voltage drop of D1 + VSUPPLY + L1 x d(IESD ) / dt+ L2 x d(IESD ) / dt
where IESD is the ESD current pulse, and VSUPPLY is the positive supply voltage.
An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4
contact discharge per the IEC61000-4-2 standard results in a current pulse that rises from zero to 30
Amps in 1ns. Here d(IESD)/dt can be approximated by ΔIESD/Δt, or 30/(1x10-9). So just 10nH of series
inductance (L1 andL2 combined) will lead to a 300V increment in VCL!
Similarly for negative ESD pulses, parasitic series inductance from the VN pin to the ground rail will lead to
drastically increased negative voltage on the line being protected.
Another consideration is the output impedance of the power supply for fast transient currents. Most power
supplies exhibit a much higher output impedance to fast transient current spikes. In the VCL equation
above, the VSUPPLY term, in reality, is given by (VDC + IESD x ROUT), where VDC and ROUT are the nominal supply
DC output voltage and effective output impedance of the power supply respectively. As an example, a
ROUT of 1 ohm would result in a 10V increment in VCL for a peak IESD of 10A.
If the inductances and resistance described above are close to zero, the rail-clamp ESD protection diodes
will do a good job of protection. However, since this is not possible in practical situations, a bypass
capacitor must be used to absorb the very high frequency ESD energy. So for any brand of rail-clamp
ESD protection diodes, a bypass capacitor should be connected between the VP pin of the diodes and the
ground plane (VN pin of the diodes) as shown in the Application Circuit diagram below. A value of 0.22µF
is adequate for IEC-61000-4-2 level 4 contact discharge protection (+8kV). Ceramic chip capacitors
mounted with short printed circuit board traces are good choices for this application. Electrolytic
capacitors should be avoided as they have poor high frequency characteristics. For extra protection,
connect a zener diode in parallel with the bypass capacitor to mitigate the effects of the parasitic series
inductance inherent in the capacitor. The breakdown voltage of the zener diode should be slightly higher
than the maximum supply voltage.
As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of
expected electrostatic discharges. The power supply bypass capacitor mentioned above should be as
close to the VP pin of the Protection Array as possible, with minimum PCB trace lengths to the power
supply, ground planes and between the signal input and the ESD device to minimize stray series
inductance.
Additional Information
See also California Micro Devices Application Notes AP209, “Design Considerations for ESD Protection”
and AP219, "ESD Protection for USB 2.0 Systems"
Rev. 3 | Page 6 of 9 | www.onsemi.com
PACDN004
Figure 1. Application of Positive ESD Pulse between Input Channel and Ground
Rev. 3 | Page 7 of 9 | www.onsemi.com
PACDN004
Mechanical Details
SOT-143 Mechanical Specifications
PACDN004 devices are packaged in 4-pin SOT-143 packages. Dimensions are presented below.
For complete information on the SOT-143 package, see the California Micro Devices SOT-143 Package
Information document.
PACKAGE DIMENSIONS
SOT-143
4
Package
Pins
Millimeters
Min Max
Inches
Dimensions
Min
Max
0.80
0.05
0.30
0.76
0.08
2.80
2.10
1.20
1.22
0.15
0.50
0.89
0.20
3.04
2.64
1.40
0.031
0.002
0.012
0.030
0.003
0.110
0.082
0.047
0.048
A
A1
b
0.006
0.019
0.035
0.008
0.119
0.103
0.055
b2
c
D
E
E1
e
1.92 BSC
0.20 BSC
0.4 0.6
0.54 REF
0.075 BSC
0.008 BSC
0.016 0.024
0.021 REF
3000 pieces
e1
L
Package Dimensions for SOT-143.
L1
# per tape
and reel
Controlling dimension: millimeters
Rev. 3 | Page 8 of 9 | www.onsemi.com
PACDN004
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any
products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising
out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical”
parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the
rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or
use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action
Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
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For additional information, please contact your local
Sales Representative
Rev. 3 | Page 9 of 9 | www.onsemi.com
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