PACDN004/R [CALMIRCO]
Trans Voltage Suppressor Diode, Unidirectional, 4 Element, Silicon, SOT-143, 4 PIN;
| 型号： | PACDN004/R |
| 厂家： | 
CALIFORNIA MICRO DEVICES CORP |
| 描述： | Trans Voltage Suppressor Diode, Unidirectional, 4 Element, Silicon, SOT-143, 4 PIN 局域网 光电二极管 |
| 文件： | 总3页 (文件大小：135K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CALIFORNIA MICRO DEVICES
PAC DN004
2 CHANNEL ESD PROTECTION ARRAY
Features
Applications
2-channel ESD protection
15KV ESD protection (HBM)
8KV contact discharge ESD protection
per IEC 61000-4-2
I/O port: protection for cellular phones,
notebooks computers, PDA, etc.
ESD protection for sensitive
electronic equipment.
Low loading capacitance, 3 pF typ.
Miniature 4-pin SOT-143 package
ESD protection for applications where
low capacitive loading is required.
Product Description
The PAC DN004 is a diode array designed to provide two channels of ESD protection for electronic components or sub-
systems. Each channel consists of a pair of diodes which steers the ESD current pulse either to the positive (VP) or negative
(VN) supply. The PAC DN004 will protect against ESD pulses up to 15 KV Human Body Model, and 8KV contact discharge
per International Standard IEC 61000-4-2.
This device has identical characteristics as the PAC DN006 (6 channel array). They can be used together in order to provide
a larger number of protected inputs if required. This device is particularly well-suited for portable electronics (e.g. cellular
phones, PDAs, notebook computers) because of its small package footprint, high ESD protection level, and low loading
capacitance. It is also suitable for protecting video output lines and I/O ports in computers and peripheral equipment.
SCHEMATIC CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
4
Diode Forward DC Current (Note 1)
Storage Temperature
20mA
VP
-65°C to 150°C
-20°C to 85°C
Operating Temperature Range
DC Voltage at any Channel Input VN-0.5V to VP+0.5V
2
3
I/O 2
I/O 1
Note 1: Only one diode conducting at a time.
VN
1
S TA N D A R D S P E C IF IC A TIO N S
Min.
Param eter
Typ.
Max.
5.5 V
10 µA
0.95 V
Operating Supply Voltage (VP- VN)
Supply Current, (VP - VN) = 5.5V, T= 25°C
Diode Forward Voltage, IF = 20mA, T = 25°C
ESD Protection
0.65 V
Peak Discharge Voltage at any Channel Input, in-system (Note 2)
000Human Body Model, Method 3015 (Note 3, 4)
000Contact Discharge per IEC 61000-4-2 (Note 5)
± 15 KV
± 8 KV
Channel Clamp Voltage @ 15KV ESD HBM, T = 25°C
(Notes 3, 4)
000Positive transients
000Negative transients
Channel Leakage Current, T = 25°C
VP+ 13.0 V
VN- 13.0 V
± 1.0 µA
± 0.1 µA
3pF
Channel Input Capacitance (Measured @ 1 MHz)
VP= 5V, VN= 0V, VIN= 2.5V (Note 4)
6pF
Package Power Rating
225mW
Note 2: From I/O pins to VP or VN only. VP bypassed to VN with 0.2 µF ceramic capacitor.
Note 3: Human Body Model per MIL-STD-883, Method 3015, CDischarge=100pF, RDischarge=1.5KΩ, VP=5.0V, VN=GND.
Note 4: This parameter is guaranteed by characterization.
Note 5: Standard IEC 61000-4-2 with CDischarge=150pF, and RDischarge=330Ω, VP=5V, VN=GND.
©1999 California Micro Devices Corp. All rights reserved.
P/Active® is a registered trademark and PAC is a trademark of California Micro Devices.
C0280498D
11/99
1
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
CALIFORNIA MICRO DEVICES
PAC DN004
Input Capacitance vs. Input Voltage
5
4
3
2
1
0
0
1
2
3
4
5
Input Voltage
Typical variation of CIN with VIN
(VP = 5V, VN = 0V, 0.1µF chip capacitor between VP & VN)
S TA N D A R D P A R T O R D E R IN G IN F O R M A TIO N
Package
Ordering Part Num ber
Pins
Style
Part Marking
4
SOT-143
DN004
When placing an order please specify desired shipping: Tubes or Tape & Reel.
Application Information
See also California Micro Devices Application note AP209, Design Considerations for ESD protection.
In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize
parasitic series inductances to the Supply and Ground rails. Refer to Figure 1, which illustrates the case of a positive
ESD pulse applied between an input channel and Chassis Ground. The parasitic series inductance back to the power
supply is represented by L1. The voltage VZ on the line being protected is:
VZ = Forward voltage drop of D1 + L1 x d(Iesd)/dt + VSupply
where Iesd is the ESD current pulse, and VSupply is the positive supply voltage.
Figure 1
An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge
per the IEC 61000-4-2 standard results in a current pulse that rises from zero to 30 Amps in 1nS. Here d(Iesd)/dt can be
approximated by ∆Iesd/∆t, or 30/(1x10-9). So just 10nH of series inductance (L1) will lead to a 300V increment in VZ!
©1999 California Micro Devices Corp. All rights reserved.
11/99
2
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
CALIFORNIA MICRO DEVICES
PAC DN004
Similarly for negative ESD pulses, parasitic series inductance from the VN pin to the ground rail will lead to drastically
increased negative voltage on the line being protected.
Another consideration is the output impedance of the power supply for fast transient currents. Most power supplies
exhibit a much higher output impedance to fast transient current spikes. In the VZ equation above, the VSupply term, in
reality, is given by (VDC + Iesd x Rout), where VDC and Rout are the nominal supply DC output voltage and effective output
impedance of the power supply respectively. As an example, a Rout of 1 ohm would result in a 10V increment in VZ for a
peak Iesd of 10A.
To mitigate these effects, a high frequency bypass capacitor should be connected between the VP pin of the ESD Protection
Array and the ground plane. The value of this bypass capacitor should be chosen such that it will absorb the charge
transferred by the ESD pulse with minimal change in VP. Typically a value in the 0.1 µF to 0.2 µF range is adequate for
IEC-61000-4-2 level 4 contact discharge protection (8KV). For higher ESD voltages, the bypass capacitor should be
increased accordingly. Ceramic chip capacitors mounted with short printed circuit board traces are good choices for this
application. Electrolytic capacitors should be avoided as they have poor high frequency characteristics. For extra protection,
connect a zener diode in parallel with the bypass capacitor to mitigate the effects of the parasitic series inductance
inherent in the capacitor. The breakdown voltage of the zener diode should be slightly higher than the maximum supply
voltage.
As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected
electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the VP pin of the
Protection Array as possible, with minimum PCB trace lengths to the power supply and ground planes to minimize stray
series inductance.
©1999 California Micro Devices Corp. All rights reserved.
11/99
3
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
相关型号：
PACDN004Y
Trans Voltage Suppressor Diode, Bidirectional, 2 Element, Silicon, SOT-143, 4 PIN
CALMIRCO
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