BCM8705LAKFBG [BOARDCOM]
SERIAL 10-GBE/FIBRE CHANNEL TRANSCEIVER WITH WIS LAYER AND XAUI⢠INTERFACE; 串行10 - GBE /光纤信道与WIS层与XAUIâ ?? ¢接口收发器
| 型号： | BCM8705LAKFBG |
| 厂家： | 
Broadcom Corporation. |
| 描述： | SERIAL 10-GBE/FIBRE CHANNEL TRANSCEIVER WITH WIS LAYER AND XAUI⢠INTERFACE |
| 文件： | 总2页 (文件大小：99K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BCM8705
®
SERIAL 10-GBE/FIBRE CHANNEL TRANSCEIVER WITH WIS LAYER AND
XAUI™ INTERFACE
S U M M A R Y O F B E N E F I T S
F E A T U R E S
•
•
•
Fully integrated CMU, CDR, SerDes, limiting amplifier,
EyeOpener®, and 4-lane XAUI™ interface
Best performance for LAN (10-GbE) and WAN (OC-192
SONET) application
•
PMD interface supported serial rates: 9.953/10.3125/
10.5188-Gbps
Universal design for 10-GbE, SONET, and 10 GFC for
XENPAK/X2 module
•
•
•
Receive equalization on XAUI and 10G serial interfaces
Transmit pre-emphasis and amplitude control on XAUI interface
10G PMD interface phase and decision threshold adjust
•
Compliant to XENPAK/X2 3.0 and XPAK MSA optical
module standards
•
WIS layer for EOS/WAN applications
•
Integrated and compact design allows for high-density line
card applications
• SONET performance monitoring
Supports Broadcom’s StrataXGS® Ethernet switches service
•
•
•
Upgrade path for existing Broadcom LAN PHY transceivers
aware flow control (SAFC) protocol
Build-in features reduce external components
• Meets and exceeds industry standard
•
•
•
Clean-up PLL
2.5V voltage regulator output
In-rush current limits
•
IEEE 802.3™ae serial Ethernet transceiver (LAN/WAN PHY),
MDIO Clause 45 management interface with extended indirect
address register access
•
•
•
10-Gigabit Fibre Channel draft, rev 3.0
Support for XFP/XFI interfaces
Support for XENPAK/X2 3.0 and XPAK MSA optical module
standards
A P P L I C A T I O N S
•
Additional features
•
•
•
•
•
•
•
Jumbo packets support in WAN mode
XENPAK, X2, XPAK modules
Interface to XFP modules
LAN/MAN/WAN switch/routers
Hubs and repeaters
Reference clock output for XFP module reference clock
I2C master to control XFP module from device
Staged power-up mode to minimize in-rush current
Loopback modes supporting IEEE standards modes
Built-in self-test (BIST) and PRBS generator/checker
•
•
•
•
• Pin-compatible with the BCM8704
Network interface cards (NICs)
•
•
Low power: LAN mode 900 mW, WAN mode 1.0W to 1.1W
Available in 13-mm x 13-mm and 17-mm x 17-mm plastic BGA
(Pb-free version also available)
BCM8705 Block Diagram
XAUI
BCM8705
OTX
ORX
9.953/10.3125/10.5188
Gbps
RS
Media
Access
Controller
Interface
MAC
Optical
PMD
MDC MDIO
Management
Interface
EEPROM
O V E R V I E W
System/MAC Interface
Line/Fiber-Optic Module Interface
AC-coupled
XAUI
outputs
Differential CML
X[A:D]OP/N
X[A:D]IP/N
10G Serial
Inputs
internally biased
differential CML
PDIP/N
AC-coupled
internally biased
differential CML
XAUI
inputs
PPDOUT
XPDOUT
PCOP/N
PDOP/N
10G Serial
Outputs
Differential CML
External VCXO
PEXTCLKP/N
XEXTCLKP/N
PVCOXP/N
AC-coupled
internally biased
differential LVPECL
SYSRSTB
RSTB
MDC
MDIO
PRTAD[4:0]
VCPCDR
VCNCDR
CDR Loop
Filter
PMD Analog
CMOS
XAUI
Control
and
Status
PLOSB/A1
PMD
PCDRLK
PCMULK
OPTXENB0/1
OPTXRST0/1
OPRXLOS
OPBIASFLT
OPTMPFLT
OPPWFLT
OPTXFLT
REFCLKOUT
Optics
Control
and
2WENB
CONFIG[1:0]
CMOS
Status
LASI
TXONOFF
OPRXFLT
OPOUTLVL
OPINLVL
SDA
SCL
2-Wire
interface
CMOS
TRSTB
JTCK
TMS
JTAG
TDI
TDO
BCM8705 Fully Integrated Interface
The BCM8705 Ethernet/Fibre Channel/SONET LAN/WAN PHY is a
fully integrated serialization/deserialization (9.953/10.3125/
10.5188-Gbps) interface device performing the extension functions for a
10-gigabit serial Ethernet reconciliation sublayer (RS) interface. The
XGXS, PCS, and PMA functions include 8B/10B coding, 64B/66B
coding, SerDes, WIS, clock multiplication unit (CMU), and clock and
data recovery (CDR).
On-chip clock synthesis is performed by the high-frequency low-jitter
phase-locked loops for the PMD and XAUI output retimers. Individual
PMD and XAUI clock recovery is performed on the device by
synchronizing directly to their respective incoming data streams. Elastic
buffers are provided to allow the XAUI and PMD interfaces to operate
in asynchronous configuration. Only an external 155.52/156.25/
159.38-MHz oscillator is required for the reference clock input.
For WAN applications, a WIS-compliant framer with flexible clocking
modes allows transmission of Ethernet traffic over a WAN network.
The BCM8705 is available in a 13-mm × 13-mm, 256-pin FBGA with a
0.8-mm ball pitch and also in a 17-mm x 17-mm, 256-pin 1-mm ball
pitch RoHS-compliant package.
Broadcom®, the pulse logo, Connecting everything®, the Connecting everything logo, EyeOpener®,
and StrataXGS® are among the trademarks of Broadcom Corporation and/or its affiliates in the United
States, certain other countries and/or the EU. Any other trademarks or trade names mentioned are the
property of their respective owners.
®
BROADCOM CORPORATION
16215 Alton Parkway, P.O. Box 57013
Irvine, California 92619-7013
Phone: 949-450-8700
Fax: 949-450-8710
E-mail: info@broadcom.com
Web: www.broadcom.com
© 2006 by BROADCOM CORPORATION. All rights reserved.
8705-PB02-R
04/17/06
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