BCM8727BIFBG [BOARDCOM]
DUAL-CHANNEL 10-GBE SFI-TO-XAUI⢠TRANSCEIVER WITH EDC; 双通道10 - GBE SFI- TO- XAUIâ ?? ¢收发器和EDC
| 型号： | BCM8727BIFBG |
| 厂家： | 
Broadcom Corporation. |
| 描述： | DUAL-CHANNEL 10-GBE SFI-TO-XAUI⢠TRANSCEIVER WITH EDC |
| 文件： | 总2页 (文件大小：129K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BCM8727
®
Brief
DUAL-CHANNEL 10-GBE SFI-TO-XAUI™ TRANSCEIVER WITH EDC
S U M M A R Y O F B E N E F I T S
F E A T U R E S
Dual-channel SFI-to-XAUI™ transceiver
Single-reference clock input enables use of low-cost 156.25
MHz oscillator.
•
•
•
Integrated microcontroller and AGC with a wide dynamic
range
Supports low-cost SFP+ copper twin-ax up to 15m
•
•
Supports SFP+ SR, LR, and LRM optical interfaces and up to
15m of direct attached copper
LRM mode supports 300m of Multimode Fiber (MMF),
exceeding the IEEE 802.3aq standard.
•
•
•
•
Programmable amplitude control on 10G serial transmitter
interface
PMD transmit preemphasis for flexible placement of Physical
Layer (PHY)
•
•
•
Standard two-wire Broadcom Serial Interface (BSC) support
for external E2, XFP, SFP, SFP+
Support for module present detection and configuring of
BCM8727 accordingly
MDIO interface compliant to IEEE802.3ae Clause 45 with
extended indirect address register access
Multirate 10 GbE and 1 GbE support for legacy interfaces
Support for XFP/XFI interfaces
•
•
A P P L I C A T I O N S
Physical Medium Dependent (PMD) interface: serial 10.3125
Gbps CML
High-density Ethernet Switching and Routing Platforms
Next-generation Blade Servers
•
•
•
•
PCS 64B/66B scrambler/descrambler
XGXS 8B/10B error detection ENDEC
XAUI link synchronization/deskew
•
•
•
•
•
•
•
•
SFP+ optical SR, LR, and LRM modules
SFP+ copper twin-ax
4-lane XAUI interface (3.125 Gbps)
Built-In Self-Test (BIST) on 10G serial and XAUI interfaces
Power dissipation: 2.4W
Core supply—1.0V, I/O—3.3V
Small 19 mm x 19 mm BGA package, 1-mm ball pitch
BCM8727 Functional Block Diagram
BCM8727
10.3125
Gbps
SFI 1
SFP+
SFP+
XAUI Interface 1
XAUI Interface 2
LRM-
EDC
MAC/
Switch
10.3125
Gbps
SFI 2
LRM-
EDC
MDC MDIO
Management
Interface
O V E R V I E W
XAOP
XAON
8B/10B
Encoder
Serializer
Serializer
64/66B
PDIP
PDIN
MMF EDC
DSP Core
Synchronizer
Descrambler
Decoder
CDR and
Deserializer
AGC
XDOP
XDON
8B/10B
Encoder
322.26M
312.5M
156.25M
CMU
156.25 MHz
REFCK
RefClk
Block
REFCLKP
REFCLKN
32K
ROM
uC
SPI
312.5M
16K
RAM
312.5M
SP
I
Sync. Detect
Lane Sync
8B/10B
Lane
Alignment
FIFO
XAIP
XAIN
DLL and
Deserializer
322.26M
Decoder
64/66B
Encoder
Scrambler
PDOP
PDON
CMU and
Serializer
Sync. Detect
Lane Sync
8B/10B
Lane
Alignment
FIFO
XDIP
XDIN
DLL and
Deserializer
Decoder
XAOP
XAON
8B/10B
Encoder
Serializer
Serializer
64/66B
PDIP
PDIN
MMF EDC
DSP Core
Synchronizer
Descrambler
Decoder
CDR and
Deserializer
AGC
XDOP
XDON
8B/10B
Encoder
322.26M
312.5M
156.25M
CMU
REFCK RefClk
Block
32K
ROM
uC
SPI
312.5M
16K
RAM
312.5M
SPI
Sync. Detect
Lane Sync
8B/10B
Lane
Alignment
FIFO
XAIP
XAIN
DLL and
Deserializer
322.26M
Decoder
64/66B
Encoder
Scrambler
PDOP
PDON
CMU and
Serializer
Sync. Detect
Lane Sync
8B/10B
Lane
Alignment
FIFO
XDIP
XDIN
DLL and
Deserializer
Decoder
MDIO
MDC
PRTAD[4:1]
Management
and
Control
Interface
RSTB
LASI
OPRXLOS
BSC Serial
Interface
SDA
SCL
Optics
Control
and
MOD
_ABS
OPTXENB
OPRSTB
Status
JTAG
BCM8727 Block Diagram
The BCM8727 is a dual-channel 10-GbE SFI-to-XAUI transceiver that
incorporates an Electronic Dispersion Compensation (EDC) equalizer
supporting SFP+ line-card applications.
On-chip clock synthesis is performed by the high-frequency, low-jitter,
Phase-Locked Loops (PLLs) for the PMD and XAUI output retimers.
Individual PMD and XAUI clock recovery is performed on the device by
synchronizing directly to the respective incoming data streams. An
external 156.25 MHz reference clock input is required for each port.
The BCM8727 is a multirate PHY targeted for SMF, MMF, or copper
twin-ax applications interfacing to both limiting-based and linear-based
SFP+ and SFP modules. The BCM8727 is fully compliant to the 10-GbE
IEEE 802.3aq standard and also supports 1000BASE-X for 1-GbE
operation.
The BCM8727 Ethernet LRM PHY device is a fully integrated SerDes
(10.3125 Gbps) interface device performing the extension functions for
a 10-Gigabit serial Ethernet Reconciliation Sublayer (RS) interface. The
XGXS, PCS, and PMA functions include 8B/10B coding, 64B/66B
coding, SerDes, Clock Multiplication Unit (CMU), and Clock and Data
Recovery (CDR).
The BCM8727 is developed using an all-DSP high-speed front-end
providing the highest performance and most flexibility for line-card
designers. An on-chip microcontroller implements the control algorithm
for the DSP core.
The BCM8727 is available in a 19 mm x 19 mm, 1 mm pitch, 324-pin
BGA, RoHS-compliant package. The BCM8727 supports a footprint-
compatible layout with the BCM8726 dual LRM PHY.
Broadcom®, the pulse logo, Connecting everything®, and the Connecting everything logo are among
the trademarks of Broadcom Corporation and/or its affiliates in the United States, certain other countries
and/or the EU. Any other trademarks or trade names mentioned are the property of their respective
owners.
®
BROADCOM CORPORATION
5300 California Avenue
Phone: 949-926-5000
Fax: 949-926-5203
Irvine, California 92617
© 2009 by BROADCOM CORPORATION. All rights reserved.
E-mail: info@broadcom.com
Web: www.broadcom.com
8727-PB00-R
03/16/09
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