BCM8706 [BOARDCOM]

XAUI TO SERIAL 10G BASE-LRM TRANSCEIVER; XAUI串行10G BASE- LRM收发器
BCM8706
型号: BCM8706
厂家: Broadcom Corporation.    Broadcom Corporation.
描述:

XAUI TO SERIAL 10G BASE-LRM TRANSCEIVER
XAUI串行10G BASE- LRM收发器

文件: 总2页 (文件大小:154K)
中文:  中文翻译
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BCM8706  
®
XAUI™ TO SERIAL 10G BASE-LRM TRANSCEIVER  
S U M M A R Y O F B E N E F I T S  
F E A T U R E S  
Meets and exceeds industry standard  
MDIO interface compliant to IEEE 802.3ae Clause 45 with extended  
indirect address register access  
IEEE 802.3ae  
IEEE802.3aq  
Single reference clock input, enables use of low-cost 25-MHz crystal  
or 156.25-MHz oscillator.  
High-performance mode supports 300m of MMF fiber.  
Low-power mode supports 220m of MMF, as specified in the 802.3aq  
standard.  
Integrated micro-controller, no external memory required  
Support for XENPAK/X2 3.0 and XPAK MSA Optical Module  
standards and the emerging SFP+ standard  
Integrated AGC with a dynamic range of 60 mV–700 mV  
Multiple interface support  
Simplifies manufacturability with integrated built-in self test (BIST)  
and loopback modes on the 10-G serial and XAUI interfaces.  
4 Lane XAUI™ (3.125 Gbps)  
XFP/XFI  
2
Programmable amplitude control on 10G serial transmitter  
PMD  
Standard I C serial interface support for external E2 and XFP.  
-
Serial 10.3125-Gbps CML  
XAUI link synchronization/deskew  
XGXS 8B/10B error detection ENDEC  
PCS 64B/66B scrambler/descrambler  
Receive equalization on XAUI and 10G serial interfaces  
Power dissipation: < 1.5W (Low-power mode)  
Core Supply: 1.0V; I/O: 3.3V  
Reference clock output for XFP module reference clock  
Loss-of-signal detection  
A P P L I C A T I O N S  
XENPAK, X2 Modules for LRM  
Direct attach to SFP+ modules  
Network interface cards (NICs)  
Link activity indicator outputs  
XAUI transmit pre-emphasis for transmission over backplanes  
BCM8706 Functional Block Diagram  
XAUI  
OTX  
RS  
XGXS  
10.3125  
Gbps  
Media  
Access  
Controller  
Interface  
BCM8706  
MAC  
ORX  
MMF EDC  
REFCLK  
25M or  
156.25M  
2
MDC MDIO  
I C  
Optical PMD  
E2  
Management  
Interface  
O V E R V I E W  
BCM8706  
XAOP  
XAON  
8B/10B  
Serializer  
Serializer  
Encoder  
PDIP  
PDIN  
64/66B  
Synchronizer  
Descrambler  
Decoder  
CDR and  
Deserializer  
MMF EDC  
DSP Core  
AGC  
XDOP  
XDON  
8B/10B  
Encoder  
322.26M  
312.5M  
uC  
8K ROM  
8K RAM  
156.25M  
CMU  
SPI  
SPI  
25 MHz,  
156.25 MHz  
REFCLKP  
REFCLKN  
RefClk  
Block  
312.5M  
312.5M  
322.26M  
Lane  
Alignment  
FIFO  
Sync. Detect  
Lane Sync  
8B/10B  
DLL and  
De-serializer  
XAIP  
XAIN  
64/66B  
Synchronizer  
Descrambler  
Decoder  
Decoder  
PDOP  
PDON  
CMUR and  
Serializer  
Lane  
Alignment  
FIFO  
Sync. Detect  
Lane Sync  
8B/10B  
DLL and  
De-serializer  
XDIP  
XDIN  
Decoder  
MDIO  
MDC  
PRTAD[4:0]  
RSTB  
Management  
and  
Control  
Interface  
OPRXLOS  
OPTMPFLT  
OPBIASFLT  
OPPWFLT  
LASI  
Optics  
Control  
and  
XAUI BIST Generator  
PMD BIST Generator  
XAUI BIST Checker  
PMD BIST Checker  
PRBS Genertor and Checker  
SDA  
SCL  
I2C Serial  
Interface  
Status  
OPTXENB  
OPRSTB  
JTAG  
BCM8706 Reference Design  
The BCM8706 incorporates a receive equalizer that supports Electronic  
Dispersion Compensation (EDC) over multimode fiber (MMF). The  
EDC equalizer is designed for applications over MMF covering  
distances up to 220m of OM1, OM2, OM3 fiber as per the IEEE  
standard. The BCM8706 will be fully compliant with the IEEE802.3aq  
standard. In enhanced performance mode, the BCM8706 is capable of  
supporting up to 300m over OM1, OM2, and OM3 fiber.  
PMD and XAUI clock recovery is performed on the device by  
synchronizing directly to the respective incoming data streams. An  
external 25-MHz or 156.25-MHz oscillator is required for the reference  
clock input.  
The BCM8706 Ethernet LRM PHY is a fully integrated SerDes (10.3125  
Gbps) interface device performing the extension functions for a 10-GbE  
Reconciliation Sublayer (RS) interface. The XGXS, PCS, and PMA  
functions include 8B/10B coding, 64B/66B coding, SerDes, Clock  
Multiplication Unit (CMU), and Clock and Data Recovery (CDR).  
An onboard microcontroller implements the control algorithm for the  
MMF EDC DSP Core.  
On-chip clock synthesis is performed by the high-frequency low-jitter  
phase-locked loops for the PMD and XAUI output retimers. Individual  
The BCM8706 is available in a 13 mm × 13 mm, 256-pin FBGA, RoHS  
compliant package.  
Broadcom®, the pulse logo, Connecting everything®, and the Connecting everything logo are among  
the trademarks of Broadcom Corporation and/or its affiliates in the United States, certain other countries  
and/or the EU. Any other trademarks or trade names mentioned are the property of their respective  
owners.  
®
BROADCOM CORPORATION  
16215 Alton Parkway, P.O. Box 57013  
Irvine, California 92619-7013  
Phone: 949-450-8700  
Fax: 949-450-8710  
E-mail: info@broadcom.com  
Web: www.broadcom.com  
© 2006 by BROADCOM CORPORATION. All rights reserved.  
8706-PB00-R  
05/16/06  

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