OPA820IDR [BB]
Unity-Gain Stable, Low-Noise, Voltage-Feedback Operational Amplifier; 单位增益稳定，低噪声，电压反馈运算放大器
| 型号： | OPA820IDR |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | Unity-Gain Stable, Low-Noise, Voltage-Feedback Operational Amplifier |
| 文件： | 总25页 (文件大小：425K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA820
SBOS303A − JUNE 2004 − REVISED JULY 2004
Unity-Gain Stable, Low-Noise, Voltage-Feedback
Operational Amplifier
FD EATURES
DESCRIPTION
HIGH BANDWIDTH (240MHz, G = +2)
The OPA820 provides a wideband, unity-gain stable,
voltage-feedback amplifier with a very low input noise voltage
and high output current using a low 5.6mA supply current. At
unity-gain, the OPA820 gives > 800MHz bandwidth with < 1dB
peaking. The OPA820 complements this high-speed
operation with excellent DC precision in a low-power device.
A worst-case input offset voltage of 750µV and an offset
current of 400nA give excellent absolute DC precision for
pulse amplifier applications.
D
D
D
D
HIGH OUTPUT CURRENT ( 110mA)
LOW INPUT NOISE (2.5nV/√Hz)
LOW SUPPLY CURRENT (5.6mA)
FLEXIBLE SUPPLY VOLTAGE
Dual 2.5V to 6V
Single +5V to +12V
D
EXCELLENT DC ACCURACY
Maximum 25°C Input Offset Voltage = 750µV
Maximum 25°C Input Offset Current = 400nA
Minimal input and output voltage swing headroom allow the
OPA820 to operate on a single +5V supply with > 2V output
swing. While not a rail-to-rail (RR) output, this swing will
support most emerging analog-to-digital converter (ADC)
input ranges with lower power and noise than typical RR
output op amps.
PP
AD PPLICATIONS
LOW-COST VIDEO LINE DRIVERS
Exceptionally low dG/dP (0.01%/0.03°) supports low-cost
composite video line driver applications. Existing designs can
use the industry-standard pinout SO-8 package while
emerging high-density portable applications can use the
SOT23-5. Offering the industry’s lowest thermal impedance in
a SOT package, along with full specification over both the
commercial and industrial temperature ranges, gives solid
performance over a wide temperature range.
D
D
D
D
D
D
D
D
ADC PREAMPLIFIERS
ACTIVE FILTERS
LOW-NOISE INTEGRATORS
PORTABLE TEST EQUIPMENT
OPTICAL CHANNEL AMPLIFIERS
LOW-POWER, BASEBAND AMPLIFIERS
CCD IMAGING CHANNEL AMPLIFIERS
OPA650 AND OPA620 UPGRADE
RELATED PRODUCTS
SINGLES
DUALS
TRIPLES
QUADS
FEATURES
OPA354
OPA690
—
OPA2354
OPA2690
OPA2652
OPA2822
—
—
OPA4354 CMOS RR Output
OPA3690
—
—
—
High Slew Rate
SOT23-8
—
—
—
—
Low Noise
—
OPA4820 Quad OPA820
+5V
+5V
REFT
(+3V)
2kΩ
2kΩ
2kΩ
RS
24.9
0.1µF
VIN
Ω
IN
IN
OPA820
Ω
50
100pF
ADS850
14−Bit
10MSPS
−5V
402Ω
0.1µF
402Ω
(+2V) (+1V)
REFB VREF
2kΩ
SEL
AC-Coupled, 14-Bit ADS850 Interface
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆꢇ ꢂꢈ ꢃ ꢉꢆꢉ ꢊꢋ ꢌꢍ ꢎ ꢏꢐ ꢑꢊꢍꢋ ꢊꢒ ꢓꢔ ꢎ ꢎ ꢕꢋꢑ ꢐꢒ ꢍꢌ ꢖꢔꢗ ꢘꢊꢓ ꢐꢑꢊ ꢍꢋ ꢙꢐ ꢑꢕꢚ ꢀꢎ ꢍꢙꢔ ꢓꢑꢒ
ꢓ ꢍꢋ ꢌꢍꢎ ꢏ ꢑꢍ ꢒ ꢖꢕ ꢓ ꢊ ꢌꢊ ꢓ ꢐ ꢑꢊ ꢍꢋꢒ ꢖ ꢕꢎ ꢑꢛꢕ ꢑꢕ ꢎ ꢏꢒ ꢍꢌ ꢆꢕꢜ ꢐꢒ ꢇꢋꢒ ꢑꢎ ꢔꢏ ꢕꢋꢑ ꢒ ꢒꢑ ꢐꢋꢙ ꢐꢎ ꢙ ꢝ ꢐꢎ ꢎ ꢐ ꢋꢑꢞꢚ
ꢀꢎ ꢍ ꢙꢔꢓ ꢑ ꢊꢍ ꢋ ꢖꢎ ꢍ ꢓ ꢕ ꢒ ꢒ ꢊꢋ ꢟ ꢙꢍ ꢕ ꢒ ꢋꢍꢑ ꢋꢕ ꢓꢕ ꢒꢒ ꢐꢎ ꢊꢘ ꢞ ꢊꢋꢓ ꢘꢔꢙ ꢕ ꢑꢕ ꢒꢑꢊ ꢋꢟ ꢍꢌ ꢐꢘ ꢘ ꢖꢐ ꢎ ꢐꢏ ꢕꢑꢕ ꢎ ꢒꢚ
Copyright 2004, Texas Instruments Incorporated
www.ti.com
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SBOS303A − JUNE 2004 − REVISED JULY 2004
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
(1)
ABSOLUTE MAXIMUM RATINGS
handledwith appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V
DC
Internal Power Dissipation . . . . . . . . . . . . See Thermal Information
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2V
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
Input Common-Mode Voltage Range . . . . . . . . . . . . . . . . . . . .
V
S
Storage Temperature Range . . . . . . . . . . . . . . . . . −40°C to +125°C
Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300°C
Junction Temperature (T ) . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
J
ESD Rating
Human Body Model (HBM) . . . . . . . . . . . . . . . . . . . . . . +3000V
Charge Device Model (CDM) . . . . . . . . . . . . . . . . . . . . +1000V
Machine Model (MM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300V
(1)
Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not supported.
PACKAGE/ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE-LEAD
(1)
OPA820
SO-8
D
−45°C to +85°C
OPA820
OPA820ID
OPA820IDR
Rails, 100
″
″
″
DBV
″
″
″
NSO
″
Tape and Reel, 2500
Tape and Reel, 250
Tape and Reel, 3000
OPA820
SOT23-5
−45°C to +85°C
OPA820IDBVT
OPA820IDBVR
″
″
″
(1)
For the most current specification and package information, refer to our web site at www.ti.com.
PIN CONFIGURATION
Top View
SO
Top View
SOT
Output
+VS
1
2
3
5
4
−
VS
Noninverting Inut
Inverting Input
NC
Inverting Input
NC
1
2
3
4
8
7
6
5
+VS
Output
NC
Noninverting Input
−
VS
NC = No Connection
NSO
Pin Orientation/Package Marking
2
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SBOS303A − JUNE 2004 − REVISED JULY 2004
ELECTRICAL CHARACTERISTICS: V = 5V
S
Boldface limits are tested at +25°C.
R
F
= 402Ω, R = 100Ω, and G = +2, unless otherwise noted.
L
OPA820ID, IDBV
MIN/MAX OVER TEMPERATURE
TYP
TEST
LEVEL
(3)
0°C to
70°C
−40°C to
+85°C
MIN/
MAX
(2)
(2)
(1)
+25°C
+25°C
PARAMETER
CONDITIONS
UNITS
AC PERFORMANCE
Small-Signal Bandwidth
G = +1, V = 0.1V , R = 0Ω
800
240
30
MHz
MHz
MHz
MHz
MHz
dB
typ
min
min
min
typ
typ
typ
min
typ
typ
typ
C
B
B
B
C
C
C
B
C
C
C
O
PP
F
G = +2, V = 0.1V
170
23
160
21
155
20
O
PP
G = +10, V = 0.1V
O
PP
Gain-Bandwidth Product
Bandwidth for 0.1dB Gain Flatness
Peaking at a Gain of +1
Large-Signal Bandwidth
Slew Rate
G ≥ 20
280
38
220
204
200
G = +2, V = 0.1V
O
PP
V
O
= 0.1V , R = 0
0.5
85
PP
F
G = +2, V = 2V
MHz
V/µs
ns
O
PP
G = +2, 2V Step
G = +2, V = 0.2V Step
240
1.5
22
192
186
180
Rise Time and Fall Time
Settling Time to 0.02%
to 0.1%
O
G = +2, V = 2V Step
ns
O
G = +2, V = 2V Step
18
ns
O
Harmonic Distortion
2nd-Harmonic
G = +2, f = 1MHz, V = 2V
O PP
R
L
R
L
R
L
R
L
= 200Ω
≥ 500Ω
= 200Ω
≥ 500Ω
−85
−90
−95
−110
2.5
−81
−85
−90
−80
−83
−89
−102
2.8
−79
−81
−88
−100
2.9
dBc
dBc
max
max
max
max
max
max
typ
B
B
B
B
B
B
C
C
3rd-Harmonic
dBc
−105
2.7
dBc
Input Voltage Noise
Input Current Noise
Differential Gain
f > 100kHz
nV/√Hz
pA/√Hz
%
f > 100kHz
1.7
2.6
2.8
3.0
G = +2, PAL, V = 1.4V , R = 150Ω
0.01
0.03
O
PP
L
Differential Phase
G = +2, PAL, V = 1.4V , R = 150Ω
°
typ
O
PP
L
(4)
DC PERFORMANCE
Open-Loop Voltage Gain (A
Input Offset Voltage
)
V
O
= 0V, Input-Referred
66
62
61
1.0
4
60
1.2
4
dB
mV
min
max
max
max
max
max
max
A
A
B
A
B
A
B
OL
V
CM
V
CM
V
CM
V
CM
V
CM
V
CM
= 0V
= 0V
= 0V
= 0V
= 0V
= 0V
0.2
0.75
Average Input Offset Voltage Drift
Input Bias Current
µV/°C
µΑ
nA/°C
nA
−9
−17
400
−19
30
600
5
−23
50
700
5
Average Input Bias Current Drift
Input Offset Current
100
Inverting Input Bias Current Drift
INPUT
nA/°C
(5)
Common-Mode Input Range (CMIR)
4.0
85
3.8
76
3.7
75
3.6
73
V
min
min
A
A
Common-Mode Rejection Ratio
Input Impedance
V
CM
= 0V, Input-Referred
dB
Differential Mode
V
V
= 0V
= 0V
18 0.8
6 1.0
kΩ pF
MΩ pF
typ
typ
C
C
CM
Common Mode
CM
OUTPUT
Output Voltage Swing
No Load
= 100Ω
3.7
3.6
3.5
3.5
90
3.45
3.45
80
3.4
3.4
75
V
V
min
min
min
typ
A
A
A
C
C
R
L
Output Current
V
O
= 0
110
125
0.04
mA
mA
Ω
Short-Circuit Output Current
Closed-Loop Output Impedance
POWER SUPPLY
Output Shorted to Ground
G = +2, f ≤ 100kHz
typ
Specified Operating Voltage
Maximum Operating Voltage
Maximum Quiescent Current
Minimum Quiescent Current
Power-Supply Rejection Ratio (−PSRR)
THERMAL CHARACTERISTICS
Specification: ID, IDBV
5
V
v
typ
max
max
min
min
C
A
A
A
A
6.0
5.75
5.45
64
6.0
6.2
5.0
63
6.0
6.4
4.8
62
V
V
=
=
5V
5V
5.6
5.6
72
mA
mA
dB
S
S
Input Referred
−40 to +85
°C
typ
C
Thermal Resistance, q
JA
D
SO-8
Junction-to-Ambient
Junction-to-Ambient
125
150
°C/W
°C/W
typ
typ
C
C
DBV
SOT23-5
(1)
Junction temperature = ambient for +25°C specifications.
Junction temperature = ambient at low temperature limits; junction temperature = ambient +9°C at high temperature limit for over temperature.
Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only
(2)
(3)
for information.
Current is considered positive out-of-node. V
Tested < 3dB below minimum specified CMRR at CMIR limits.
(4)
(5)
is the input common-mode voltage.
CM
3
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SBOS303A − JUNE 2004 − REVISED JULY 2004
ELECTRICAL CHARACTERISTICS: V = +5V
S
Boldface limits are tested at +25°C.
R
F
= 402Ω, R = 100Ω, and G = +2, unless otherwise noted.
L
OPA820ID, IDBV
TYP
MIN/MAX OVER TEMPERATURE
TEST
LEVEL
(3)
0°C to
70°C
−40°C to
+85°C
MIN/
MAX
(2)
(2)
(1)
+25°C
+25°C
PARAMETER
CONDITIONS
UNITS
AC PERFORMANCE
Small-Signal Bandwidth
G = +1, V = 0.1V , R = 0Ω
550
230
28
MHz
MHz
MHz
MHz
dB
typ
min
min
min
typ
typ
min
typ
typ
typ
C
B
B
B
C
C
B
C
C
C
O
PP
F
G = +2, V = 0.1V
168
21
155
20
151
19
O
PP
G = +10, V = 0.1V
O
PP
Gain-Bandwidth Product
Peaking at a Gain of 1
Large-Signal Bandwidth
Slew Rate
G ≥ 20
260
0.5
70
200
190
185
V
O
= 0.1V , R = 0Ω
PP F
G = +2, V = 2V
MHz
V/µs
ns
O
PP
G = +2, 2V Step
G = +2, V = 2V Step
200
1.7
24
145
140
135
Rise Time and Fall Time
Settling Time to 0.02%
to 0.1%
O
G = +2, V = 2V Step
ns
O
G = +2, V = 2V Step
21
ns
O
Harmonic Distortion
2nd-Harmonic
G = +2, f = 1MHz, V = 2V
O PP
R
L
R
L
R
L
R
L
= 200Ω
≥ 500Ω
= 200Ω
≥ 500Ω
−80
−83
−100
−98
2.5
−76
−79
−92
−95
2.8
−75
−77
−91
−93
2.9
−74
−75
−90
−92
3.0
dBc
dBc
max
max
max
max
max
max
B
B
B
B
B
B
3rd-Harmonic
dBc
dBc
Input Voltage Noise
Input Current Noise
f > 100kHz
nV/√Hz
pA/√Hz
f > 100kHz
1.6
2.5
2.7
2.9
(4)
DC PERFORMANCE
Open-Loop Voltage Gain (A
Input Offset Voltage
)
V
O
= 2.5V, R = 100Ω
65
60
59
1.4
4
58
1.6
4
dB
mV
min
max
max
max
max
max
max
A
A
B
A
B
A
B
OL
L
V
CM
V
CM
V
CM
V
CM
V
CM
V
CM
= 2.5V
= 2.5V
= 2.5V
= 2.5V
= 2.5V
= 2.5V
0.3
1.1
−16
400
Average Input Offset Voltage Drift
Input Bias Current
µV/°C
µΑ
nA/°C
nA
−8
−18
30
600
5
−22
50
700
5
Average Input Bias Current Drift
Input Offset Current
100
Inverting Input Bias Current Drift
nA/°C
INPUT
Least Positive Input Voltage
Most Positive Input Voltage
Common-Mode Rejection Ratio (CMRR)
Input Impedance
0.9
4.5
83
1.1
4.2
74
1.2
4.1
73
1.3
4.0
72
V
V
min
max
min
A
A
A
V
CM
= 2.5V, Input-Referred
dB
Differential Mode
V
V
= 2.5V
= 2.5V
15 1
5 1.3
kΩ pF
MΩ pF
typ
typ
C
C
CM
Common Mode
CM
OUTPUT
Most Positive Output Voltage
No Load
+3.9
+3.8
+1.2
+1.2
105
+3.8
+3.7
+1.3
+1.3
80
+3.75
+3.65
+1.35
+1.35
70
+3.7
+3.6
+1.4
+1.4
65
V
V
min
min
max
max
min
typ
A
A
A
A
A
C
C
R
R
= 100Ω to 2.5V
No Load
L
Least Positive Output Voltage
V
= 100Ω to 2.5V
V
L
Output Current
V
O
= 2.5V
mA
mA
Ω
Short-Circuit Output Current
Closed-Loop Output Impedance
Output Shorted to Ground
115
G = +2, f ≤ 100kHz
0.04
typ
POWER SUPPLY
Specified Operating Voltage
Maximum Operating Voltage
Maximum Quiescent Current
Minimum Quiescent Current
Power-Supply Rejection Ratio (+PSRR)
+5
V
typ
max
max
min
typ
C
A
A
A
C
+12
5.4
4.4
+12
5.5
+12
5.6
4.1
V
V
V
= +5V
= +5V
5.0
5.0
68
mA
mA
dB
S
4.25
S
Input-Referred
THERMAL CHARACTERISTICS
Specification: ID, IDBV
−40 to +85
°C
typ
C
Thermal Resistance, q
JA
D
SO-8
Junction-to-Ambient
Junction-to-Ambient
125
150
°C/W
°C/W
typ
typ
C
C
DBV
SOT23-5
(1)
(2)
(3)
Junction temperature = ambient for +25°C specifications.
Junction temperature = ambient at low temperature limits; junction temperature = ambient +7°C at high temperature limit for over temperature.
Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only
for information.
(4)
(5)
Current is considered positive out-of-node. V
is the input common-mode voltage.
CM
Tested < 3dB below minimum specified CMRR at CMIR limits.
4
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SBOS303A − JUNE 2004 − REVISED JULY 2004
TYPICAL CHARACTERISTICS: V = 5V
S
R
F
= 402Ω, R = 100Ω, and G = +2, unless otherwise noted.
L
NONINVERTING SMALL−SIGNAL FREQUENCY RESPONSE
INVERTING SMALL−SIGNAL FREQUENCY RESPONSE
3
3
0
3
6
9
G = +1
−
G =
G =
1
Ω
RF = 0
0
−
2
G = +5
−
−
−
−
3
6
9
G = +2
−
G =
5
−
−
G = +10
−
G = 10
−
−
−
−
−
−
12
15
18
12
15
18
VO = 0.1VPP
VO = 0.1VPP
Ω
RL = 100
See Figure 1
Ω
RL = 100
See Figure 2
1M
10M
100M
1G
1
10
Frequency (MHz)
100
500
Frequency (Hz)
NONINVERTING LARGE−SIGNAL FREQUENCY RESPONSE
VO = 0.5VPP
INVERTING LARGE−SIGNAL FREQUENCY RESPONSE
VO = 0.5VPP
9
6
3
0
3
0
−
−
−
3
6
9
VO = 1VPP
VO = 2VPP
VO = 1VPP
VO = 2VPP
−
3
6
9
VO = 4VPP
VO = 4VPP
−
−
−
−
12
15
18
G = +2
−
G =
RL = 100
See Figure 2
1
−
Ω
RL = 100
See Figure 1
Ω
−
12
1
10
100
500
1
10
100
500
Frequency (MHz)
Frequency (MHz)
NONINVERTING PULSE RESPONSE
INVERTING PULSE RESPONSE
0.4
0.3
2.0
0.4
0.3
2.0
G = −1
Large Signal 1V
Right Scale
1.5
1.5
See Figure 2
0.2
1.0
0.2
1.0
0.1
0.5
0.1
0.5
Small Signal 100mV
Left Scale
Small Signal 100mV
Left Scale
0
0
0
0
−0.1
−0.2
−0.3
−0.4
−0.5
−1.0
−1.5
−2.0
−0.1
−0.2
−0.3
−0.4
−0.5
−1.0
−1.5
−2.0
Large Signal 1V
Right Scale
G = +2
See Figure 1
Time (10ns/div)
Time (10ns/div)
5
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SBOS303A − JUNE 2004 − REVISED JULY 2004
TYPICAL CHARACTERISTICS: V = 5V (continued)
S
R
F
= 402Ω, R = 100Ω, and G = +2, unless otherwise noted.
L
1MHz HARMONIC DISTORTION vs SUPPLY VOLTAGE
VO = 2VPP
HARMONIC DISTORTION vs LOAD RESISTANCE
−
−
−
−
−
75
80
85
90
95
−
−
−
−
−
−
70
75
80
85
90
95
f = 1MHz
VO = 2VPP
G = +2V/V
Ω
RL = 200
G = +2V/V
2nd−Harmonic
2nd−Harmonic
3rd−Harmonic
3rd−Harmonic
−
−
100
105
See Figure 1
5.5
See Figure 1
−
100
100
2.5
3.0
3.5
4.0
4.5
5.0
6.0
10
10
1k
Supply Voltage ( VS)
Ω
Resistance ( )
HARMONIC DISTORTION vs OUTPUT VOLTAGE
f = 1MHz
HARMONIC DISTORTION vs FREQUENCY
VO = 2VPP
−
−
−
−
−
75
80
85
90
95
−
−
−
−
−
−
−
−
60
65
70
75
80
85
90
95
Ω
RL = 100
G = +2V/V
Ω
RL = 200
2nd−Harmonic
G = +2V/V
2nd−Harmonic
−
−
−
100
105
110
3rd−Harmonic
3rd−Harmonic
−
−
100
105
See Figure 1
0.1
See Figure 1
10
1
0.1
1
Output Voltage (VPP
)
Frequency (MHz)
HARMONIC DISTORTION vs NONINVERTING GAIN
f = 1MHz
HARMONIC DISTORTION vs INVERTING GAIN
f = 1MHz
−
−
−
−
−
−
−
−
−
−
−
−
70
75
80
85
90
95
70
75
80
85
90
95
Ω
Ω
RL = 200
O = 2VPP
RL = 200
VO = 2VPP
V
2nd−Harmonic
2nd−Harmonic
3rd−Harmonic
3rd−Harmonic
−
−
−
100
105
110
See Figure 2
See Figure 1
−
100
1
10
1
| |
Gain ( V/V )
Gain (V/V)
6
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SBOS303A − JUNE 2004 − REVISED JULY 2004
TYPICAL CHARACTERISTICS: V = 5V (continued)
S
R
F
= 402Ω, R = 100Ω, and G = +2, unless otherwise noted.
L
TWO−TONE, 3RD−ORDER
INTERMODULATION INTERCEPT
INPUT VOLTAGE AND CURRENT NOISE
100
50
45
40
35
30
25
20
15
PI
PO
OPA820
Ω
50
Ω
200
Ω
402
Ω
402
10
√
Voltage Noise (2.5nV/ Hz)
√
Current Noise (1.7pA/ Hz)
1
10
100
1k
10k
100k
1M
10M
0
5
10
15
20
25
30
Frequency (Hz)
Frequency (MHz)
RECOMMENDED RS vs CAPACITIVE LOAD
0dB Peaking Targeted
FREQUENCY RESPONSE vs CAPACITIVE LOAD
CL = 10pF
100
10
1
8
7
6
5
4
3
2
1
0
CL = 22pF
CL = 47pF
CL = 100pF
RS
VI
VO
(1)
OPA820
Ω
50
CL
Ω
1k
Ω
402
−
1
2
3
Ω
NOTE: (1) 1k is optional.
Ω
402
−
−
1
10
100
1000
1
10
100
400
Capacitive Load (pF)
Frequency (MHz)
CMRR AND PSRR vs FREQUENCY
CMRR
OPEN−LOOP GAIN AND PHASE
90
80
70
60
50
40
30
20
10
0
80
0
70
60
50
40
30
20
10
0
−20
20 log (AOL
)
−40
−60
+PSRR
−80
∠AOL
−100
−120
−140
−160
−180
−
PSRR
−10
100
1k
10k
100k
1M
10M 100M
1G
1k
10k
100k
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
7
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SBOS303A − JUNE 2004 − REVISED JULY 2004
TYPICAL CHARACTERISTICS: V = 5V (continued)
S
R
F
= 402Ω, R = 100Ω, and G = +2, unless otherwise noted.
L
OUTPUT VOLTAGE AND CURRENT LIMITATIONS
5
CLOSED−LOOP OUTPUT IMPEDANCE vs FREQUENCY
10
1
1W Internal
Output Current
4
3
2
1
0
1
2
3
4
5
Power Limit
Limit
Ω
RL = 100
Ω
RL = 25
Ω
RL = 50
−
−
−
−
−
0.1
0.01
Output Current
Limit
1W Internal
Power Limit
−
−
−
50
150
100
0
IO (mA)
50
100
150
1k
10k
100k
1M
10M
100M
Frequency (Hz)
INVERTING OVERDRIVE RECOVERY
NONINVERTING OVERDRIVE RECOVERY
Input Right Scale
5
4
3
2
1
0
5
4
3
2
1
0
8
6
4
2
0
2
4
6
8
4
3
2
1
0
−
−
−
−
Input
Right Scale
Output Left Scale
Output
Left Scale
−
−
−
−
−
−
−
−
−
−
1
2
3
4
5
1
2
3
4
5
−
−
−
−
1
2
3
4
Ω
RL = 100
Ω
RL = 100
G = +2V/V
See Figure 1
−
G = 1V/V
See Figure 2
Time (40ns/div)
Time (40ns/div)
TYPICAL DC DRIFT OVER TEMPERATURE
COMPOSITE VIDEO dG/dP
dG Negative Video
1.0
0.5
0
20
10
0
0.20
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
0.40
0.36
0.32
0.28
0.24
0.20
0.16
0.12
0.08
0.04
0
G = +2V/V
Right Scale
10x Input Offset Current (IOS)
Input Offset Voltage (VOS
)
dP Negative Video
dP Positive Video
Left Scale
−
−
10
0.5
Input Bias Current (IB)
Right Scale
dG Positive Video
−1.0
−20
125
1
2
3
4
−50
−25
0
25
50
75
100
Video Loads
Ambient Temperature (_C)
8
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SBOS303A − JUNE 2004 − REVISED JULY 2004
TYPICAL CHARACTERISTICS: V = 5V (continued)
S
R
F
= 402Ω, R = 100Ω, and G = +2, unless otherwise noted.
L
COMMON−MODE INPUT RANGE AND OUTPUT SWING
vs SUPPLY VOLTAGE
SUPPLY AND OUTPUT CURRENT vs TEMPERATURE
125
12
9
6
5
4
3
2
1
0
Left Scale
Sink/Source Output Current
100
75
+VIN
−
VIN
6
Supply Current
Right Scale
+VOUT
50
3
−
VOUT
25
0
−
−
25
50
0
25
50
75
100
125
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
_
Ambient Temperature ( C)
Supply Voltage ( VS)
TYPICAL INPUT OFFSET VOLTAGE DISTRIBUTION
COMMON−MODE AND DIFFERENTIAL
INPUT IMPEDANCE
2500
−
µ
Mean = 30 V
10M
1M
µ
Standard Deviation = 80 V
Common−Mode Input Impedance
Total Count = 6115
2000
1500
1000
500
0
100k
10k
1k
Differential Input Impedance
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
µ
Input Offset Voltage ( V)
TYPICAL INPUT OFFSET CURRENT DISTRIBUTION
2000
1800
1600
1400
1200
1000
800
Mean = 26nA
Standard Deviation = 57nA
Total Count = 6115
600
400
200
0
Input Offset Current (nA)
9
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SBOS303A − JUNE 2004 − REVISED JULY 2004
TYPICAL CHARACTERISTICS: V = +5V
S
R
F
= 402Ω, R = 100Ω, and G = +2, unless otherwise noted.
L
NONINVERTING SMALL−SIGNAL FREQUENCY RESPONSE
INVERTING SMALL−SIGNAL FREQUENCY RESPONSE
3
3
0
3
6
9
−
−
G =
G =
1
2
G = +1
0
G = +2
−
−
−
−
−
−
3
6
9
−
G =
5
G = +5
G = +10
−
G = 10
−
−
−
−
−
−
12
15
18
12
15
18
VO = 0.1VPP
VO = 0.1VPP
Ω
Ω
RL = 100
RL = 100
See Figure 4
See Figure 3
1M
10M
100M
1G
1
10
Frequency (MHz)
100
500
Frequency (Hz)
NONINVERTING LARGE−SIGNAL FREQUENCY RESPONSE
VO = 0.5VPP
INVERTING LARGE−SIGNAL FREQUENCY RESPONSE
VO = 0.5VPP
9
6
3
0
3
0
VO = 1VPP
−
−
−
3
6
9
VO = 2VPP
VO = 1VPP
VO = 2VPP
VO = 4VPP
VO = 4VPP
−
3
6
9
−
−
−
−
12
15
18
−
G =
RL = 100
See Figure 4
1
G = +2V/V
Ω
−
Ω
RL = 100
See Figure 3
−
12
1
10
100
600
1
10
100
500
Frequency (MHz)
Frequency (MHz)
NONINVERTING PULSE RESPONSE
INVERTING PULSE RESPONSE
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
4.5
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
4.5
G = −1
Large Signal 1V
Right Scale
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
See Figure 4
Small Signal 100mV
Left Scale
Small Signal 100mV
Left Scale
Large Signal 1V
Right Scale
G = +2
See Figure 3
Time (10ns/div)
Time (10ns/div)
10
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SBOS303A − JUNE 2004 − REVISED JULY 2004
TYPICAL CHARACTERISTICS: V = +5V (continued)
S
R
F
= 402Ω, R = 100Ω, and G = +2, unless otherwise noted.
L
HARMONIC DISTORTION vs LOAD RESISTANCE
HARMONIC DISTORTION vs FREQUENCY
−
−
−
−
−
−
−
−
−
75
80
85
90
95
60
70
80
90
f = 1MHz
VO = 2VPP
G = +2V/V
G = +2V/V
2nd−Harmonic
2nd−Harmonic
Ω
RL = 200
V
O = 2VPP
3rd−Harmonic
3rd−Harmonic
−
−
100
110
−
−
100
See Figure 3
See Figure 3
0.1
105
100
1k
10
10
1
10
Ω
Resistance ( )
Frequency (MHz)
HARMONIC DISTORTION vs OUTPUT VOLTAGE
VO = 2VPP
HARMONIC DISTORTION vs NONINVERTING GAIN
f = 1MHz
−
−
−
70
80
90
−
−
−
−
60
70
80
90
f = 1MHz
G = +2V/V
Ω
RL = 200
O = 2VPP
2nd−Harmonic
V
2nd−Harmonic
Ω
RL = 200
3rd−Harmonic
3rd−Harmonic
−
−
100
110
−
−
100
110
See Figure 3
0.1
See Figure 3
1
Output Voltage Swing (VPP
1
10
)
Gain (V/V)
TWO−TONE, 3RD−ORDER
HARMONIC DISTORTION vs INVERTING GAIN
f = 1MHz
INTERMODULATION INTERCEPT
−
−
−
−
−
−
70
75
80
85
90
95
40
35
30
25
20
15
+5V
Ω
RL = 200
O = 2VPP
Ω
Ω
806
806
µ
0.01
F
PI
V
PO
OPA820
Ω
57.6
2nd−Harmonic
200Ω
Ω
402
Ω
402
0.01µF
3rd−Harmonic
See Figure 4
−
100
1
0
5
10
15
20
25
30
|
|
Gain ( V/V )
Frequency (MHz)
11
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SBOS303A − JUNE 2004 − REVISED JULY 2004
TYPICAL CHARACTERISTICS: V = +5V (continued)
S
R
F
= 402Ω, R = 100Ω, and G = +2, unless otherwise noted.
L
RECOMMENDED RS vs CAPACITIVE LOAD
FREQUENCY RESPONSE vs CAPACITIVE LOAD
CL = 10pF
100
8
7
6
5
4
3
2
1
0
1
2
3
0dB Peaking Targeted
CL = 22pF
CL = 47pF
CL = 100pF
10
+5V
806Ω
µ
F
0.01
RS
V
I
VO
(1)
OPA820
57.6Ω
Ω
806
CL
1kΩ
402Ω
−
−
−
NOTE: (1) 1kΩis optional.
402Ω
µ
0.01
F
1
1
10
100
1000
1
10
100
300
Capacitive Load (pF)
Frequency (MHz)
SUPPLY AND OUTPUT CURRENT vs TEMPERATURE
TYPICAL DC DRIFT OVER TEMPERATURE
125
100
75
12
9
1.5
1.0
15
10
5
10x Input Offset Current (IOS
)
Source Output Current
Sink Output Current
0.5
Right Scale
6
0
0
Input Offset Voltage (VOS
)
Left Scale
Supply Current
−0.5
−1.0
−1.5
−5
−10
−15
50
3
Input Bias Current (IB)
Right Scale
25
0
125
−50
−25
0
25
50
75
100
125
−
−
25
50
0
25
50
75
100
Ambient Temperature (_C)
_
Ambient Temperature ( C)
TYPICAL INPUT OFFSET VOLTAGE DISTRIBUTION
TYPICAL INPUT OFFSET CURRENT DISTRIBUTION
3500
3000
2500
2000
1500
1000
500
2000
1800
1600
1400
1200
1000
800
−
µ
µ
Mean = 490 V
Mean = 43nA
Standard Deviation = 50nA
Total Count = 6115
Standard Deviation = 90 V
Total Count = 6115
600
400
200
0
0
Input Offset Voltage (mV)
Input Offset Current (nA)
12
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SBOS303A − JUNE 2004 − REVISED JULY 2004
+5V
APPLICATIONS INFORMATION
WIDEBAND VOLTAGE-FEEDBACK
OPERATION
+
µ
µ
0.1 F
2.2 F
The combination of speed and dynamic range offered by the
OPA820 is easily achieved in a wide variety of application
circuits, providing that simple principles of good design
practice are observed. For example, good power-supply
decoupling, as shown in Figure 1, is essential to achieve the
lowest possible harmonic distortion and smooth frequency
response.
50Ω Load
Ω
50
VO
RT
205Ω
µ
OPA820
0.01 F
RG
402Ω
RF
402Ω
50Ω Source
VI
Proper PC board layout and careful component selection will
maximize the performance of the OPA820 in all applications,
as discussed in the following sections of this data sheet.
RM
57.6
Ω
0.1µF
2.2µF
+
Figure 1 shows the gain of +2 configuration used as the basis
for most of the typical characteristics. Most of the curves were
characterized using signal sources with 50Ω driving
impedance and with measurement equipment presenting
50Ω load impedance. In Figure 1, the 50Ω shunt resistor at the
−
5V
Figure 2. Inverting G = −1 Specifications and Test
Circuit
V
terminal matches the source impedance of the test
I
In the inverting case, just the feedback resistor appears as
part of the total output load in parallel with the actual load. For
the 100Ω load used in the typical characteristics, this gives a
total load of 80Ω in this inverting configuration. The gain
resistor is set to get the desired gain (in this case 402Ω for a
generator while the 50Ω series resistor at the V terminal
provides a matching resistor for the measurement equipment
load. Generally, data sheet specifications refer to the voltage
O
swings at the output pin (V in Figure 1). The 100Ω load,
O
combined with the 804Ω total feedback network load,
presents the OPA820 with an effective load of approximately
90Ω in Figure 1.
gain of −1) while an additional input matching resistor (R ) can
M
be used to set the total input impedance equal to the source
if desired. In this case, R = 57.6Ω in parallel with the 402Ω
M
gain setting resistor gives a matched input impedance of 50Ω.
This matching is only needed when the input needs to be
matched to a source impedance, as in the characterization
testing done using the circuit of Figure 2.
+5V
+VS
+
The OPA820 offers extremely good DC accuracy as well as
low noise and distortion. To take full advantage of that DC
precision, the total DC impedance looking out of each of the
input nodes must be matched to get bias current cancellation.
For the circuit of Figure 2, this requires the 205Ω resistor
shown to ground on the noninverting input. The calculation for
this resistor includes a DC-coupled 50Ω source impedance
µ
0.1 F
2.2µF
50Ω Source
Ω
50 Load
RS
50Ω
VIN
VO
50Ω
OPA820
RF
Ω
402
along with R and R . Although this resistor will provide
G
M
cancellation for the bias current, it must be well decoupled
(0.01µF in Figure 2) to filter the noise contribution of the
resistor and the input current noise.
RG
402Ω
0.1µF
2.2µF
+
As the required R resistor approaches 50Ω at higher gains,
G
the bandwidth for the circuit in Figure 2 will far exceed the
bandwidth at that same gain magnitude for the noninverting
circuit of Figure 1. This occurs due to the lower noise gain for
the circuit of Figure 2 when the 50Ω source impedance is
included in the analysis. For instance, at a signal gain of −10
−
VS
−5V
Figure 1. Gain of +2, High-Frequency Application
and Characterization Circuit
(R = 50Ω, R = open, R = 499Ω) the noise gain for the
G
M
F
circuit of Figure 2 will be 1 + 499Ω/(50Ω + 50Ω) = 6 as a result
of adding the 50Ω source in the noise gain equation. This
gives considerable higher bandwidth than the noninverting
gain of +10. Using the 240MHz gain bandwidth product for the
OPA820, an inverting gain of −10 from a 50Ω source to a 50Ω
WIDEBAND INVERTING OPERATION
Operating the OPA820 as an inverting amplifier has several
benefits and is particularly useful when a matched 50Ω source
and input impedance is required. Figure 2 shows the inverting
gain of −1 circuit used as the basis of the inverting mode
typical characteristics.
R
gives 55MHz bandwidth, whereas the noninverting gain of
G
+10 gives 30MHz.
13
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SBOS303A − JUNE 2004 − REVISED JULY 2004
Figure 4 shows the AC-coupled, single +5V supply, gain of
−1V/V circuit configuration used as a basis for the +5V only
Typical Characteristic curves. In this case, the midpoint DC
bias on the noninverting input is also decoupled with an
additional 0.01µF decoupling capacitor. This reduces the
source impedance at higher frequencies for the noninverting
input bias current noise. This 2.5V bias on the noninverting
WIDEBAND SINGLE-SUPPLY OPERATION
Figure 3 shows the AC-coupled, single +5V supply, gain of
+2V/V circuit configuration used as a basis for the +5V only
Electrical and Typical Characteristics. The key requirement for
single-supply operation is to maintain input and output signal
swings within the useable voltage ranges at both the input and
the output. The circuit of Figure 3 establishes an input
midpoint bias using a simple resistive divider from the +5V
supply (two 806Ω resistors) to the noninverting input. The
input signal is then AC-coupled into this midpoint voltage bias.
The input voltage can swing to within 0.9V of the negative
input pin appears on the inverting input pin and, since R is DC
G
blocked by the input capacitor, will also appear at the output
pin.
The single-supply test circuits of Figure 3 and Figure 4 show
+5V operation. These same circuits can be used over a single-
supply range of +5V to +12V. Operating on a single +12V
supply, with the Absolute Maximum Supply voltage
specification of +13V, gives adequate design margin for the
typical 5% supply tolerance.
supply and 0.5V of the positive supply, giving a 3.6V input
PP
signal range. The input impedance matching resistor (57.6Ω)
used in Figure 3 is adjusted to give a 50Ω input match when
the parallel combination of the biasing divider network is
included. The gain resistor (R ) is AC-coupled, giving the
G
circuit a DC gain of +1. This puts the input DC bias voltage
(2.5V) on the output as well. On a single +5V supply, the output
voltage can swing to within 1.3V of either supply pin while
delivering more than 80mA output current giving 2.4V output
swing into 100Ω (5.6dBm maximum at the matched load).
+5V
+VS
+
µ
µ
6.8 F
0.1 F
Ω
50 Source
Ω
Ω
806
µ
0.01 F
DIS
VI
Ω
100
VO
VS/2
OPA820
Ω
57.6
806
RF
Ω
402
RG
Ω
402
µ
0.01 F
Figure 3. AC-Coupled, G = +2V/V, Single-Supply Specifications and Test Circuit
+5V
+VS
+
µ
µ
6.8 F
0.1 F
Ω
Ω
806
DIS
VO
Ω
100
µ
806
0.01 F
VS/2
OPA820
RG
RF
µ
0.01 F
Ω
402
Ω
402
VI
Figure 4. AC-Coupled, G = −1V/V, Single-Supply Specifications and Test Circuit
14
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SBOS303A − JUNE 2004 − REVISED JULY 2004
Since the DC bias current of the CMOS ADC input is
negligible, the resistor has no effect on overall gain or offset
BUFFERING HIGH-PERFORMANCE ADCs
To achieve full performance from a high dynamic range ADC,
considerable care must be exercised in the design of the input
amplifier interface circuit. The example circuit on the front
page shows a typical AC-coupled interface to a very high
dynamic range converter. This AC-coupled example allows
the OPA820 to be operated using a signal range that swings
accuracy. Refer to the typical characteristic R vs Capacitive
S
Load to obtain a good starting value for the series resistor. This
will ensure flat frequency response to the ADC input.
Increasing the external capacitor value will allow the series
resistor to be reduced. Intentionally bandlimiting using this RC
network can also be used to limit noise at the converter input.
symmetrically around ground (0V). The 2V
swing is then
PP
level-shifted through the blocking capacitor to a midscale
reference level, which is created by a well-decoupled resistive
divider off the converter’s internal reference voltages. To have
a negligible effect (1dB) on the rated spurious-free dynamic
range (SFDR) of the converter, the amplifier’s SFDR should be
at least 18dB greater than the converter. The OPA820 has
minimal effect on the rated distortion of the ADS850, given its
VIDEO LINE DRIVING
Most video distribution systems are designed with 75Ω series
resistors to drive a matched 75Ω cable. In order to deliver a net
gain of 1 to the 75Ω matched load, the amplifier is typically set
up for a voltage gain of +2, compensating for the 6dB
attenuation of the voltage divider formed by the series and
shunt 75Ω resistors at either end of the cable.
79dB SFDR at 2V , 1MHz. The > 90dB (< 1MHz) SFDR for
PP
the OPA820 in this configuration implies a < 3dB degradation
(for the system) from the converter’s specification. For further
The circuit of Figure 1 applies to this requirement if all
references to 50Ω resistors are replaced by 75Ω values.
Often, the amplifier gain is further increased to 2.2, which
recovers the additional DC loss of a typical long cable run. This
SFDR improvement with the OPA820,
configuration is suggested.
a differential
Successful application of the OPA820 for ADC driving
requires careful selection of the series resistor at the amplifier
output, along with the additional shunt capacitor at the ADC
input. To some extent, selection of this RC network will be
determined empirically for each converter. Many high-
performance CMOS ADCs, such as the ADS850, perform
better with the shunt capacitor at the input pin. This capacitor
provides low source impedance for the transient currents
produced by the sampling process. Improved SFDR is often
obtained by adding this external capacitor, whose value is
often recommended in this converter data sheet. The external
capacitor, in combination with the built-in capacitance of the
ADC input, presents a significant capacitive load to the
OPA820. Without a series isolation resistor, an undesirable
peaking or loss of stability in the amplifier may result.
change would require the gain resistor (R ) in Figure 1 to be
G
reduced from 402Ω to 335Ω. In either case, both the gain
flatness and the differential gain/phase performance of the
OPA820 will provide exceptional results in video distribution
applications. Differential gain and phase measure the change
in overall small-signal gain and phase for the color sub-carrier
frequency (3.58MHz in NTSC systems) versus changes in the
large-signal output level (which represents luminance
information in a composite video signal). The OPA820, with
the typical 150Ω load of a single matched video cable, shows
less than 0.01%/0.01° differential gain/phase errors over the
standard luminance range for a positive video (negative sync)
signal. Similar performance would be observed for multiple
video signals, as shown in Figure 5.
Ω
335
Ω
402
Ω
75 Transmission Line
Ω
75
Ω
75
Ω
75
VOUT
VOUT
VOUT
OPA820
Video
Input
Ω
Ω
Ω
75
75
75
Ω
75
High output current drive capability allows three
Ω
back−terminated 75 transmission lines to be simultaneously driven.
Figure 5. Video Distribution Amplifier
15
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This approach saves board space, cost, and power compared
to using two additional OPA820 devices, and still achieves
very good noise and distortion performance as a result of the
moderate loading on the input amplifiers.
SINGLE OP AMP DIFFERENTIAL AMPLIFIER
The voltage-feedback architecture of the OPA820, with its
high common-mode rejection ratio (CMRR), will provide
exceptional performance in differential amplifier configura-
tions. Figure 6 shows a typical configuration. The starting
point for this design is the selection of the R value in the range
F
+5V
of 200Ω to 2kΩ. Lower values reduce the required R ,
G
increasing the load on the V source and on the OPA820
V1
2
output. Higher values increase output noise as well as the
effects of parasitic board and device capacitances. Following
OPA2822
Power−supply decoupling not shown.
the selection of R , R must be set to achieve the desired
F
G
RF1
+5V
inverting gain for V . Remember that the bandwidth will be set
Ω
500
Ω
500
2
approximately by the gain bandwidth product (GBP) divided
VO
by the noise gain (1 + R /R ). For accurate differential
OPA820
F
G
RG
Ω
500
RF1
operation (that is, good CMRR), the ratio R /R must be set
Ω
2
1
500
Ω
500
equal to R /R .
F
G
−
5V
Ω
500
Ω
500
+5V
OPA2822
V2
Power−supply decoupling not shown.
R1
V1
−
5V
50Ω
R
F (V1 − V2)
R2
VO
=
OPA820
RG
Figure 7. Wideband 3-Op Amp Differencing
Amplifier
R2 RF
=
when
RG
RF
R1 RG
In this circuit, the common-mode gain to the output is always
V2
1, because of the four matched 500Ω resistors, whereas the
differential gain is set by (1 + 2R /R ), which is equal to 2
F1
G
−
5V
using the values in Figure 7. The differential to single-ended
conversion is still performed by the OPA820 output stage. The
Figure 6. High-Speed, Single Differential
Amplifier
high-impedance inputs allow the V and V sources to be
1
2
terminated or impedance-matched as required. If the V and
1
V inputs are already truly differential, such as the output from
2
a signal transformer, then a single matching termination
resistor may be used between them. Remember, however,
Usually, it is best to set the absolute values of R and R equal
2
1
to R and R , respectively; this equalizes the divider
F
G
that a defined DC signal path must always exist for the V and
resistances and cancels the effect of input bias currents.
1
V inputs; for the transformer case, a center-tapped secon-
2
dary connected to ground would provide an optimum DC
operating point.
However, it is sometimes useful to scale the values of R and
2
R in order to adjust the loading on the driving source, V . In
1
1
most cases, the achievable low-frequency CMRR will be
limited by the accuracy of the resistor values. The 85dB
CMRR of the OPA820 itself will not determine the overall circuit
CMRR unless the resistor ratios are matched to better than
DAC TRANSIMPEDANCE AMPLIFIER
High-frequency Digital-to-Analog Converters (DACs) require
a low-distortion output amplifier to retain their SFDR
performance into real-world loads. See Figure 8 for a
single-ended output drive implementation. In this circuit, only
one side of the complementary output drive signal is used. The
diagram shows the signal output current connected into the
virtual ground-summing junction of the OPA820, which is set
up as a transimpedance stage or I-V converter. The unused
current output of the DAC is connected to ground. If the DAC
requires its outputs to be terminated to a compliance voltage
other than ground for operation, then the appropriate voltage
level may be applied to the noninverting input of the OPA820.
0.003%. If it is necessary to trim the CMRR, then R is the
2
suggested adjustment point.
THREE OP AMP DIFFERENCING
(Instrumentation Topology)
The primary drawback of the single op amp differential
amplifier is its relatively low input impedances. Where high
impedance is required at the differential input, a standard
instrumentation amplifier (INA) topology may be built using the
OPA820 as the differencing stage. Figure 7 shows an
example of this, in which the two input amplifiers are packaged
together as a dual voltage-feedback op amp, the OPA2822.
16
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SBOS303A − JUNE 2004 − REVISED JULY 2004
C1
150pF
VO = ID RF
OPA820
+5V
High−Speed
DAC
R1
R2
RF
CF
Ω
Ω
505
124
V1
C2
100pF
VO
OPA820
CD
ID
RF
Ω
402
→
GBP Gain Bandwidth
Product (Hz) for the OPA820.
Power−supply
decoupling not shown.
−
5V
RG
Ω
402
ID
Figure 9. 5MHz Butterworth Low-Pass Active
Filter
Figure 8. Wideband, Low-Distortion DAC
Transimpedance Amplifier
Another type of filter, a high-Q bandpass filter, is shown in
Figure 10. The transfer function for this filter is:
The DC gain for this circuit is equal to R . At high frequencies,
F
)R
s RR1
3
4
the DAC output capacitance (C ) will produce a zero in the
R
C
VOUT
VIN
D
4
1
+
noise gain for the OPA820 that may cause peaking in the
closed-loop frequency response. C is added across R to
R
R
1
C
3
5
s2 ) s R1
)
R
2
R
C C
1 2
F
F
(3)
1
4
compensate for this noise-gain peaking. To achieve a flat
transimpedance frequency response, this pole in the
feedback network should be set to:
R3
2
with wO
+
R2R4R5C1C2
(4)
(5)
wO
GBP
4pRFCD
1
1
and
+
+
Ǹ
Q
R1C1
2pRFCF
(1)
For the values chosen in Figure 10:
which will give a corner frequency f
of approximately:
−3dB
w
fO + O ] 1MHz
2p
GBP
2pRFCD
f*3dB
+
Ǹ
(6)
(2)
and Q = 100
See Figure 11 for the frequency response of the filter
shown in Figure 10.
ACTIVE FILTERS
Most active filter topologies will have exceptional performance
using the broad bandwidth and unity-gain stability of the
OPA820. Topologies employing capacitive feedback require
a unity-gain stable, voltage-feedback op amp. Sallen-Key
filters simply use the op amp as a noninverting gain stage
inside an RC network. Either current- or voltage-feedback op
amps may be used in Sallen-Key implementations.
R3
Ω
500
OPA820
R4
Ω
500
Figure 9 shows an example Sallen-Key low-pass filter, in
which the OPA820 is set up to deliver a low-frequency gain of
+2. The filter component values have been selected to
achieve a maximally-flat Butterworth response with a 5MHz,
−3dB bandwidth. The resistor values have been slightly
adjusted to compensate for the effects of the 240MHz
bandwidth provided by the OPA820 in this configuration. This
filter may be combined with the ADC driver suggestions to
provide moderate (2-pole) Nyquist filtering, limiting noise, and
out-of-band harmonics into the input of an ADC. This filter will
deliver the exceptionally low harmonic distortion required by
high SFDR ADCs such as the ADS850 (14-bit, 10MSPS,
82dB SFDR).
C2
1000pF
R5
Ω
158
R2
158
R1
15.8k
Ω
VOUT
Ω
OPA820
VIN
C1
1000pF
Figure 10. High-Q 1MHz Bandpass Filter
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OPERATING SUGGESTIONS
OPTIMIZING RESISTOR VALUES
6
0
Since the OPA820 is a unity-gain stable, voltage-feedback op
amp, a wide range of resistor values may be used for the
feedback and gain-setting resistors. The primary limits on
these values are set by dynamic range (noise and distortion)
and parasitic capacitance considerations. Usually, the feed-
back resistor value should be between 200Ω and 1kΩ. Below
200Ω, the feedback network will present additional output
loading which can degrade the harmonic distortion perfor-
mance of the OPA820. Above 1kΩ, the typical parasitic
capacitance (approximately 0.2pF) across the feedback
resistor may cause unintentional band limiting in the amplifier
response. A direct short is suggested as a feedback for
−
6
−
−
−
−
−
−
−
−
−
−
−
12
18
24
30
36
42
48
54
60
66
72
100k
1M
10M
Frequency (Hz)
100M
A = +1V/V.
V
A good rule of thumb is to target the parallel combination of R
F
and R (see Figure 1) to be less than about 200Ω. The
G
combined impedance R || R interacts with the inverting input
F
G
capacitance, placing an additional pole in the feedback
network, and thus a zero in the forward response. Assuming
Figure 11. High-Q 1MHz Bandpass Filter
Frequency Response
a 2pF total parasitic on the inverting node, holding R || R
<
F
G
200Ω will keep this pole above 400MHz. By itself, this
DESIGN-IN TOOLS
constraint implies that the feedback resistor R can increase
F
to several kΩ at high gains. This is acceptable as long as the
DEMONSTRATION BOARDS
pole formed by R and any parasitic capacitance appearing in
F
Two PC boards are available to assist in the initial evaluation
of circuit performance using the OPA820 in its two package
styles. Both of these are available, free, as an unpopulated PC
board delivered with descriptive documentation. The
summary information for these boards is shown in the table
below.
parallel is kept out of the frequency range of interest.
In the inverting configuration, an additional design
consideration must be noted. R becomes the input resistor
G
and therefore the load impedance to the driving source. If
impedance matching is desired, R may be set equal to the
G
required termination value. However, at low inverting gains,
the resulting feedback resistor value can present a significant
load to the amplifier output. For example, an inverting gain of
LITERATURE
REQUEST
NUMBER
BOARD PART
NUMBER
2 with a 50Ω input matching resistor (= R ) would require a
G
PRODUCT
OPA820ID
PACKAGE
SO-8
100Ω feedback resistor, which would contribute to output
DEM-OPA68xU
DEM-OPA6xxN
SBOU010
SBOU009
loading in parallel with the external load. In such a case, it
OPA820IDBV
SOT23-5
would be preferable to increase both the R and R values,
F G
and then achieve the input matching impedance with a third
resistor to ground (see Figure 2). The total input impedance
Go to the TI web site (www.ti.com) to request evaluation
boards in the OPA820 product folder.
becomes the parallel combination of R and the additional
G
shunt resistor.
MACROMODELS AND APPLICATIONS
SUPPORT
Computer simulation of circuit performance using SPICE is
often a quick way to analyze the performance of the OPA820
BANDWIDTH vs GAIN
Voltage-feedback op amps exhibit decreasing closed-loop
bandwidth as the signal gain is increased. In theory, this
relationship is described by the GBP shown in the
specifications. Ideally, dividing GBP by the noninverting signal
gain (also called the noise gain, or NG) will predict the
closed-loop bandwidth. In practice, this only holds true when
the phase margin approaches 90°, as it does in high-gain
configurations. At low signal gains, most amplifiers will exhibit
a more complex response with lower phase margin. The
OPA820 is optimized to give a maximally-flat, 2nd-order
Butterworth response in a gain of 2. In this configuration, the
OPA820 has approximately 64° of phase margin and will show
a typical −3dB bandwidth of 240MHz. When the phase margin
is 64°, the closed-loop bandwidth is approximately √2 greater
than the value predicted by dividing GBP by the noise gain.
and its circuit designs. This is particularly true for video and R
F
amplifier circuits where parasitic capacitance and inductance
can play a major role on circuit performance. A SPICE model
for the OPA820 is available through the TI web page
(www.ti.com). The applications department is also available
for design assistance. These models predict typical
small-signal AC, transient steps, DC performance, and noise
under a wide variety of operating conditions. The models
include the noise terms found in the electrical specifications of
the data sheet. These models do not attempt to distinguish
between the package types in their small-signal AC
performance.
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Increasing the gain will cause the phase margin to approach
90° and the bandwidth to more closely approach the predicted
value of (GBP/NG). At a gain of +10, the 30MHz bandwidth
shown in the Electrical Characteristics agrees with that
predicted using the simple formula and the typical GBP of
280MHz.
The Typical Characteristics show the recommended R vs
S
Capacitive Load and the resulting frequency response at the
load. The criterion for setting the recommended resistor is
maximum bandwidth, flat frequency response at the load.
Since there is now a passive low-pass filter between the
output pin and the load capacitance, the response at the
output pin itself is typically somewhat peaked, and becomes
flat after the roll-off action of the RC network. This is not a
concern in most applications, but can cause clipping if the
desired signal swing at the load is very close to the amplifier’s
swing limit. Such clipping would be most likely to occur in pulse
response applications where the frequency peaking is
manifested as an overshoot in the step response.
OUTPUT DRIVE CAPABILITY
The OPA820 has been optimized to drive the demanding load
of a doubly-terminated transmission line. When a 50Ω line is
driven, a series 50Ω into the cable and a terminating 50Ω load
at the end of the cable are used. Under these conditions, the
cable impedance will appear resistive over a wide frequency
range, and the total effective load on the OPA820 is 100Ω in
parallel with the resistance of the feedback network. The
electrical characteristics show a 3.6V swing into this
load—which will then be reduced to a 1.8V swing at the
termination resistor. The 75mA output drive over tempera-
ture provides adequate current drive margin for this load.
Higher voltage swings (and lower distortion) are achievable
when driving higher impedance loads.
Parasitic capacitive loads greater than 2pF can begin to
degrade the performance of the OPA820. Long PC board
traces, unmatched cables, and connections to multiple
devices can easily cause this value to be exceeded. Always
consider this effect carefully, and add the recommended
series resistor as close as possible to the OPA820 output pin
(see the Board Layout section).
DISTORTION PERFORMANCE
A single video load typically appears as a 150Ω load (using
standard 75Ω cables) to the driving amplifier. The OPA820
provides adequate voltage and current drive to support up to
three parallel video loads (50Ω total load) for an NTSC signal.
With only one load, the OPA820 achieves an exceptionally low
0.01%/0.03° dG/dP error.
The OPA820 is capable of delivering an exceptionally low
distortion signal at high frequencies and low gains. The
distortion plots in the Typical Characteristics show the typical
distortion under a wide variety of conditions. Most of these
plots are limited to 100dB dynamic range. The OPA820
distortion does not rise above −90dBc until either the signal
level exceeds 0.9V and/or the fundamental frequency ex-
ceeds 500kHz. Distortion in the audio band is ≤ −100dBc.
DRIVING CAPACITIVE LOADS
One of the most demanding, and yet very common, load
conditions for an op amp is capacitive loading. A high-speed,
high open-loop gain amplifier like the OPA820 can be very
susceptible to decreased stability and closed-loop response
peaking when a capacitive load is placed directly on the output
pin. In simple terms, the capacitive load reacts with the
open-loop output resistance of the amplifier to introduce an
additional pole into the loop and thereby decrease the phase
margin. This issue has become a popular topic of application
notes and articles, and several external solutions to this
problem have been suggested. When the primary
considerations are frequency response flatness, pulse
response fidelity, and/or distortion, the simplest and most
effective solution is to isolate the capacitive load from the
feedback loop by inserting a series isolation resistor between
the amplifier output and the capacitive load. This does not
eliminate the pole from the loop response, but rather shifts it
and adds a zero at a higher frequency. The additional zero
acts to cancel the phase lag from the capacitive load pole, thus
increasing the phase margin and improving stability.
Generally, until the fundamental signal reaches very high
frequencies or powers, the 2nd-harmonic will dominate the
distortion with
a negligible 3rd-harmonic component.
Focusing then on the 2nd-harmonic, increasing the load
impedance improves distortion directly. Remember that the
total load includes the feedback network—in the noninverting
configuration this is the sum of R + R , whereas in the
F
G
inverting configuration this is just R (see Figure 1). Increasing
F
the output voltage swing increases harmonic distortion
directly. Increasing the signal gain will also increase the
2nd-harmonic distortion. Again, a 6dB increase in gain will
increase the 2nd- and 3rd-harmonic by 6dB even with a
constant output power and frequency. Finally, the distortion
increases as the fundamental frequency increases because
of the roll-off in the loop gain with frequency. Conversely, the
distortion will improve going to lower frequencies down to the
dominant open-loop pole at approximately 100kHz. Starting
from the −85dBc 2nd-harmonic for 2V
into 200Ω, G = +2
PP
distortion at 1MHz (from the Typical Characteristics), the
2nd-harmonic distortion will not show any improvement below
100kHz and will then be:
−100dB − 20log (1MHz/100kHz) = −105dBc
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(9µA typ into the pins) but with a very close match between the
two input currents—typically 100nA input offset current. The
total output offset voltage may be considerably reduced by
matching the source impedances looking out of the two inputs.
For example, one way to add bias current cancellation to the
circuit of Figure 1 would be to insert a 175Ω series resistor into
the noninverting input from the 50Ω terminating resistor. When
the 50Ω source resistor is DC-coupled, this will increase the
source impedance for the noninverting input bias current to
200Ω. Since this is now equal to the impedance looking out of
NOISE PERFORMANCE
The OPA820 complements its low harmonic distortion with low
input noise terms. Both the input-referred voltage noise and
the two input-referred current noise terms combine to give a
low output noise under a wide variety of operating conditions.
Figure 12 shows the op amp noise analysis model with all the
noise terms included. In this model, all the noise terms are
taken to be noise voltage or current density terms in either
nV/√Hz or pA/√Hz.
the inverting input (R || R ), the circuit will cancel the gains for
F
G
the bias currents to the output leaving only the offset current
times the feedback resistor as a residual DC error term at the
output. Using a 402Ω feedback resistor, this output error will
now be less than 0.4µA × 402Ω = 160µV at 25°C.
ENI
EO
OPA820
RS
IBN
THERMAL ANALYSIS
ERS
The OPA820 will not require heatsinking or airflow in most
applications. Maximum desired junction temperature would
set the maximum allowed internal power dissipation as
described below. In no case should the maximum junction
temperature be allowed to exceed +150°C.
RF
√
4kTRS
√
4kTRF
IBI
RG
4kT
RG
−
_
4kT = 1.6E 20J
Operating junction temperature (T ) is given by
J
at 290 K
T
+ P × q . The total internal power dissipation (P ) is the
A
D JA D
sum of quiescent power (P ) and additional power
DQ
Figure 12. Op Amp Noise Analysis Model
dissipated in the output stage (P ) to deliver load power.
DL
Quiescent power is simply the specified no-load supply
The total output spot noise voltage is computed as the square
root of the squared contributing terms to the output noise
voltage. This computation is adding all the contributing noise
powers at the output by superposition, then taking the square
root to get back to a spot noise voltage. Equation 3 shows the
general form for this output noise voltage using the terms
presented in Figure 12.
current times the total supply voltage across the part. P will
DL
depend on the required output signal and load but would, for
a grounded resistive load, be at a maximum when the output
is fixed at a voltage equal to 1/2 of either supply voltage (for
equal bipolar supplies). Under this worst-case condition,
2
P
= V /(4 × R ), where R includes feedback network
S L L
DL
loading.
Note that it is the power in the output stage and not in the load
that determines internal power dissipation.
) ǒI SǓ2
) ǒI FǓ2
2
NI
2
ƪE
Ǹ
) 4kTR ƫNG
E
+
R
R
) 4kTR NG
BN
BI
F
O
S
(7)
As a worst-case example, compute the maximum T using an
J
OPA820IDBV (SOT23-5 package) in the circuit of Figure 1
operating at the maximum specified ambient temperature of
+85°C.
Dividing this expression by the noise gain (NG = 1 + R /R )
will give the equivalent input referred spot noise voltage at the
noninverting input, as shown in Equation 4.
F
G
2
P
= 10V(6.4mA) + 5 /(4 × (100Ω || 800Ω)) = 134mW
D
2
ǒ
SǓ2
) 4kTRS
IBIRF
) ǒ Ǔ )
NG
4kTRF
NG
Maximum T = +85°C + (134mW × 150°C/W) = 105°C
2
J
+ Ǹ
EN
ENI ) IBN
R
(8)
BOARD LAYOUT
Evaluating these two equations for the OPA820 circuit
presented in Figure 1 will give a total output spot noise voltage
of 6.44nV/√Hz and an equivalent input spot noise voltage of
3.22nV/√Hz.
Achieving optimum performance with a high-frequency
amplifier such as the OPA820 requires careful attention to
board layout parasitics and external component types.
Recommendations that will optimize performance include:
a) Minimize parasitic capacitance to any AC ground for all
of the signal I/O pins. Parasitic capacitance on the output
and inverting input pins can cause instability: on the
noninverting input, it can react with the source impedance to
cause unintentional bandlimiting. To reduce unwanted
capacitance, a window around the signal I/O pins should be
opened in all of the ground and power planes around those
pins. Otherwise, ground and power planes should be
unbroken elsewhere on the board.
DC OFFSET CONTROL
The OPA820 can provide excellent DC signal accuracy
because of its high open-loop gain, high common-mode
rejection, high power-supply rejection, and low input offset
voltage and bias current offset errors. To take full advantage
of this low input offset voltage, careful attention to input bias
current cancellation is also required. The high-speed input
stage for the OPA820 has a moderately high input bias current
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b) Minimize the distance (< 0.25”) from the power-supply
pins to high-frequency 0.1µF decoupling capacitors. At
the device pins, the ground and power-plane layout should not
be in close proximity to the signal I/O pins. Avoid narrow power
and ground traces to minimize inductance between the pins
and the decoupling capacitors. The power-supply connec-
tions should always be decoupled with these capacitors.
Larger (2.2µF to 6.8µF) decoupling capacitors, effective at
lower frequency, should also be used on the main supply pins.
These may be placed somewhat farther from the device and
may be shared among several devices in the same area of the
PC board.
d) Connections to other wideband devices on the board
may be made with short direct traces or through onboard
transmission lines. For short connections, consider the trace
and the input to the next device as a lumped capacitive load.
Relatively wide traces (50mils to 100mils) should be used,
preferably with ground and power planes opened up around
them. Estimate the total capacitive load and set R from the
S
plot of Recommended R vs Capacitive Load. Low parasitic
S
capacitive loads (< 5pF) may not need an R since the
S
OPA820 is nominally compensated to operate with a 2pF
parasitic load. Higher parasitic capacitive loads without an R
S
are allowed as the signal gain increases (increasing the
unloaded phase margin). If a long trace is required, and the
6dB signal loss intrinsic to a doubly-terminated transmission
line is acceptable, implement a matched impedance
transmission line using microstrip or stripline techniques
(consult an ECL design handbook for microstrip and stripline
layout techniques). A 50Ω environment is normally not
necessary onboard, and in fact, a higher impedance
environment will improve distortion as shown in the distortion
versus load plots. With a characteristic board trace impedance
defined based on board material and trace dimensions, a
matching series resistor into the trace from the output of the
OPA820 is used as well as a terminating shunt resistor at the
input of the destination device. Remember also that the
terminating impedance will be the parallel combination of the
shunt resistor and input impedance of the destination device;
this total effective impedance should be set to match the trace
impedance. If the 6dB attenuation of a doubly-terminated
transmission line is unacceptable, a long trace can be
series-terminated at the source end only. Treat the trace as a
capacitive load in this case and set the series resistor value as
c) Careful selection and placement of external compo-
nents will preserve the high-frequency performance of
the OPA820. Resistors should be a very low reactance type.
Surface-mount resistors work best and allow a tighter overall
layout. Metal-film and carbon composition, axially leaded
resistors can also provide good high-frequency performance.
Again, keep their leads and PC board trace length as short as
possible. Never use wire-wound type resistors in
a
high-frequency application. Since the output pin and inverting
input pin are the most sensitive to parasitic capacitance,
always position the feedback and series output resistor, if any,
as close as possible to the output pin. Other network
components, such as noninverting input termination resistors,
should also be placed close to the package. Where
double-side component mounting is allowed, place the
feedback resistor directly under the package on the other side
of the board between the output and inverting input pins. Even
with a low parasitic capacitance shunting the external
resistors, excessively high resistor values can create
significant time constants that can degrade performance.
Good axial metal-film or surface-mount resistors have
approximately 0.2pF in shunt with the resistor. For resistor
values > 1.5kΩ, this parasitic capacitance can add a pole
and/or a zero below 500MHz that can effect circuit operation.
Keep resistor values as low as possible consistent with
load-driving considerations. It has been suggested here that
shown in the plot of R vs Capacitive Load. This will not
S
preserve signal integrity as well as a doubly-terminated line.
If the input impedance of the destination device is low, there
will be some signal attenuation due to the voltage divider
formed by the series output into the terminating impedance.
e) Socketing a high-speed part like the OPA820 is not
recommended. The additional lead length and pin-to-pin
capacitance introduced by the socket can create an extremely
troublesome parasitic network, which can make it almost
impossible to achieve a smooth, stable frequency response.
Best results are obtained by soldering the OPA820 onto the
board.
a good starting point for design would be to set R || R
=
G
F
200Ω. Using this setting will automatically keep the resistor
noise terms low, and minimize the effect of their parasitic
capacitance.
21
ꢂꢀꢉꢠ ꢡꢢ
www.ti.com
SBOS303A − JUNE 2004 − REVISED JULY 2004
These diodes provide moderate protection to input overdrive
voltages above the supplies as well. The protection diodes
can typically support 30mA continuous current. Where higher
currents are possible (for example, in systems with 15V
supply parts driving into the OPA820), current-limiting series
resistors should be added into the two inputs. Keep these
resistor values as low as possible since high values degrade
both noise performance and frequency response. Figure 14
shows an example protection circuit for I/O voltages that may
exceed the supplies.
INPUT AND ESD PROTECTION
The OPA820 is built using a very high-speed complementary
bipolar process. The internal junction breakdown voltages are
relatively low for these very small geometry devices. These
breakdowns are reflected in the Absolute Maximum Ratings
table. All device pins are protected with internal ESD
protection diodes to the power supplies, as shown in
Figure 13.
+VCC
+5V
Ω
50 Source
Power−supply
External
Pin
decoupling not shown.
Ω
174
V1
Ω
50
D1
D2
OPA820
VO
Ω
50
−
VCC
RF
Ω
50
Figure 13. Internal ESD Protection
Ω
301
RG
Ω
301
−
5V
D1 = D2 IN5911 (or equivalent)
Figure 14. Gain of +2 with Input Protection
22
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