OPA333AIDR [BB]
1.8V, microPOWER CMOS OPERATIONAL AMPLIFIERS Zer-PI Drift Series; 1.8V ,微功耗CMOS运算放大器泽尔-PI漂移系列型号: | OPA333AIDR |
厂家: | BURR-BROWN CORPORATION |
描述: | 1.8V, microPOWER CMOS OPERATIONAL AMPLIFIERS Zer-PI Drift Series |
文件: | 总18页 (文件大小:471K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
OPA333
OPA2333
SBOS351 − MARCH 2006
1.8V, microPOWER
CMOS OPERATIONAL AMPLIFIERS
Zerj-Drift Series
FEATURES
DESCRIPTION
D
D
D
D
D
D
D
D
LOW OFFSET VOLTAGE: 10µV (max)
ZERO DRIFT: 0.05µV/°C (max)
The OPA333 series of CMOS operational amplifiers uses
a proprietary auto-calibration technique to simultaneously
provide very low offset voltage (10µV max) and near-zero
drift over time and temperature. These miniature,
high-precision, low quiescent current amplifiers offer
high-impedance inputs that have a common-mode range
100mV beyond the rails and rail-to-rail output that swings
within 50mV of the rails. Single or dual supplies as low as
+1.8V ( 0.9V) and up to +5.5V ( 2.75V) may be used.
They are optimized for low-voltage, single-supply
operation.
0.01Hz to 10Hz NOISE: 1.1µV
PP
QUIESCENT CURRENT: 17µA
SINGLE-SUPPLY OPERATION
SUPPLY VOLTAGE: 1.8V to 5.5V
RAIL-TO-RAIL INPUT/OUTPUT
microSIZE PACKAGES: SC70 and SOT23
The OPA333 family offers excellent CMRR without the
crossover associated with traditional complementary input
stages. This design results in superior performance for
driving analog-to-digital converters (ADCs) without
degradation of differential linearity.
APPLICATIONS
D
D
D
D
D
D
TRANSDUCER APPLICATIONS
TEMPERATURE MEASUREMENTS
ELECTRONIC SCALES
The OPA333 (single version) is available in the SC70-5,
SOT23-5, and SO-8 packages. The OPA2333 (dual
version) is offered in DFN-8 (3mm x 3mm, available
Q2 ’06) and SO-8 packages. All versions are specified for
operation from −40°C to +125°C.
MEDICAL INSTRUMENTATION
BATTERY-POWERED INSTRUMENTS
HANDHELD TEST EQUIPMENT
OPA333
0.1Hz TO 10Hz NOISE
OUT
1
2
3
5
4
V+
−
V
−
+IN
IN
SOT23−5
OPA333
+IN
1
2
3
5
4
V+
−
V
−
IN
OUT
1s/div
SC70−5
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
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Copyright 2006, Texas Instruments Incorporated
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SBOS351 − MARCH 2006
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handledwith appropriate precautions. Failure to observe
(1)
ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7V
(2)
Signal Input Terminals, Voltage
. . . . . . . . . −0.3V to (V+) + 0.3V
. . . . . . . . . . . . . . . . . . . . 10mA
proper handling and installation procedures can cause damage.
(2)
Signal Input Terminals, Voltage
(3)
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
Output Short-Circuit
. . . . . . . . . . . . . . . . . . . . . . . . . Continuous
Operating Temperature . . . . . . . . . . . . . . . . . . . . . −40°C to +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . −65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4000V
Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000V
(1)
Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not supported.
(2)
(3)
Input terminals are diode-clamped to the power-supply rails.
Input signals that can swing more than 0.3V beyond the supply
rails should be current limited to 10mA or less.
Short-circuit to ground, one amplifier per package.
(1)
ORDERING INFORMATION
PRODUCT
PACKAGE-LEAD
SOT23-5
SC70-5
PACKAGE DESIGNATOR
PACKAGE MARKING
OPA333
DBV
DCK
D
OAXQ
BQY
OPA333
OPA333
SO-8
O333A
O2333A
BQZ
OPA2333
OPA2333
SO-8
D
(2)
DFN-8
DRB
(1)
(2)
For the most current specification and package information see the Package Option Addendum at the end of this document, or see the TI web
site at www.ti.com.
Available Q2 ’06.
PIN CONFIGURATIONS
OPA333
OPA333
OPA2333
NC(1)
V+
NC(1)
1
2
3
4
8
7
6
5
OUT
1
2
3
5
4
V+
OUT A
1
2
3
4
8
7
6
5
V+
A
−
−
V
IN
−
OUT B
IN A
B
OUT
NC(1)
−
+IN
IN
+IN
−
+IN A
IN B
−
V
−
V
+IN B
SOT23−5
OPA333
OPA2333
SO−8
SO−8
+IN
1
2
3
5
V+
OUT A
1
2
3
8
7
6
5
V+
Exposed
Thermal
Die Pad
on
−
V
−
IN A
+IN A
OUT B
−
IN
4
OUT
−
IN B
Underside(2)
−
V
4
+IN B
SC70−5
(1)
(2)
(3)
DFN−8(3)
NC denotes no internal connection.
Connect thermal die pad to V−.
Available Q2 ’06.
2
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SBOS351 − MARCH 2006
ELECTRICAL CHARACTERISTICS: V = +1.8V to +5.5V
S
Boldface limits apply over the specified temperature range, T = −40°C to +125°C.
A
At T = +25°C, R = 10kΩ connected to V /2, V
= V /2, and V
= V /2, unless otherwise noted.
A
L
S
CM
S
OUT S
OPA333, OPA2333
MIN
TYP
MAX
PARAMETER
TEST CONDITIONS
= +5V
UNIT
OFFSET VOLTAGE
Input Offset Voltage
vs Temperature
V
V
2
10
0.05
5
µV
µV/°C
µV/V
OS
S
dV /dT
OS
0.02
vs Power Supply
Long-Term Stability
PSRR
V
= +1.8V to +5.5V
1
See Note (1)
0.1
S
(1)
Channel Separation, dc
INPUT BIAS CURRENT
Input Bias Current
µV/V
I
70
200
400
pA
pA
pA
B
over Temperature
Input Offset Current
NOISE
150
140
I
OS
Input Voltage Noise, f = 0.01Hz to 1Hz
Input Voltage Noise, f = 0.1Hz to 10Hz
Input Current Noise, f = 10Hz
INPUT VOLTAGE RANGE
Common-Mode Voltage Range
Common-Mode Rejection Ratio
INPUT CAPACITANCE
Differential
0.3
1.1
µV
µV
fA/√Hz
PP
PP
i
100
n
V
(V−) − 0.1
(V+) + 0.1
V
CM
CMRR
(V−) − 0.1V < V
< (V+) + 0.1V
106
130
dB
CM
2
4
pF
pF
Common-Mode
OPEN-LOOP GAIN
Open-Loop Voltage Gain
FREQUENCY RESPONSE
Gain-Bandwidth Product
Slew Rate
A
(V−) + 100mV < V < (V+) − 100mV, R = 10kΩ
106
130
dB
O
L
OL
GBW
SR
C = 100pF
L
G = +1
350
kHz
0.16
V/µs
OUTPUT
Voltage Output Swing from Rail
over Temperature
Short-Circuit Current
Capacitive Load Drive
Open-Loop Output Impedance
POWER SUPPLY
R = 10kΩ
30
5
50
mV
mV
mA
L
R
= 10kΩ
70
L
I
SC
C
See Typical Characteristics
2
L
f = 350kHz, I = 0
kΩ
O
Specified Voltage Range
Quiescent Current Per Amplifier
over Temperature
Turn-On Time
V
1.8
5.5
V
S
I
I
= 0
17
25
µA
µA
µs
Q
O
28
V
= +5V
100
S
TEMPERATURE RANGE
Specified Range
−40
−40
−65
+125
+150
+150
°C
°C
°C
Operating Range
Storage Range
Thermal Resistance
SOT23-5
q
°C/W
°C/W
°C/W
°C/W
°C/W
JA
200
150
50
SO-8
DFN-8
SC70-5
250
(1)
300-hour life test at +150°C demonstrated randomly distributed variation of approximately 1µV.
3
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SBOS351 − MARCH 2006
TYPICAL CHARACTERISTICS
At T = +25°C, V = +5V, and C = 0pF, unless otherwise noted.
A
S
L
OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION
OFFSET VOLTAGE PRODUCTION DISTRIBUTION
µ
Offset Voltage ( V)
µ
_
Offset Voltage Drift ( V/ C)
OPEN−LOOP GAIN vs FREQUENCY
COMMON−MODE REJECTION RATIO vs FREQUENCY
120
100
80
60
40
20
0
250
200
150
100
50
140
120
100
80
60
0
40
−
−
50
20
−
20
100
0
10
100
1k
10k
100k
1M
1
10
100
1k
10k
100k
1M
Frequency (Hz)
Frequency (Hz)
POWER−SUPPLY REJECTION RANGE vs FREQUENCY
+PSRR
OUTPUT VOLTAGE SWING vs OUTPUT CURRENT
120
100
80
60
40
20
0
3
2
1
0
VS
VS
=
=
2.75V
0.9V
−
_
40 C
−
PSRR
_
+25 C
_
+125 C
_
+25 C
−
_
40 C
−
−
−
1
2
3
_
+125 C
_
+25 C
−
_
40 C
1
10
100
1k
10k
100k
1M
0
1
2
3
4
5
6
7
8
9
10
Frequency (Hz)
Output Current (mA)
4
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TYPICAL CHARACTERISTICS (continued)
At T = +25°C, V = +5V, and C = 0pF, unless otherwise noted.
A
S
L
INPUT BIAS CURRENT vs COMMON−MODE VOLTAGE
INPUT BIAS CURRENT vs TEMPERATURE
100
80
60
40
20
0
200
150
100
50
VS = 5.5V
VS = 1.8V
−
IB
−
IB
−
IB
V
= 5V
S
0
+IB
−
−
−
−
20
40
60
80
−
50
−
−
−
100
150
200
+IB
+IB
−
100
−
−
0
1
2
3
4
5
50
25
0
25
50
75
100
125
_
Temperature ( C)
Common−Mode Voltage (V)
QUIESCENT CURRENT vs TEMPERATURE
LARGE−SIGNAL STEP RESPONSE
25
20
15
10
5
G = 1
RL = 10k
Ω
V
S = 5.5V
VS = 1.8V
0
−
−
25
50
0
25
50
75
100
125
µ
Time (50 s/div)
_
Temperature ( C)
POSITIVE OVER−VOLTAGE RECOVERY
SMALL−SIGNAL STEP RESPONSE
G = +1
Ω
0
RL = 10k
Input
Output
Ω
10k
+2.5V
Ω
1k
0
OPA333
−
2.5V
µ
Time (50 s/div)
µ
Time (5 s/div)
5
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TYPICAL CHARACTERISTICS (continued)
At T = +25°C, V = +5V, and C = 0pF, unless otherwise noted.
A
S
L
SETTLING TIME vs CLOSED−LOOP GAIN
4V Step
NEGATIVE OVER−VOLTAGE RECOVERY
Input
600
500
400
300
200
100
0
0
0
Ω
10k
+2.5V
Ω
1k
0.001%
0.01%
Output
OPA333
−
2.5V
1
10
100
µ
Time (50 s/div)
Gain (dB)
SMALL−SIGNAL OVERSHOOT vs LOAD CAPACITANCE
0.1Hz TO 10Hz NOISE
40
35
30
25
20
15
10
5
0
10
100
1000
1s/div
Load Capacitance (pF)
CURRENT AND VOLTAGE NOISE SPECTRAL DENSITY
vs FREQUENCY
1000
100
10
1000
Continues with no 1/f (flicker) noise.
Current Noise
100
Voltage Noise
10
1
10
100
1k
10k
Frequency (Hz)
6
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INPUT VOLTAGE
APPLICATIONS INFORMATION
The OPA333 and OPA2333 input common-mode voltage
range extends 0.1V beyond the supply rails. The OPA333
is designed to cover the full range without the troublesome
transition region found in some other rail-to-rail amplifiers.
The OPA333 and OPA2333 are unity-gain stable and free
from unexpected output phase reversal. They use a
proprietary auto-calibration technique to provide low offset
voltage and very low drift over time and temperature. For
lowest offset voltage and precision performance, circuit
layout and mechanical conditions should be optimized.
Avoid temperature gradients that create thermoelectric
(Seebeck) effects in the thermocouple junctions formed
Normally, input bias current is about 70pA; however, input
voltages exceeding the power supplies can cause
excessive current to flow into or out of the input pins.
Momentary voltages greater than the power supply can be
tolerated if the input current is limited to 10mA. This
limitation is easily accomplished with an input resistor, as
shown in Figure 1.
from
connecting
dissimilar
conductors.
These
thermally-generated potentials can be made to cancel by
assuring they are equal on both input terminals. Other
layout and design considerations include:
D
D
D
Use low thermoelectric-coefficient conditions (avoid
dissimilar metals).
Thermally isolate components from power supplies or
other heat sources.
Current−limiting resistor
required if input voltage
exceeds supply rails by
Shield op amp and input circuitry from air currents,
such as cooling fans.
≥
0.5V.
+5V
IOVERLOAD
Following these guidelines will reduce the likelihood of
junctions being at different temperatures, which can cause
thermoelectric voltages of 0.1µV/°C or higher, depending
on materials used.
10mA max
VOUT
OPA333
VIN
Ω
5k
OPERATING VOLTAGE
The OPA333 and OPA2333 op amps operate over a
power-supply range of +1.8V to +5.5V ( 0.9V to 2.75V).
Supply voltages higher than +7V (absolute maximum) can
permanently damage the device. Parameters that vary
over supply voltage or temperature are shown in the
Typical Characteristics section of this data sheet.
Figure 1. Input Current Protection
INTERNAL OFFSET CORRECTION
The OPA333 and OPA2333 op amps use an
auto-calibration technique with a time-continuous 350kHz
op amp in the signal path. This amplifier is zero-corrected
every 8µs using a proprietary technique. Upon power-up,
the amplifier requires approximately 100µs to achieve
specified VOS accuracy. This design has no aliasing or
flicker noise.
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The OPA333 and OPA2333 have an output stage that
allows the output voltage to be pulled to its negative supply
rail, or slightly below, using the technique previously
described. This technique only works with some types of
output stages. The OPA333 and OPA2333 have been
characterized to perform with this technique; however, the
recommended resistor value is approximately 20kΩ. Note
that this configuration will increase the current
consumption by several hundreds of microamps.
Accuracy is excellent down to 0V and as low as −2mV.
Limiting and nonlinearity occurs below−2mV, but excellent
accuracy returns as the output is again driven above
−2mV. Lowering the resistance of the pull-down resistor
will allow the op amp to swing even further below the
negative rail. Resistances as low as 10kΩ can be used to
achieve excellent accuracy down to −10mV.
ACHIEVING OUTPUT SWING TO THE OP
AMP NEGATIVE RAIL
Some applications require output voltage swings from 0V
to a positive full-scale voltage (such as +2.5V) with
excellent accuracy. With most single-supply op amps,
problems arise when the output signal approaches 0V,
near the lower output swing limit of a single-supply op amp.
A good single-supply op amp may swing close to
single-supply ground, but will not reach ground. The output
of the OPA333 and OPA2333 can be made to swing to
ground, or slightly below, on a single-supply power source.
To do so requires the use of another resistor and an
additional, more negative, power supply than the op amp
negative supply. A pull-down resistor may be connected
between the output and the additional negative supply to
pull the output down below the value that the output would
otherwise achieve, as shown in Figure 2.
GENERAL LAYOUT GUIDELINES
Attention to good layout practices is always
recommended. Keep traces short and, when possible, use
a printed circuit board (PCB) ground plane with
surface-mount components placed as close to the device
pins as possible. Place a 0.1µF capacitor closely across
the supply pins. These guidelines should be applied
throughout the analog circuit to improve performance and
provide benefits such as reducing the EMI
(electromagnetic-interference) susceptibility.
V+ = +5V
OPA333
VOUT
VIN
Ω
RP = 20k
−
Op Amp V = Gnd
Operational amplifiers vary in their susceptibility to radio
frequency interference (RFI). RFI can generally be
identified as a variation in offset voltage or dc signal levels
with changes in the interfering RF signal. The OPA333 has
been specifically designed to minimize susceptibility to
RFI and demonstrates remarkably low sensitivity
compared to previous generation devices. Strong RF
fields may still cause varying offset levels..
−
5V
Additional
Negative
Supply
Figure 2. For V
Range to Ground
OUT
4.096V
REF3140
+5V
+
µ
0.1 F
R9
150k
R1
6.04k
Ω
Ω
R5
Ω
+5V
0.1 F
31.6k
D1
µ
R2
2.94k
R2
Ω
Ω
549
−
−
+
+
VO
OPA333
R6
K−Type
Thermocouple
Ω
200
Zero Adj.
R4
6.04k
R3
µ
_
40.7 V/ C
Ω
Ω
60.4
Figure 3. Temperature Measurement
8
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Figure 4 shows the basic configuration for a bridge
amplifier.
VS
A low-side current shunt monitor is shown in Figure 5. RN
are operational resistors used to isolate the ADS1100 from
the noise of the digital I2C bus. Since the ADS1100 is a
16-bit converter, a precise reference is essential for
maximum accuracy. If absolute accuracy is not required,
and the 5V power supply is sufficiently stable, the
REF3130 may be omitted.
R1
+5V
R
R
R
R
VOUT
OPA333
R1
VREF
Figure 4. Single Op Amp Bridge Amplifier
3V
+5V
REF3130
Load
R1
R2
Ω
Ω
Ω
4.99k
4.99k
R6
71.5k
RN
Ω
V
Ω
56
RSHUNT
ILOAD
OPA333
Ω
1
R3
4.99k
R4
RN
Ω
56
I2C
ADS1100
Ω
48.7k
R7
1.18k
(PGA Gain = 4)
FS = 3.0V
Stray ground−loop reistance.
Ω
1% resistors provide adequate common−mode rejection at small ground−loop errors.
Figure 5. Low-Side Current Monitor
9
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RG
zener(1)
V+
RSHUNT
(2)
R1
MOSFET rated to
stand−off supply voltage
such as BSS84 for
up to 50V.
Ω
10k
OPA333
V+
+5V
Two zener
biasing methods
are shown.(3)
Output
RBIAS
Load
RL
Notes:
(1) zener rated for op amp supply capability (that is, 5.1V for OPA333).
(2) Current−limiting resistor.
(3) Choose zener biasing resistor or dual NMOSFETS (FDG6301N, NTJD4001N, or Si1034)
Figure 6. High-Side Current Monitor
V1
INA152
−
In
OPA333
2
3
5
6
R2
Ω
100k
Ω
Ω
Ω
60k
1M
VO
R1
3V
NTC
Thermistor
R2
1M
OPA333
1
OPA333
V2
+In
−
VO = (1 + 2R2/R1) (V2 V1)
Figure 7. Thermistor Measurement
Figure 8. Precision Instrumentation Amplifier
10
ꢂ ꢀꢉ ꢠꢠꢠ
ꢂ ꢀꢉ ꢡꢠꢠ ꢠ
www.ti.com
SBOS351 − MARCH 2006
DFN PACKAGE
DFN LAYOUT GUIDELINES
The OPA2333 is offered in an DFN-8 package (also known
as SON). The DFN is a QFN package with lead contacts
on only two sides of the bottom of the package. This
leadless package maximizes board space and enhances
thermal and electrical characteristics through an exposed
pad.
The exposed leadframe die pad on the DFN package
should be soldered to a thermal pad on the PCB. A
mechanical drawing showing an example layout is
attached at the end of this data sheet. Refinements to this
layout may be necessary based on assembly process
requirements. Mechanical drawings located at the end of
this data sheet list the physical dimensions for the package
and pad. The five holes in the landing pattern are optional,
and are intended for use with thermal vias that connect the
leadframe die pad to the heatsink area on the PCB.
DFN packages are physically small, have a smaller routing
area, improved thermal performance, and improved
electrical parasitics. Additionally, the absence of external
leads eliminates bent-lead issues.
The DFN package can be easily mounted using standard
printed circuit board (PCB) assembly techniques. See
Application Note QFN/SON PCB Attachment (SLUA271)
and Application Report Quad Flatpack No-Lead Logic
Packages (SCBA017), both available for download at
www.ti.com.
Soldering the exposed pad significantly improves
board-level reliability during temperature cycling, key
push, package shear, and similar board-level tests. Even
with applications that have low-power dissipation, the
exposed pad must be soldered to the PCB to provide
structural integrity and long-term reliability.
The exposed leadframe die pad on the bottom of the
package should be connected to V− or left
unconnected.
11
PACKAGE OPTION ADDENDUM
www.ti.com
14-Mar-2006
PACKAGING INFORMATION
Orderable Device
OPA2333AID
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
8
8
8
8
8
5
5
5
5
5
5
5
5
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
OPA2333AIDG4
OPA2333AIDR
SOIC
SOIC
D
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
OPA2333AIDRG4
OPA333AID
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
OPA333AIDBVR
OPA333AIDBVRG4
OPA333AIDBVT
OPA333AIDBVTG4
OPA333AIDCKR
OPA333AIDCKRG4
OPA333AIDCKT
OPA333AIDCKTG4
OPA333AIDG4
SOT-23
SOT-23
SOT-23
SOT-23
SC70
DBV
DBV
DBV
DBV
DCK
DCK
DCK
DCK
D
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SC70
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SC70
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SC70
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
OPA333AIDR
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
OPA333AIDRG4
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Mar-2006
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 2
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