HSDL-3210-021G [AVAGO]
SPECIALTY INTERFACE CIRCUIT, SMA8, ULTRA SMALL, SMT-8;
| 型号： | HSDL-3210-021G |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | SPECIALTY INTERFACE CIRCUIT, SMA8, ULTRA SMALL, SMT-8 驱动程序和接口 接口集成电路 信息通信管理 |
| 文件： | 总24页 (文件大小：461K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HSDL-3210
IrDA®CompliantLowPower
1.15 Mbit/s InfraredTransceiver
DataSheet
Features
Description
• Fully Compliant to IrDA 1.4 low power specification from
9.6 kbit/s to 1.15 Mbit/s
The HSDL-3210 is one of a new generation of low-cost
Infrared (IR) transceiver modules from Avago
Technologies. It features one of the smallest footprint
in the industry at 2.5 H x 8.0 W x 3.0 D mm. Although
the supply voltage can range from 2.7 V to 3.6 V, the
LED is driven by an internal constant current source of
60 mA at SIR data rates and 150 mA at MIR data rates.
• Ultra small surface mount package
• Minimal height: 2.5 mm
• V from 2.7 to 3.6 volts
CC
• Interface to 1.5 volts input/output logic circuits
• Withstands 100 mV power supply ripple typically
p-p
The HSDL-3210 incorporates the capability for
adjustable optical power. The optical power can be
adjusted lower when the nominal desired link distance
is very short. At 5 cm link distance, only 6% of the full
power is required.
• Adjustable optical power for link distance from
5 to 20 cm
• Low shutdown current – 10 nA typical
• Complete shutdown – TxD, RxD, PIN diode
• Three optional external components
• Temperature performance guaranteed, -25°C to 85°C
• Integrated EMI shield
The HSDL-3210 supports the Serial Interface for
Transceiver Control Specification that provides a
common interface between the transceiver and
controller. It is also designed to interface to input/
output logic circuits as low as 1.5 V.
• IEC60825-1 class 1 eye safe
• Edge detection input – Prevents the LED from long turn
on time
Applications
• Mobile telecom
– Cellular phones
– Pagers
– Smart phones
• Data communication
– PDAs
– Portable printers
• Digital imaging
– Digital cameras
– Photo-imaging printers
Application Support
Information
The Application Engineering
group in Avago Technologies is
available to assist you with the
Technical understanding
Ordering Information
Part Number
Packaging Type
Tape and Reel
Package
Quantity
HSDL-3210-021
Front View
2500
associated with HSDL-3210
infrared transceiver module. You
can contact them through your
local Avago sales representatives
for additional details.
Application Circuit
VLED
8
7
8
7
6
5
4
3
2
1
ADJUSTABLE
OPTICAL
C1
6.8 µF
TXD/SWDAT
POWER
REAR VIEW
RXD/SRDAT
SD
6
5
Figure 2. Rear view diagram with pin-out.
SERIAL
TRANSCEIVER
CONTROL
SCLK
4
3
V
CC
CC
I/O V
2
1
C2
1.0 µF
C3
0.47 µF
GND
Figure 1. Functional block diagram of HSDL-3210.
I/O Pin Configuration Table
Pin Symbol
Description
Notes
1
2
3
4
5
6
GND
IOV
Ground
Connect to system ground.
Input/Output V
Connect to ASIC logic controller V voltage.
CC
CC
CC
V
CC
Supply Voltage
Serial Clock
Regulated, 2.7 to 3.6 Volts
SCLK
SD
Use as clock input pin for programming mode. See Table 1 for details.
Shut Down Active High This pin must be driven either high or low, do NOT float the pin.
RXD/SRDAT Receiver Data Output.
Active Low
Output is a low pulse when a light pulse is received. SRDAT is the read
data for the Serial Transceiver Control (STC). Do NOT float this pin.
7
TXD/SWDAT Transmitter Data Input/ Logic High turns on the LED. If held high longer than ~20 µs, the LED
Serial Write Data
is turned off. SWDAT is the write data for the Serial Transceiver
Control (STC). Do NOT float this pin.
8
-
VLED
LED Supply Voltage
EMI Shield
May be unregulated, 2.7 to 5.5 volts.
SHIELD
Connect to system ground via a low inductance trace. For best
performance, do not connect to GND directly at the part.
2
Recommended Application Circuit Components
Component
Recommended Value
6.8 µF, ± 20%, Tantalum
1.0 µF, ± 20%, Tantalum
0.47 µF, ± 20%, Ceramic
Notes
C1
1
C2
C3
Note:
1. C1, which is optional, must be placed within 0.7 cm of the HSDL-3210 to obtain optimum noise immunity.
Serial Interface for
Transceiver Control
The Serial Interface for
Transceiver Control (STC) is used
to control and program the
features of the transceiver. These
features include input/output
(I/O) control, optical power
adjustment and shut down.
The STC requires three signals: a
serial clock (SCLK) that is used
for timing, and two unidirectional
lines multiplexed with the
transmitter (write) TXD/SWDAT
and receiver (read) RXD/SRDAT
infrared signal lines.
the TXD line, disable/enable the
RXD line and 4-level optical
power adjustment.
A set of commands is provided to
handle the programming control
features. The general command
format is shown in Figure 3. The
HSDL-3210 STC Write Data
The HSDL-3210 supports the
write function to disable/enable
Commands are shown in Table 1.
ADDRESS [2-0]
INDEX [3-0]
C
DATA
Figure 3. General command format.
Table 1. Serial Interface for Transceiver Control – Write Data Format
Address [2-0]
Index [3-0]
C
Data
IrDA Data –data rates
SIR (2.4 to 115.2 Kbps)
MIR (0.576, 1.152 Mbps)
I/O Control
000
000
0001
0001
1
1
00000000
00000001
SD Normal Mode
SD Sleep Mode
RXD disable
000
000
000
000
000
000
0000
0000
0000
0000
0000
0000
1
1
1
1
1
1
XXXXXXX1
XXXXXXX0
XXXXXX0X
XXXXXX1X
XXXXX0XX
XXXXX1XX
RXD enable
TXD disable
TXD enable
Optical Power Adjustment
10% link distance
25% link distance
50% link distance
100% link distance
000
000
000
000
0010
0010
0010
0010
1
1
1
1
00XXXXXX
01XXXXXX
10XXXXXX
11XXXXXX
3
Table 2. Serial Interface for Transceiver Control – Read Data Format
Address [2-0]
Index [3-0]
C
Data
IrDA Data –data rates
SIR (2.4 to 115.2 Kbps)
MIR (0.576, 1.152 Mbps)
I/O Control
000
000
0001
0001
0
0
00000000
00000001
SD Normal Mode
SD Sleep Mode
RXD disable
000
000
000
000
000
000
0000
0000
0000
0000
0000
0000
0
0
0
0
0
0
XXXXXXX0
XXXXXXX1
XXXXXX0X
XXXXXX1X
XXXXX0XX
XXXXX1XX
RXD enable
TXD disable
TXD enable
Optical Power Adjustment
10% link distance
25% link distance
50% link distance
100% link distance
ID
000
000
000
000
0010
0010
0010
0010
0
0
0
0
00XXXXXX
01XXXXXX
10XXXXXX
11XXXXXX
Manufacturer
Product
000
000
1111
1111
0
0
00000001
01000001
.
Transceiver I/O Truth Table
STC SD Mode
SCLK
SD
TXD
LED
Receiver
RXD
Notes
2,3
Normal Mode
Low
Low
High
Low
On
Don’t care
IrDA Signal
No Signal
Don’t care
Don’t care
Not Valid
Low
Off
4,5
High
Sleep Mode
Don’t care
Notes:
Don’t care
Don’t care
Off
Off
High
6
6
Don’t care
High
High
2. If TXD is stuck in the high state, the LED will turn off after about 14 µs.
3. RXD will echo the TXD signal while TXD is transmitting data.
4. In-Band IrDA signals and data rates ≤ 1.152 Mbps.
5. RXD Logic Low is pulsed response.
6. RXD Logic High during shutdown is a weak pull up (equivalent to an approximately 300 kΩ resistor).
4
Ca ution: The BiCMOS inher ent to this design of this component incr ea ses the component’s
susceptibility to da ma ge fr om electr osta tic discha r ge (ESD). It is a dvised tha t nor ma l sta tic
pr eca utions be ta ken in ha ndling a nd a ssembly of this component to pr event da ma ge a nd/ or
degr a da tion which ma y be induced by ESD.
Absolute Maximum Ratings
For implementations where case to ambient thermal resistance is ≤50°C/W.
Parameter
Symbol
Min.
-40
-25
0
Max.
100
85
Units
°C
°C
V
Storage Temperature
Operating Temperature
LED Supply Voltage
Supply Voltage
T
S
T
A
V
LED
6.5
V
CC
0
6.5
V
Input/Output Voltage
Input Voltage: TXD, SCLK, SD
Output Voltage: RXD
IOV
0
V
V
CC
CC
V
I
0
V + 0.5
CC
V
V
O
-0.5
V + 0.5
CC
V
Recommended Operating Conditions
Parameter
Symbol Min.
Max.
Units
°C
V
Conditions
Notes
Operating Temperature
Supply Voltage
T
-25
2.7
85
A
V
3.6
CC
Logic Input Voltage
for TXD ,SCLK, SD
Logic High
Logic Low
V
2/3 IOV
IOV
V
1.5 V ≤IOV ≤3.6 V
CC
IH
CC
CC
V
IL
0
1/3 IOV
V
1.5 V ≤IOV ≤3.6 V
CC
CC
2
Logic High Receiver
Input Irradiance EIH
EI
0.0081
500
500
0.3
mW/cm
For in-band signals
≤115.2kb/s (SIR)
7
7
H
2
0.0225
mW/cm
0.576 Mb/s ≤ in-band
signals ≤ 1.15 Mb/s (MIR)
2
Logic Low Receiver Input
Input/Output Voltage
Receiver Data Rate
EI
L
µW/cm
V
For in-band signals.
IOV
1.5
V
CC
CC
0.0024
1.152
Mb/s
5
Electrical and Optical Specifications
Specifications hold over the recommended operating conditions unless otherwise noted. Unspecified test conditions may be
anywhere in their operating range. All typical values are at 25°C and 3.0 V unless otherwise noted.
Parameter
Symbol
Min.
Typ. Max. Units Conditions
Notes
Receiver
RXD Output Voltage
Logic High
Logic Low
V
IOV -0.2
IOV
V
I =-200 µA, EI ≤0.3
OH
µW/cm
OH
CC
CC
2
V
OL
0
0.4
V
I =200 µA
OL
8
Viewing Angle
2φ
1/2
30
°
Peak Sensitivity Wavelength
RXD Pulse Width (SIR)
RXD Pulse Width (MIR)
RXD Rise and Fall Times
Receiver Latency Time
Receiver Wake Up Time
Transmitter
λp
880
nm
µs
ns
ns
µs
µs
t
(SIR)
1
7.5
750
100
50
C =10 pF
8,9
9
PW
L
t
(MIR) 200
C =10 pF
L
PW
t , t
R
25
25
30
C =10 pF
L
F
t
t
10
11
L
100
RW
Radiant Intensity (SIR)
Radiant Intensity (MIR)
Peak Wavelength
IE
4
9
15
28.8
72
mW/Sr T =25°C, θ ≤15°, TXD ≥ V
A 1/2 IH
H
IE
H
30
mW/Sr T =25°C, θ ≤15°, TXD ≥ V
A 1/2 IH
λp
875
35
nm
nm
°
Spectral Line Half Width
Viewing Angle
∆λ
1/2
2φ
30
60
1/2
Optical Pulse Width (SIR)
tpw
1.41
1.6
2.23
µs
tpw(TXD) = 1.6 µs
Optical Pulse Width
(MIR, IOV ≥1.5 V)
tpw
148
217
50
260
600
ns
ns
tpw(TXD) = 217 ns
CC
Optical Rise and Fall Times (SIR)
tr (EI)
tf (EI)
tpw(TXD) = 1.6 µs
Optical Rise and Fall Times (MIR)
tr (EI)
tf (EI)
30
40
ns
tpw(TXD) = 1.6 µs
LED Current
On (SIR)
I
60
72
180
1
mA
mA
µs
V
=V =3.6 V, V (TXD) ≥ V
VLED
VLED CC I IH
On (MIR)
Current Off
I
150
0.005
V
=V =3.6 V, V (TXD) ≥ V
VLED
VLED CC I IH
I
V
=V =3.6 V, V (TXD) ≤ V
VLED
VLED CC I IL
Transceiver
TXD Input Current
High
I
10
200
nA
nA
µA
V ≥ V
I IH
H
Low
I
L
-10
0.01
-200
0 ≤ V ≤ V
I IL
Supply Current
Shutdown
I
CC1
V =3.6 V, V ≥ V - 0.5,
CC SD CC
T =25°C
A
Idle
I
300
0.8
450
3.0
µA
V =3.6 V, V (TXD) ≤ V ,EI=0
CC I IL
CC2
Active,
I
CC3
mA
V =3.6 V, V (TXD) ≤ V
IL
12,13
CC
I
Receive
Notes:
7. An in-band optical signal is a pulse/sequence where the peak wavelength, λp, is defined as 850 nm ≤ λp ≤ 900 nm,
and the pulse characteristics are compliant with the IrDA Serial Infrared Physical Layer Link Specification.
2
2
8. For in band signals ≤ 1.152 Mbps where 9 µW/cm ≤ EI ≤ 500 mW/cm .
2
2
9. For 0.576 Mbps ≤ in band signals ≤ 1.152 Mbps where 22.5 µW/cm ≤ EI ≤ 500 mW/cm .
10. Latency is defined as the time from the last TXD light output pulse until the receiver has recovered full sensitivity.
11. Receiver wake up time is measured from the SD pin high to low transition or V power on, to valid RXD output.
CC
2
12. Typical values are at EI = 10 mW/cm .
2
13. Maximum value is at EI = 500 mW/cm .
6
t
pw
V
OH
90%
50%
10%
V
OL
t
t
r
f
Figure 4. RXD output waveform.
t
pw
LED ON
90%
50%
10%
LED OFF
t
t
f
r
Figure 5. LED optical waveform.
TXD
LED
t
pw (MAX.)
Figure 6. TXD ‘Stuck On’ protection waveform.
SD
RX
LIGHT
RXD
t
RW
Figure 7. Receiver wakeup time waveform.
7
Package Dimensions
MOUNTING
CENTER
4.0
1.025
C
L
2.05
RECEIVER
EMITTER
2.2
2.5
1.175
1.05
1.25
0.35
0.65
0.80
2.85
COPLANARITY:
0 to -0.2 mm
2.55
4.0
8.0
3.0
2.9
1.85
C
L
UNIT: mm
TOLERANCE: ± 0.2 mm
COPLANARITY: 0.1 mm MAX.
PIN 1
0.6
3.325
6.65
Figure 8. Package outline dimensions.
8
Tape and Reel Dimensions
4.0 ± 0.1
+ 0.1
UNIT: mm
1.75 ± 0.1
1.5
1.5 ± 0.1
0
POLARITY
PIN 8: LED A
7.5 ± 0.1
16.0 ± 0.2
8.4 ± 0.1
3.4 ± 0.1
PIN 1: CX
0.4 ± 0.05
2.8 ± 0.1
8.0 ± 0.1
PROGRESSIVE DIRECTION
EMPTY
PARTS MOUNTED
LEADER
(400 mm MIN.)
(40 mm MIN.)
EMPTY
(40 mm MIN.)
OPTION # "B" "C" QUANTITY
001
021
178 60
330 80
500
2500
UNIT: mm
DETAIL A
2.0 ± 0.5
B
C
13.0 ± 0.5
R 1.0
LABEL
21 ± 0.8
DETAIL A
+ 2
0
16.4
2.0 ± 0.5
Figure 9. Tape and reel dimensions.
9
Moisture-Proof Packaging
All HSDL-3210 options are shipped in moisture-proof packaging. Once opened, moisture absorption begins.
This product is compliant to JEDEC level 4.
UNITS IN A SEALED
MOISTURE-PROOF
PACKAGE
PACKAGE IS
OPENED (UNSEALED)
ENVIRONMENT
LESS THAN 30°C,
AND LESS THAN
60% RH
YES
PACKAGE IS
OPENED LESS
THAN 72 HOURS
NO BAKING
IS NECESSARY
YES
NO
PERFORM RECOMMENDED
BAKING CONDITIONS
NO
Figure 10. Baking conditions chart.
Baking Conditions
Recommended Storage
Conditions
If the parts are not stored in dry
conditions, they must be baked
before reflow to prevent damage
to the parts.
Storage Temp.
10˚C to 30˚C
Below 60% RH
Relative Humidity
Time from Unsealing to Soldering
After removal from the bag, the
parts should be soldered within
three days if stored at the recom-
mended storage conditions.
Packaging
In Reels
In Bulk
Temp.
60˚C
Time
≥ 48 hours
≥ 4 hours
≥ 2 hours
≥ 1 hour
100˚C
125˚C
150˚C
Baking should only be done once.
10
Reflow Profile
MAX. 245°C
R3 R4
230
200
183
170
R2
150
90 sec.
MAX.
125
100
ABOVE
183°C
R1
R5
50
25
0
50
100
150
200
250
300
t-TIME (SECONDS)
P1
HEAT
UP
P2
SOLDER PASTE DRY
P3
SOLDER
REFLOW
P4
COOL
DOWN
Figure 11. Reflow graph.
Process Zone
Heat Up
Symbol
P1, R1
P2, R2
∆T
Maximum ∆T/∆time
4˚C/s
25˚C to 125˚C
125˚C to 170˚C
Solder Paste Dry
Solder Reflow
0.5˚C/s
P3, R3
P3, R4
170˚C to 230˚C (245˚C at 10 seconds max.)
230˚C to 170˚C
4˚C/s
–4˚C/s
Cool Down
P4, R5
170˚C to 25˚C
–3˚C/s
The reflow profile is a straight
line representation of a nominal
temperature profile for a convec-
tive reflow solder process. The
temperature profile is divided
into four process zones, each
with different ∆T/∆time tempera-
ture change rates. The ∆T/∆time
rates are detailed in the above
table. The temperatures are
Process zone P2 should be of
sufficient time duration (> 60
seconds) to dry the solder paste.
The temperature is raised to a
level just below the liquidus point
of the solder, usually 170°C
(338°F).
metallic growth within the solder
connections becomes excessive,
resulting in the formation of weak
and unreliable connections. The
temperature is then rapidly
reduced to a point below the
solidus temperature of the solder,
usually 170°C (338°F), to allow
the solder within the connections
to freeze solid.
Process zone P3 is the solder
reflow zone. In zone P3, the tem-
perature is quickly raised above
the liquidus point of solder to
230°C (446°F) for optimum
measured at the component to
printed circuit board connections.
Process zone P4 is the cool down
after solder freeze. The cool
In process zone P1, the PC board
and HSDL-3210 castellation I/O
pins are heated to a temperature
of 125°C to activate the flux in
the solder paste. The temperature
ramp up rate, R1, is limited to
4°C per second to allow for even
heating of both the PC board and
HSDL-3210 castellation I/O pins.
results. The dwell time above the
liquidus point of solder should be
between 15 and 90 seconds. It
usually takes about 15 seconds to
assure proper coalescing of the
solder balls into liquid solder and
the formation of good solder
connections. Beyond a dwell
time of 90 seconds, the inter-
down rate, R5, from the liquidus
point of the solder to 25°C (77°F)
should not exceed –3°C per sec-
ond maximum. This limitation is
necessary to allow the PC board
and HSDL-3210 castellation I/O
pins to change dimensions
evenly, putting minimal stresses
on the HSDL-3210 transceiver.
11
Appendix A : SMT Assembly Application Note
1.0 Solder Pad, Mask and Metal Solder Stencil Aperture
METAL STENCIL
FOR SOLDER PASTE
PRINTING
STENCIL
APERTURE
LAND
PATTERN
SOLDER
MASK
PCBA
Figure 12. Stencil and PCBA.
1.1 Recommended Land Pattern
C
L
SHIELD
SOLDER PAD
1.35
MOUNTING
CENTER
1.25
2.05
0.10
0.775
1.75
FIDUCIAL
0.60
0.475
1.425
UNIT: mm
2.375
3.325
Figure 13. Land pattern.
12
1.2 Recommended Metal Solder
Stencil Aperture
It is recommended that only a
0.152 mm (0.006 inches) or a
0.127 mm (0.005 inches) thick
stencil be used for solder paste
printing. This is to ensure ad-
equate printed solder paste vol-
ume and no shorting. See the
table below the drawing for com-
binations of metal stencil aper-
ture and metal stencil thickness
that should be used.
APERTURES AS PER
LAND DIMENSIONS
t
w
l
Aperture opening for shield pad
is 2.7 mm x 1.25 mm as per land
pattern.
Figure 14. Solder stencil aperture.
Stencil Thickness, t (mm)
Aperture Size (mm)
Length, l
Width, w
0.55 ± 0.05
0.55 ± 0.05
0.152 mm
0.127 mm
2.60 ± 0.05
3.00 ± 0.05
8.2
1.3 Adjacent Land Keepout and
Solder Mask Areas
Adjacent land keep-out is the
maximum space occupied by
the unit relative to the land pat-
tern. There should be no other
SMD components within this
area.
0.2
3.1
The minimum solder resist strip
width required to avoid solder
bridging adjacent pads is
0.2 mm. It is recommended that
two fiducial crosses be placed at
mid-length of the pads for unit
alignment.
SOLDER MASK
3.0
UNITS: mm
Not e: Wet/Liquid Photo-
Imageable solder resist/mask is
recommended.
Figure 15. Adjacent land keep-out and solder mask areas.
13
2. The shield trace is a wide, low
inductance trace back to the
system ground.
Appendix B: PCB Layout
Suggestion
The following PCB layout shows
a recommended layout that
should result in good electrical
and EMI performance. Things to
note:
A reference layout of a 2-layer
Avago evaluation board for
HSDL-3210 based on the
guidelines stated above is shown
below. For more details, please
refer to Avago Application Note
1114, Infrared Transceiver PC
Board Layout for Noise
3. C1 is an optional V filter
CC
capacitor. It may be left out if
the V is clean.
CC
4. V
can be connected to
LED
either unfiltered or unregulated
power. If C1 is used, and if
Immunity.
1. The ground plane should be
continuous under the part, but
should not extend under the
shield trace.
V
is connected to V , the
LED
CC
connection should be before
the C1 cap.
Top Layer
Bottom Layer
Figure 16. PCB layout suggestions.
14
Appendix C: General
Interface to Recommended I/O chips
1.152 Mb/s, and supports HP-SIR
and TV Remote modes. The
design of the HSDL-3210 also
includes the following unique
features:
Application Guide for the
The HSDL-3210’s TXD data input
is buffered to allow for CMOS
drive levels. No peaking circuit or
capacitor is required. Data rate
from 9.6 kb/s up to 1.152 Mbp/s
is available at the RXD pin.
®
HSDL-3210 Infrared IrDA
Compliant 1.15 Mb/s
Transceiver
Description
• Supports the serial interface for
transceiver control (STC)
specification.
The HSDL-3210, a low-cost and
small form factor infrared
transceiver, is designed to
address the mobile computing
market such as PDAs, as well as
small embedded mobile products
such as digital cameras and
cellular phones. It is fully
The block diagram below shows
how the IR port fits into a mobile
phone and PDA platform.
• Low passive component count.
• Shutdown mode for low power
consumption requirement.
• Interface to input/output logic
circuits as low as 1.5 V.
• Adjustable optical power
management
compliant to IrDA 1.3 low power
specification from 9.6 kb/s to
SPEAKER
AUDIO INTERFACE
DSP CORE
MICROPHONE
ASIC
CONTROLLER
RF INTERFACE
TRANSCEIVER
MOD/
DE-MODULATOR
IR
MICROCONTROLLER
USER INTERFACE
MOBILE PHONE PLATFORM
LCD
PANEL
RAM
ROM
IR
CPU
FOR EMBEDDED
APPLICATION
PCMCIA
CONTROLLER
TOUCH
PANEL
COM
PORT
RS232C
DRIVER
PDA PLATFORM
Figure 17. Mobile phone and PDA platform diagrams.
15
Serial Interface Transceiver Control
(STC)
operating modes and states, thus
electrical interface can be
standardized across different
vendors and transceivers.
Activity on the SCLK line
determines whether the trans-
ceiver is to operate in the normal
or STC mode.
HSDL-3210 supports the serial
interface for transceiver control
specification that provides a
common interface between the
transceiver and controller.
The diagram below shows the
STC I/O between the transceiver
and the IrDA controller.
Please refer to Avago Application
Note 1270 Serial Transceiver
Control for Infrared Transceivers
for further information on
implementing STC using HSDL-
3210 as well as the lists of
registers supported by HSDL-
3210.
STC comprises a 3-wire interface:
TXD/SWDAT, RXD/ARDAT and
SCLK. This 3-wire interface
abolishes the use of different
modes and logic pins of existing
transceivers. Instead registers on
board the transceiver store
In normal operation, the TXD and
RXD carry IR transmit and
receive signals. In STC mode,
SWDAT and SRDAT carry
command and responses to and
from the transceiver respectively.
TXD
RXD
INFRARED CONTROLLER
(MASTER)
SCLK
TRANSCEIVER (SLAVE)
STC – NORMAL MODE
SWDAT
(WRITE COMMAND)
SRDAT
(SEND RESPONSES)
INFRARED CONTROLLER
(MASTER)
SCLK
(CLOCK COMMAND / RESPONSE)
TRANSCEIVER (SLAVE)
/ RESPONSE MODE
STC – COMMAND
Figure 18. STC block diagram.
16
7
7
7
0
0
0
STC Bus Protocol and Timing
Diagrams
INDX (4)
C (1)
1st BYTE
2nd BYTE
3rd BYTE
ADDR (3)
Bus Protocol
A set of commands is provided to
handle the various transactions
between the master and the slave.
The general format is shown in
Figure 19 whereby communica-
tions consist of a mandatory
command phase followed by an
optional response phase. The
response phase occurs only when
the slave needs to respond to a
command.
DATA (SLAVE RESPONSE) or E_INDX (8)
DATA (SLAVE RESPONSE) (8)
Figure 19. General command format.
The command format consists of
either 2 or 3 bytes command.
The first byte, which is manda-
tory and common to all trans-
actions, consists of the address/
index/control bits. There are two
control fields. The first one is the
“C” field which determines
Write Transactions
Write transactions are when the
master writes data to the slave to
select the slave’s operational
mode. This requires only the
command phase as shown below.
whether the command is a read
or write operation or to act as a
qualifier for a special operation.
The second one is the “INDX”
field whereby certain patterns
define Special Transactions while
others are for normal Data Trans-
actions. The “ADDR” field is used
to specify which transceiver the
command is for. In a single
transceiver system, this field is
set to “000”.
1
INDX [3:0]
ADDR [2:0]
ADDR [2:0]
DATA
1
1
1
1
1
E_INDX[7:0]
DATA
Figure 20. Write command phase format.
Read Transactions
Read transactions occur when the
master queries the internal regis-
ters of the slave. The initial com-
mand phase is always followed by
the response phase from the
slave as shown below.
The second byte contains the
data payload for a 2 byte com-
mand. For a 3 byte command,
this second byte is an 8 bit
extended index.
INDX [3:0]
0
0
ADDR [2:0]
ADDR [2:0]
The third byte is the data payload
when the extended index is used.
1
1
1
1
E_INDX[7:0]
Figure 21a. Read command phase format.
DATA
Figure 21b. Slave response format.
17
Bus Timing Diagrams
5. The first low-to-high transition
of SCLK indicates that an STC
transition is pending. On re-
ceipt of his rising edge, the slave
will disable the LED. The next
SCLK low-to-high transition
indicates the start cycle, fol-
lowed by the command phase
(which the controller puts out
on the SWDAT line). The LED
needs to be disabled since TXD
and SWDAT are multiplexed. If
the LED is not disabled, then
the LED will pulse according to
the SWDAT bit stream.
8. During a READ transaction, the
controller holds the SWDAT line
low for 1 clock after sending the
ADDRESS and INDEX byte. It
then holds it high and low for 3
clocks before the end of the
The bus timings are designed to
be simple and to minimize the
effects of timing skew. This sec-
tion discusses some key points
with regard to bus timings and
illustrates typical STC transac-
tions with the use of waveforms.
transaction. This is to allow the
transceiver to monitor the im-
pending end of a transaction
rather than by counting pulses.
Bus Timing Notes
9. When powered up, the trans-
ceiver is not ready to perform IR
transmissions. The controller
has to initialize the transceiver.
The brief powered up sequences
are:
1. Data is transferred in Little
Endian order, that is, the LSB
on the first byte is transmitted
first and the MSB of the second
or third byte is transmitted last.
6. The LED is re-enabled (by the
slave) on the last SCLK of the
STC transaction bit stream.
Normal infrared transmission
can resume. No SCLK transi-
tions should take place until the
next STC transaction else the
LED will be disabled.
2. There are no gaps between bytes
in the command or response
phases.
9.1. On power up, an inter-
nally generated signal in the
transceiver sets the 3 con-
trol registers:
3. Each byte in the command and
response phase is preceded by a
start bit on the SCLK line.
a) Control Register 0:
• Bit 0: shutdown mode
• Bit 1: RXD disabled
• Bit 2: LED disabled
b) Control Register 1:
• Bit 0-7: SIR mode
4. For data sampling and clocking,
4.1. Input data is sampled on
the rising edge of SCLK.
7. The response from the slave is
carried on the SRDAT line,
which is multiplexed with RXD.
The detector is (internally) dis-
abled by the slave during the
response phase. This is to pre-
vent stray IR transitions from
corrupting the SRDAT bit
stream.
4.2. Output data from the con-
troller is clocked out on the
falling edge of SCLK.
c) Control Register 2:
4.3. Output data from the slave
is clocked out on the rising
edge of SCLK.
• Bit 0-7: Power at 100%
level
9.2. The controller has to initial-
ize the transceiver by:
a) Hold SWDAT low
b) Toggle SCLK for at least
30 cycles
The transceiver is in STC mode
and ready to accept STC
transactions.
18
Bus Timing Sample Waveforms
The following diagrams are
sample waveforms for 2 byte
write and read transactions and a
3 byte read transaction.
(A) SET CONTROL REGISTER 1 TO MIR MODE
1st BYTE
2nd BYTE
DATA
START C BIT
INDEX
ADDRESS
START
SCLK
SWDAT
SRDAT
DON'T CARE
LED_DIS
(INTERNAL)
Figure 22. Write waveform – set control register 1 to MIR mode.
(B) READ FROM CONTROL REGISTER 2
1st BYTE
2nd BYTE
DATA
START C BIT
INDEX
ADDRESS
START
SCLK
SWDAT
SRDAT
DON'T CARE
LED_DIS
(INTERNAL)
STC_RXD_EN
(INTERNAL)
Figure 23. Read waveform – read from control register 2 (transmitter power level).
19
(C) READ DEVICE ID
1st BYTE
INDEX
2nd BYTE
DATA
3rd BYTE
DATA
START C BIT
ADDRESS START
START
SCLK
SWDAT
SRDAT
DON'T CARE
DON'T CARE
LED_DIS
(INTERNAL)
STC_RXD_EN
(INTERNAL)
Figure 24. Extended index read waveform – read device ID.
Electrical Specifications
Timing specifications are given in the table and diagram below.
Symbol Parameter Min. Max. Units
tCKp
tCKh
tCKl
SCLK Clock Period
250
60
∞
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK Clock High Time
SCLK Clock Low Time
80
tDOtv
tDOth
tDOrv
tDOrh
tDOrf
tDIs
Output Data Valid (from infrared controller)
Output Data Hold (from infrared controller)
Output Data Valid (from optical transceiver)
Output Data Hold (from optical transceiver)
Line float Delay
40
0
40
40
60
Input Data Setup
10
5
tDIh
Input Data Hold
tCKh
tCKl
tCKp
SCLK
tDOtv
tDOth
IRTX/SWDAT
IRRX/SRDAT
tDls
tDlh
tDOrv
tDOrh
tDOrf
Figure 25. Timing diagram.
The link distance testing was done using typical HSDL-3210 units with National Semiconductor’s PC87109 3V Super I/O controller and SMC’s FDC37C669
and FDC37N769 Super I/O controllers. An IR link distance of up to 40 cm was demonstrated for SIR at full power. On the other hand, for MIR at full power,
an IR link distance of up to 35 cm was demonstrated.
20
from the HSDL-3210 to the back
of the window. The distance from
the center of the LED lens to the
center of the photodiode lens, K,
is 5.1 mm. The equations for
computing the window dimen-
sions are as follows:
are comparable, Z' replaces Z in
the above equation. Z' is defined
as:
Appendix D: Optical port
dimensions for HSDL-3210
To ensure IrDA compliance, some
constraints on the height and
width of the window exist. The
minimum dimensions ensure that
the IrDA cone angles are met
without vignetting. The maximum
dimensions minimize the effects
of stray light. The minimum size
corresponds to a cone angle of
30˚ and the maximum size corre-
sponds to a cone angle of 60˚ .
Z' = Z + t/n
where ‘t’ is the thickness of the
window and ‘n’ is the refractive
index of the window material.
X = K + 2*(Z + D)*tanA
Y = 2*(Z + D)*tanA
The depth of the LED image in-
side the HSDL-3210, D, is
The above equations assume that
the thickness of the window is
negligible compared to the dis-
tance of the module from the
back of the window (Z). If they
3.17 mm. ‘A’ is the required half
angle for viewing. For IrDA com-
pliance, the minimum is 15˚ and
the maximum is 30˚ . Assuming
the thickness of the window to be
negligible, the equations result in
the following tables and graphs.
In the figure below, X is the width
of the window, Y is the height of
the window, and Z is the distance
OPAQUE
IR TRANSPARENT WINDOW
MATERIAL
Y
X
K
IR TRANSPARENT
WINDOW
OPAQUE
MATERIAL
Z
A
D
Figure 26. Window design diagram.
21
Module Depth
Aperture Width (x, mm)
Aperture Height (y, mm)
(z) mm
Max.
8.76
Min.
6.80
Max.
3.66
Min.
1.70
2.33
2.77
3.31
3.84
4.38
4.91
5.45
5.99
6.52
0
1
2
3
4
5
6
7
8
9
9.92
7.33
4.82
11.07
12.22
13.38
14.53
15.69
16.84
18.00
19.15
7.87
5.97
8.41
7.12
8.94
8.28
9.48
9.43
10.01
10.55
11.09
11.62
10.59
11.74
12.90
14.05
APERTURE WIDTH (X) vs. MODULE DEPTH
25
APERTURE HEIGHT (Y) vs. MODULE DEPTH
16
14
12
10
8
20
15
10
6
4
X MAX.
X MIN.
5
Y MAX.
Y MIN.
2
0
0
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
MODULE DEPTH (Z) – mm
MODULE DEPTH (Z) – mm
Figure 27. Aperture width (X) vs. module depth.
Figure 28. Aperture height (Y) vs. module depth.
Window Material
Shape of the Window
the radiation pattern is dependent
upon the material chosen for the
window, the radius of the front
and back curves, and the distance
from the back surface to the
transceiver. Once these items are
known, a lens design can be
made which will eliminate the
effect of the front surface curve.
Almost any plastic material will
work as a window material. Poly-
carbonate is recommended. The
surface finish of the plastic
should be smooth, without any
texture. An IR filter dye may be
used in the window to make it
look black to the eye, but the
total optical loss of the window
should be 10% or less for best
optical performance. Light loss
should be measured at 875 nm.
From an optics standpoint, the
window should be flat. This en-
sures that the window will not
alter either the radiation pattern
of the LED, or the receive pattern
of the photodiode.
If the window must be curved for
mechanical or industrial design
reasons, place the same curve on
the back side of the window that
has an identical radius as the
front side. While this will not
completely eliminate the lens
effect of the front curved surface,
it will significantly reduce the
effects. The amount of change in
The following drawings show the
effects of a curved window on the
radiation pattern. In all cases,
the center thickness of the win-
dow is 1.5 mm, the window is
made of polycarbonate plastic,
and the distance from the trans-
ceiver to the back surface of the
window is 3 mm.
The recommended plastic
materials for use as a cosmetic
window are available from
General Electric Plastics.
Recommended Plastic Materials:
Material
Number
Light
Transmission
Haze
Refractive
Index
Lexan 141L
88%
1%
1%
1%
1.586
1.586
1.586
Lexan 920A 85%
Lexan 940A 85%
Note: 920A and 940A are more flame retardant than 141L.
Recommended Dye: Violet #21051 (IR transmissant above 625 nm).
Flat Window
(First Choice)
Curved Front and Back
(Second Choice)
Curved Front, Flat Back
(Do Not Use)
Figure 29. Shape of windows.
For product information and a complete list of distributors, please go to our website: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countries.
Data subject to change. Copyright © 2006 Avago Technologies Pte. All rights reserved. Obsoletes 5988-8480EN
5989-4390EN May 28, 2006
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