HSDL-3310#007 [ETC]
Telecomm/Datacomm ; 电信/数据通信\n
| 型号： | HSDL-3310#007 |
| 厂家： | 
ETC |
| 描述： | Telecomm/Datacomm
|
| 文件： | 总18页 (文件大小：241K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Agilent HSDL-3310
®
IrDA Data Compliant
1.152 Mb/s Infrared Transceiver
Data Sheet
Features
• Fully compliant to IrDA 1.3
specifications:
– 2.4 kb/s to 1.152 Mb/s
– Excellent nose-to-nose operation
– Typical link distance > 1.5 m
Functional Description
The HSDL-3310 can be shut down
completely to achieve very low
power consumption. In the shut-
down mode, the PIN diode will be
inactive and thus producing very
little photocurrent even under
very bright ambient light. Also,
HSDL-3310 incorporates adjust-
able optical power feature to
• Guaranteed temperature
performance, –20 to 70 °C
– Critical parameters are
guaranteed over specified
temperatures and supply voltages
The HSDL-3310 is a small form
factor infrared (IR) transceiver
module that provides interface
between logic and IR signals for
through-air, serial, half-duplex IR
data link. The module is compliant
to IrDA physical layer specifications
1.3 and is IEC 825-Class 1
• Low power consumption
– Low shutdown current
(10 nA typical)
– Complete shutdown for
TXD, RXD, and PIN diode
enhance low power consumption.
eye safe.
The HSDL-3310 is designed to
interface with input/output logic
circuits as low as 1.8 V.
• Input/output interfacing voltage of
as low as 1.8 V
Applications
• Mobile telecommunication
– Cellular phone
– Pager
• Small module size
– 4 x 10 x 5 mm max (H x W x D)
• Adjustable optical power
management
– Adjustable LED driver current
for saving power while
maintaining link integrity
– Smart phone
• Data communication
– PDA
– Printer
• Digital imaging
– Digital camera
– Photo-imaging printer
• Typically withstands >100 mV
power supply ripple
p-p
• V supply 2.7 to 5.5 volts
CC
• Electronic wallet
• Integrated EMI shield
• Medical and industry data
collection
• LED stuck-high protection
CX2
CX1
R1
Functional Block Diagram
LEDA (9)
V
(3)
CC
I/0 V
(2)
CC
CX3
ADJUSTABLE
OPTICAL
POWER
TXD (8)
MD0 (5)
MD1 (6)
SHIELD
HSDL-3310
RXD (7)
MIR_SEL (4)
GND (1)
REAR VIEW
Pinout
9
8
6
5
4
3
2
1
7
I/O Pins Configuration Table
Pin Symbol
Description
Note
1
2
GND
I/OV
Ground
Connect to system ground.
Input/Output ASIC V
Connect to ASIC logic controller V voltage or supply voltage. The voltage
at this pin must be equal to or less than supply voltage.
CC
CC
CC
3
4
V
CC
Supply Voltage
Regulated 2.7 to 5.5 volts.
MIR_SEL MIR Select
This pin to be driven high to select MIR mode and low for SIR mode.
Do not float this pin.
5
6
7
MD0
MD1
RXD
Mode 0
Mode 1
This pin must be driven either high or low. Do not float this pin.
This pin must be driven either high or low. Do not float the pin.
Receiver Data Output. Output is a low pulse response when a light pulse is seen.
Active Low. Active low.
Transmitter Data Input. Logic high turns the LED on. If held high longer than ~ 50 µs, the LED is turned
8
TXD
Active High.
LED Anode
EMI Shield
off. TXD must be either driven high or low. Do not float this pin.
9
LEDA
Tied to external resistor, R1, to regulated V from 2.7 to 5.5 volts.
CC
–
SHIELD
Do not connect shield directly to ground pin; connect to system ground via a
low inductance trace.
2
Transceiver Control Truth Table
MD0
MD1
MIR_SEL
RXD
Shutdown
SIR
TXD
1
0
0
1
0
0
1
0
0
1
1
0
1
1
X
0
0
0
1
1
1
Shutdown
Full Distance Power
50 cm Distance Power
30 cm Distance Power
Full Distance Power
50 cm Distance Power
30 cm Distance Power
SIR
SIR
MIR
MIR
MIR
X = Don’t care
Transceiver I/O Truth Table
Inputs
Outputs
Transceiver Mode
Active
MIR_SEL
TXD
EI
X
IE (LED)
RXD
NV
X
0
≥ V
≤ V
≤ V
≤ V
High (On)
Low (Off)
Low (Off)
Low (Off)
Low (Off)
IH
IL
IL
IL
[1]
[2]
[3]
Active
EI
EI
EI
Low
Low
H
H
L
[3]
Active
1
Active
X
X
High
[4]
[5]
Shutdown
X
Low (Off)
NV
X = Don’t care
NV = Not valid
EI = In-Band infrared intensity at detector
Notes:
1. In-Band EI ≤ 115.2 kb/s and MIR_SEL=0
2. In-Band EI ≥ 0.576 Mb/s and MIR_SEL=1
3. Logic low is a pulsed response.
4. To maintain low shutdown current, TXD needs to be driven high or low and not to be left floating.
5. RXD is internally pull-up to V through high impedance PMOS transistor (equivalent impedance is greater than 300 kΩ).
CC
Recommended Application Circuit Components
Component
Recommended Value
2.2 Ω ± 5%, 0.5 Watt, for 2.7 ≤ V ≤ 3.3 V operation
R1
CC
2.7 Ω ± 5%, 0.5 Watt, for 3.0 ≤ V ≤ 3.6 V operation
CC
5.6 Ω ± 5%, 0.5 Watt, for 4.5 ≤ V ≤ 5.5 V operation
CC
[1]
CX1 , CX3
0.47 µF ± 20%, X7R Ceramic
6.8 µF ± 20%, Tantalum
[2]
CX2
Notes:
1. CX1 must be placed within 0.7 cm from HSDL-3310 for optimum noise immunity.
2. When using with noisy power supplies, supply rejection can be enhanced by including CX2 as
shown in ”HSDL-3310 Functional Block Diagram.“
Caution: The component is susceptibile to damage from electrostatic discharge. It is advised that
normal static precautions be taken during handling and assembling of this component to prevent
damage and/or degradation, which may be caused by ESD.
3
Absolute Maximum Ratings
For implementations where case to ambient thermal resistance is ≤ 50°C/W.
Parameter
Symbol
Min.
–40
–20
0
Max.
Units
°C
°C
V
Storage Temperature
Operating Temperature
LED Supply Voltage
Supply Voltage
T
T
100
70
7
S
A
V
V
LED
0
7
V
CC
Input/Output Voltage
Input Voltage: TXD, MD0, MD1
Output Voltage: RXD
I/OV
0
7
V
CC
V
I
0
7
V
V
O
–0.5
7
V
Recommended Operating Conditions
Parameter
Symbol
Min.
–20
2.7
Max.
70
Units
Conditions
Operating Temperature
Supply Voltage
T
°C
V
A
V
CC
5.5
Input/Output Voltage
I/OV
1.8
5.5
V
CC
Logic Input Voltage Logic High
V
V
2/3 IOV
0
IOV
CC
V
IH
CC
for TXD, MD0,
Logic Low
1/3 IOV
V
IL
CC
MD1,MIR_SEL
Receiver Input
Irradiance
2
2
[1]
Logic High EI
0.0036
0.0090
500
500
mW/cm
mW/cm
For in-band signals ≤ 115.2 kb/s
H
L
0.576 Mb/s ≤ in-band signals
[1]
≤ 1.152 Mb/s
2
Logic Low
EI
0.3
µW/cm
For in-band signals
LED (Logic High) Current
Pulse Amplitude
I
400
600
mA
V
= V = 3.0, V (TXD) ≥ V
LEDA
LED CC I IH
MD0 = 0, MD1 = 0
Receiver Data Rate
Ambient Light
0.0024
1.152
Mb/s
See IrDA Serial Infrared Physical
Layer Link Specification,
Appendix A for ambient levels
4
Electrical & Optical Specifications
Specifications (Min. and Max. values) hold over the recommended operating conditions unless otherwise noted.
Unspecified test conditions may be within the operating range. All typical values (Typ.) are at 25°C with V and IOV
CC
CC
set to 3.0 V unless otherwise noted.
Parameter
Receiver
Symbol
Min.
Typ.
Max.
Units
Conditions
Viewing Angle
2φ
1/2
30
°
Peak Sensitivity
Wavelength
λ
880
nm
p
RXD Output Voltage
Logic High
2
V
V
IOV –0.2
IOV
0.4
7.5
750
100
50
V
I
I
= –200 µA, EI ≤ 0.3 µW/cm
= 200 µA
OH
CC
CC
OH
OL
Logic Low
0
1
V
OL
[2]
RXD Pulse Width (SIR)
t
t
(SIR)
µs
ns
ns
µs
µs
θ
θ
≤ 15°, C = 9 pF
L
RPW
RPW
1/2
1/2
[3]
RXD Pulse Width (MIR)
(MIR) 200
≤ 15°, C = 9 pF
L
RXD Rise and Fall Times
t , t
r
25
25
18
C = 9 pF
f
L
[4]
Receiver Latency Time
Receiver Wake Up Time
Transmitter
t
t
L
[5]
2
100
EI = 10 mW/cm
RW
Radiant Intensity
IE
100
30
220
mW/sr
I
= 400 mA, θ ≤ 15°,
LEDA 1/2
H
TXD ≥ V . MD0 = 0, MD1 = 0,
T = 25°C
IH
A
Viewing Angle
2θ
60
°
1/2
Peak Wavelength
λ
875
35
nm
nm
p
Spectral Line Half Width
∆λ
1/2
TXD Logic Levels
High
V
V
2/3 IOV
IOV
CC
V
V
IH
CC
Low
0
1/3 IOV
IL
CC
TXD Input Current
High
I
I
0.02
1
1
µA
µA
V ≥ V
I IH
H
Low
–1
–0.02
0 ≤ V ≤ V
L
I
IL
LED Current
Off
I
0.03
1
µA
V
= V = 3.0 V, V (TXD) ≤ V
VLED
VLED CC I IL
MD0 = 0, MD1 = 0
[6]
Wakeup Time
t
t
30
25
100
50
µs
µs
TW
Maximum Optical
PW(Max)
[7]
Pulse Width
TXD Rise and
t , t
r
40
ns
t
(TXD) = 217 ns at 1.152 Mb/s
f
PW
Fall Time (Optical)
TXD Pulse Width (SIR)
TXD Pulse Width (MIR)
t
t
(SIR) 1.5
(MIR) 148
1.6
1.8
µs
t
t
(TXD) = 1.6 µs at 115.2 kb/s
TPW
TPW
PW
PW
217
260
ns
(TXD) = 217 ns at 1.152 Mb/s
5
Transceiver
MD0, MD1, MIR_SEL
Input Current
High
I
I
I
0.01
-0.02
0.01
1
1
1
µA
µA
µA
V ≥ V , V = IOV = 5
I IH CC CC
H
Low
–1
0 ≤ V ≤ V , V = IOV = 5
I IL CC CC
L
Supply Current
Shutdown
V
SD
V
CC
≥ IOV – 0.5, T = 25°C,
CC A
= 5.0 V
CC1
Idle
I
I
290
2
400
8
µA
V (TXD) ≤ V , EI = 0
CC2
CC3
I
IL
Active
mA
V (TXD) ≤ V
I
IL
Notes:
1. An in-band optical signal is a pulse/sequence where the peak wavelength, λp, is defined as 850 nm ≤ λp ≤ 900 nm, and the pulse characteristics
are compliant with the IrDA Serial Infrared Physical Layer Link Specification.
2
2
2. For in-band signals 2.41 kbps to 115.2 kbps where 3.6 µW/cm ≤ EI ≤ 500 mW/cm .
2
2
3. For in-band signals 0.576 Mbps to 1.152 Mbps where 9 µW/cm ≤ EI ≤ 500 mW/cm .
4. Latency is defined as the time from the last TXD light output pulse until the receiver has recovered its full sensitivity.
5. Receiver wake up time is measured from the MD0 pin high to low transition or MD1 pin low to high transition or V power on to valid RXD output.
CC
6. Transmitter wake up time is measured from the MD0 pin high to low transition or MD1 pin low to high transition or V power on to valid light
CC
output in response to a TXD pulse.
7. Maximum optical pulse width is defined as the maximum time that the LED will remain on. This is to prevent the long LED turn on time.
6
HSDL-3310 Package Outline with Dimensions and Recommended PC Board Layout
SOLDERING PATTERN
0.5
4.9
MOUNTING
CENTER
MOUNTING
GROUNDED
CENTER
WHOLLY
1.01
1.15
0.8
1.9
2.6
1.9
1.8
1
1
0.7
9.8
2.93
LIGHT RECEIVING
P1.0x3 = 3
P1.0x3 = 3
2.7
CENTER
EMITTING
CENTER
3.7
4
1.925
0.45
0.37
9
8
7
6
5
4
3
4
2
1
0.83
0.7
R1.77
4.44
R2
P1.0 x 8 = 8.0
1.4
2.3
4.94
1
2
3
4
5
GND
IOV
6
7
8
9
MD1
RXD
TXD
0.7
CC
V
CC
VLED
MIR
0.25
MD0
UNIT: mm
TOLERANCE: ± 0.2
HSDL-3310 Ordering Information
Part Number
Package
Standard Package Increment
HSDL-3310#007
HSDL-3310#017
Front View
Front View
400
10
7
+1
–0.5
HSDL-3310 Reel Dimension and Shape
17.5
1.6 ± 0.5
2.0 ± 0.5
13.0 ± 0.5
21.0 ± 0.8
80 ± 2
180
R 1.0
LABEL PASTED HERE
HSDL-3310 Tape and Carrier Dimensions
0.73 ± 0.1
1.75 ± 0.1
+0.1
–0
4 ± 0.1
1.6
7.5 ± 0.1
GND
16 ± 0.3
10.2 ± 0.1
VLEDA
POLARITY
0.4 ± 0.05
4.4 ± 0.1
5.24 ± 0.1
8.0 ± 0.1
DIRECTION
OF PULLING OUT
HSDL-3310 Tape Configuration
EMPTY
PARTS MOUNTED
LEADER
(40 mm MIN.)
(400 mm MIN.)
EMPTY
(40 mm MIN.)
DIRECTION
OF PULLING OUT
8
Reflow Profile
MAX. 245°C
R3 R4
230
200
183
170
R2
150
90 sec.
MAX.
ABOVE
183°C
125
100
R1
R5
50
25
0
50
100
150
200
250
300
t-TIME (SECONDS)
P1
HEAT
UP
P2
SOLDER PASTE DRY
P3
SOLDER
REFLOW
P4
COOL
DOWN
Process Zone
Symbol
P1, R1
P2, R2
P3, R3
P3, R4
P4, R5
∆T
Maximum ∆T/∆time
4°C/s
Heat Up
25°C to 125°C
125°C to 170°C
Solder Paste Dry
Solder Reflow
0.5°C/s
170°C to 230°C (245°C max.)
230°C to 170°C
4°C/s
-4°C/s
Cool Down
170°C to 25°C
-3°C/s
The reflow profile is a straight
second to allow for even heating
of both the PC board and
HSDL-3310 castellation I/O pins.
of 90 seconds, the intermetallic
growth within the solder connec-
tions becomes excessive, result-
ing in the formation of weak and
unreliable connections. The
temperature is then rapidly
reduced to a point below the soli-
dus temperature of the solder,
usually 170°C (338°F), to allow
the solder within the connections
to freeze solid.
line representation of a nominal
temperature profile for a convec-
tive reflow solder process. The
temperature profile is divided into Process zone P2 should be of
four process zones, each with
different ∆T/∆time temperature
change rates. The ∆T/∆time rates
are detailed in the above table.
sufficient time duration (> 60
seconds) to dry the solder paste.
The temperature is raised to a
level just below the liquidus point
The temperatures are measured at of the solder, usually 170°C
the component to printed-circuit
board connections. We recom-
mend using convection (forced-
medium) reflow instead of IR
reflow to eliminate the possibility
of delamination damage and
shadow effects.
(338°F).
Process zone P3 is the solder
reflow zone. In zone P3, the
Process zone P4 is the cool
down after solder freeze. The
cool down rate, R5, from the
liquidus point of the solder to
25°C (77°F) should not exceed
–3°C per second maximum. This
limitation is necessary to allow
the PC board and HSDL-3310
castellation I/O pins to change
dimensions evenly, putting mini-
mal stresses on the HSDL-3310
transceiver.
temperature is quickly raised
above the liquidus point of solder
to 230°C (446°F) for optimum
results. The dwell time above the
liquidus point of solder should be
between 15 and 90 seconds. It
usually takes about 15 seconds to
assure proper coalescing of the
solder balls into liquid solder and
the formation of good solder
connections. Beyond a dwell time
In process zone P1, the PC
board and HSDL-3310
castellation I/O pins are heated to
a temperature of 125°C to
activate the flux in the solder
paste. The temperature ramp up
rate, R1, is limited to 4°C per
9
PCB Layout Suggestion
The following PCB layout shows a
recommended layout that should
result in good electrical and EMI
performance. Things to note:
A reference layout of a 2-layer
Agilent evaluation board for HSDL-
3310 based on the guidelines
stated above is shown below. For
more details, please refer to
1. In case a separate ground
plane is available in a multi-
layer board, the ground plane
should be continuous under
the part, but should not extend
under the trace.
Agilent Application Note 1114,
Infrared Transceiver PC Board
Layout for Noise Immunity, or to
design guidelines in Agilent IrDA
Data Link Design Guide.
2. The shield trace is a wide, low
inductance trace back to the
system ground.
3. The AGND pin is connected to
the ground plane and not to
the shield tab.
4. C1 is an optional V filter
CC
capacitor. It may be left out if
the V is clean.
CC
5. V
can be connected to
LED
either unfiltered or unregu-
lated power. If C1 is used, and
if V
uses the same supply
LED
as V , the connection should
CC
be made such that V
is
LED
filtered by C1 as well.
27.1 mm
GND
UL
CX3
GND
GND
2
1
2
2
1
GND
2
1
1
Cx1
Cx2
1
GND
2
Cx4
1
3
5
7
9
11
2
4
6
8
10 12
7.60001 mm
17 mm
5.08
mm
TOP LAYER
BOTTOM LAYER
10
1.0 Solder Pad, Mask, and Metal Solder Stencil Aperture
METAL STENCIL
FOR SOLDER PASTE
PRINTING
STENCIL
APERTURE
LAND PATTERN
SOLDER
MASK
PCBA
Figure 1. Stencil and PCBA.
1.1 Recommended Land Pattern for HSDL-3310
SHIELD SOLDER PAD
Rx LENS
DIM.
mm
2.40
0.65
1.00
1.80
1.70
3.71
3.66
INCHES
0.095
0.026
0.039
0.071
0.067
0.146
0.144
a
Tx LENS
e
b
c (PITCH)
d
e
f
d
g
b
g
Y
f
a
X
theta
c
9x PAD
FIDUCIAL
FIDUCIAL
Figure 2. Top view of land pattern.
11
1.2 Adjacent Land Keepout and Solder Mask Areas
Dim.
mm
Inches
min. 0.008
0.425
h
j
min. 0.2
10.8
4.7
k
l
0.185
3.2
0.126
j
• Adjacent land keep-out is the
maximum space occupied by
the unit relative to the land
pattern. There should be no
other SMD components within
this area.
Tx LENS
Rx LENS
SOLDER
MASK
k
LAND
h
Y
• “h” is the minimum solder
resist strip width required to
avoid solder bridging adjacent
pads.
X
• It is recommended that 2
fiducial cross be place at
mid-length of the pads for unit
alignment.
l
Note: Wet/Liquid Photo-
Imageable solder resist/mask is
recommended.
Figure 3. PCBA – Adjacent land keep-out and solder mask.
2.0 Recommended Solder Paste/
Cream Volume for Castellation
Joints
Based on the evaluation for
HDSL-3600, the printed solder
paste volume required per
castellation pad is 0.30 cubic mm
(based on either no-clean or
aqueous solder cream types with
typically 60 to 65% solid content
by volume).
12
2.1 Recommended Metal Solder
Stencil Aperture
It is recommended that only
0.152 mm (0.006 inch) or
0.127 mm (0.005 inch) thick
stencil be used for solder paste
printing. This is to ensure
adequate printed solder paste
volume and no shorting. The
following combination of metal
stencil aperture and metal stencil
thickness should be used:
See Figure 4.0
t, Nominal Stencil Thickness
l, Length of Aperture
mm
mm
inches
0.006
inches
0.152
0.127
3.0 ± 0.05
0.12 ± 0.002
0.15 ± 0.002
0.005
3.7 ± 0.05
w, the width of aperture is fixed at 0.65 mm (0.026 inch)
Aperture opening for shield pad is 1.8 mm x 1.8 mm as per land dimension.
APERTURE AS PER
LAND DIMENSIONS
t (STENCIL THICKNESS)
SOLDER
PASTE
w
l
Figure 4. Solder paste stencil aperture.
13
Moisture-Proof Packaging
The HSDL-3310 is shipped in
moisture-proof packaging. Once
opened, moisture absorption
begins.
Recommended Stortage Conditions
Storage Temperature
10°C to 30°C
Relative Humidity
Below 60% RH
Time from Unsealing to Soldering
After removal from the bag, the
parts should be soldered within
two days if stored at the recom-
mended storage conditions. If the
parts have been removed from
the bag for more than two days,
the parts must be stored in a dry
box.
Baking
If the parts are not stored in a dry
environment, they must be baked
before reflow process to prevent
damage to parts. Baking should
be done only once.
Packaging
Baking Temperature
Baking Time
≥ 48 hours
≥ 4 hours
≥ 2 hours
≥ 1 hour
In Reel
10°C
100°C
125°C
150°C
In Bulk
14
Optical Port Dimensions for
HSDL-3310
without vignetting. The maximum
dimensions minimize the effects
of stray light. The minimum size
corresponds to a cone angle of
30° and the maximum size corre-
sponds to a cone angle of 60°.
To ensure IrDA compliance, some
constraints on the height and
width of the window exist. The
minimum dimensions ensure that
the IrDA cone angles are met
IR TRANSPARENT WINDOW
OPAQUE MATERIAL
Y
X
K
IR TRANSPARENT WINDOW
OPAQUE MATERIAL
Z
A
D
distance of the module from the
back of the window (Z). If they
are comparable, Z' replaces Z in
the above equation. Z' is defined
as
In the figure above, X is the width
of the window, Y is the height of
the window, and Z is the distance
from the HSDL-3310 to the back
of the window. The distance from
the center of the LED lens to the
center of the photodiode lens, K,
is 5.63 mm. The equations for
computing the window dimensions
are as follows:
The depth of the LED image
inside the HSDL-3310, D, is
8 mm. ‘A’ is the required half
angle for viewing. For IrDA com-
pliance, the minimum is 15° and
the maximum is 30°. These equa-
tions result in the following tables
and graphs:
Z' = Z + t/n
where ‘t’ is the thickness of the
window and ‘n’ is the refractive
index of the window material.
X = K + 2*(Z + D)*tanA
Y = 2*(Z + D)*tanA
The above equations assume that
the thickness of the window is
negligible compared to the
15
Module Depth
(Z) mm
Aperture Width (X) mm
Aperture Height (Y) mm
Max.
Min.
Max.
Min.
0
1
2
3
4
5
6
7
8
9
14.8676
16.0223
17.17701
18.33171
19.48641
20.64111
21.79581
22.95051
24.10521
25.25991
9.917187
10.45309
10.98898
11.52488
12.06078
12.59668
13.13258
13.66848
14.20437
14.74027
9.237604
10.3923
11.54701
12.70171
13.85641
15.01111
16.16581
17.32051
18.47521
19.62991
4.287187
4.823085
5.358984
5.894882
6.430781
6.966679
7.502577
8.038476
8.574374
9.110273
30
25
20
15
10
25
20
15
10
5
0
X MAX.
X MIN.
5
0
Y MAX.
Y MIN.
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
MODULE DEPTH (Z) – mm
MODULE DEPTH (Z) – mm
Aperture width (X) vs. module depth.
Aperture height (Y) vs. module depth.
16
Window Material
If the window must be curved for
mechanical or industrial design
reasons, place the same curve on
the back side of the window that
has an identical radius as the
front side. While this will not
completely eliminate the lens
effect of the front curved surface,
it will significantly reduce the
effects. The amount of change in
the radiation pattern is dependent
upon the material chosen for the
window, the radius of the front
and back curves, and the distance
from the back surface to the
transceiver. Once these items are
known, a lens design can be
made which will eliminate the
effect of the front surface curve.
Almost any plastic material will
work as a window material. Poly-
carbonate is recommended. The
surface finish of the plastic should
be smooth, without any texture.
An IR filter dye may be used in the
window to make it look black to
the eye, but the total optical loss
of the window should be 10 per-
cent or less for best optical
The following drawings show the
effects of a curved window on the
radiation pattern. In all cases, the
center thickness of the window is
1.5 mm, the window is made of
polycarbonate plastic, and the
distance from the transceiver to
the back of the window is 3 mm.
performance. Light loss should be
measured at 875 nm.
Shape of the Window
From an optics standpoint, the
window should be flat. This en-
sures that the window will not
alter either the radiation pattern
of the LED, or the receive pattern
of the photodiode.
Flat Window
Curved Front and Back
Curved Front, Flat Back
(First Choice)
(Second Choice)
(Do Not Use)
17
www.semiconductor.agilent.com
Data subject to change.
Copyright © 2001 Agilent Technologies, Inc.
April 4, 2001
5988-0129EN
相关型号：
HSDL-3600017
SPECIALTY INTERFACE CIRCUIT, SMA10, 12.2 X 5.1 MM, 4 MM HEIGHT, LOW PROFILE, MODULE-10
AGILENT
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