HSDL-3220-001 [AGILENT]
IrDA㈢ Data Compliant Low Power 4.0 Mbit/s Infrared Transceiver; IrDA㈢数据标准低功率4.0 Mbit / s的红外收发器
| 型号： | HSDL-3220-001 |
| 厂家： | 
AGILENT TECHNOLOGIES, LTD. |
| 描述： | IrDA㈢ Data Compliant Low Power 4.0 Mbit/s Infrared Transceiver |
| 文件： | 总19页 (文件大小：188K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Agilent HSDL-3220 IrDA®
Data Compliant Low Power
4.0 Mbit/s Infrared Transceiver
Data Sheet
Features
•
Fully compliant to IrDA 1.4 physical
layer low power specification from
9.6 kbit/s to 4.0 Mbit/s (FIR)
• Miniature package
– Height: 2.5 mm
– Width: 8.0 mm
– Depth: 3.0 mm
• Typical link distance > 50 cm
•
Guaranteed temperature performance,
-25o to 70oC
Description
The HSDL-3220 is a new
generation low profile high speed completely to achieve very low
•
Critical parameters are guaranteed over
temperature and supply voltage
The HSDL-3220 can be shutdown
• Low power consumption
Low shutdown current
– Complete shutdown of TXD, RXD,
and PIN diode
infrared transceiver module that
provides interface between logic
and IR signals for through-air,
serial, half-duplex IR data-link.
The module is fully compliant to
power consumption. In the
–
shutdown mode, the PIN diode
will be inactive and thus produc-
ing very little photocurrent even
under very bright ambient light.
• Excellent EMI performance
• Vcc supply 2.7 to 3.6 Volts
IrDA Physical Layer specification It is also designed to interface to
version 1.4 low power from
9.6kbit/s to 4.0 Mbit/s (FIR) and
is IEC825-Class 1 Eye Safe.
input/output logic circuits as low
as 1.8V. These features are ideal
for mobile devices that require
low power consumption.
• Interfacing with I/O logic circuits as
low as 1.8 V
• Lead-free package
• LED stuck-high protection
• Designed to accommodate light loss
with cosmetic windows
V
CX2
CX1
CC
CX4
• IEC 825-class 1 eye safe
• Lead-free and RoHS Compliant
V
(6)
GND (8)
CC
IOV (7)
CC
HSDL-3220
Applications
• Mobile telecom
– Mobile phones
– Smart phones
– Pagers
SD (5)
RXD (4)
• Data communication
– Pocket PC handheld products
– Personal digital assistants
– Portable printers
TXD (3)
LED C (2)
LED A (1)
TRANSMITTER
R1
• Digital imaging
V
led
– Digital cameras
CX3
– Photo-imaging printers
• Electronic wallet
Figure 1. Functional block diagram of HSDL-3220.
• Small industrial & medical
instrumentation
– General data collection devices
– Patient & pharmaceutical data
collection devices
8
7
6
5
4
3
2
1
Figure 2. Rear view diagram with pinout.
Application Support Information
The Application Engineering
Group is available to assist you
with the application design
associated with the HSDL-3220
infrared transceiver module. You
can contact them through your
local sales representatives for
additional details.
Marking Information
The unit is marked with the
letter “G” and “YWWLL” on the
shield where:
Y is the last digit of the year
WW is the work week
LL is the lot information
Order Information
Part Number
Packaging Type
Package
Quantity
HSDL-3220-021
HSDL-3220-001
Tape and Reel
Tape and Reel
Front View
Front View
2500
500
I/O Pins Configuration Table
Pin
Symbol
Description
I/O Type
Notes
1
2
3
4
5
6
7
8
-
LED A
LED C
TXD
LED Anode
I
1
2
3
4
5
6
7
8
9
LED Cathode
Transmit Data. Active High.
Receive Data. Active Low.
Shutdown. Active High.
Supply Voltage
I
RXD
O
I
SD
Vcc
IOVcc
GND
Shield
Input/Output ASIC Vcc
Ground
EMI Shield
Recommended Application Circuit Components
Component
Recommended Value
Notes
R1
5.6Ω 5%, 0.25 watt for 2.7 ≤Vled < 3.3V
10Ω 5%, 0.25 watt for 3.3 ≤Vled<4.2V
15Ω 5%, 0.25 watt for 4.2 ≤Vled < 5.5V
CX1, CX4
CX2, CX3
Notes:
0.47 µF 20%, X7R Ceramic
6.8 µF 20%, Tantalum
10
11
1. Tied through external series resistor, R1, to regulated Vled from 2.7 to 5.5V. Please refer to table
above for recommended series resistor value.
2. Internally connected to LED driver. Leave this pin unconnected.
3. This pin is used to transmit serial data when SD pin is low. If this pin is held high for longer than
50 µs, the LED is turned off. Do NOT float this pin.
4. This pin is capable of driving a standard CMOS or TTL load. No external pull-up or pull-down
resistor is required. The pin is in tri-state when the transceiver is in shutdown mode. The receiver
output echoes transmitted signal.
5. The transceiver is in shutdown mode if this pin is high for more than 400 µs. On falling edge of
this signal, the state of the TXD pin sampled and used to set receiver low bandwidth (TXD=low)
or high bandwidth (TXD=high) mode. Refer to the section ”Bandwidth selection timing” for
programming information. Do NOT float this pin.
6. Regulated, 2.7 to 3.6 Volts.
7. Connect to ASIC logic controller Vcc voltage or supply voltage. The voltage at this pin must be
equal to or less than supply voltage.
8. Connect to system ground.
9. Connect to system ground via a low inductance trace. For best performance, do not connect
directly to the transceiver pin GND.
10. CX1 must be placed within 0.7 cm of the HSDL-3220 to obtain optimum noise immunity.
11. In environments with noisy power supplies, including CX2, as shown in Figure 1, can enhance
supply ripple rejection performance.
2
Bandwidth Selection Timing
The transceiver is in default SIR/
MIR mode when powered on.
User needs to apply the following
programming sequence to both
the SD and TXD inputs to enable
the transceiver to operate at FIR
mode.
V
IH
V
IH
SD/MODE
50%
SD/MODE
50%
V
IL
V
IL
t
t
H
S
t
t
H
S
V
IH
TXD
50%
50%
TXD
50%
50%
V
V
IL
IL
Figure 3. Bandwidth selection timing at SIR/MIR mode.
Figure 4. Bandwidth selection timing at FIR mode.
Setting the transceiver to SIR/MIR
Mode (9.6 kbit/s to 1.152 Mbit/s)
4. Ensure that TXD input re-
mains low for tH ≥ 100 ns, the
receiver is now in SIR/MIR
mode
2. After SD/Mode input remains
HIGH at > 25 ns, set TXD input
to logic HIGH, wait tS ≥ 25 ns
(from 50% of TXD rising edge
till 50% of SD falling edge)
1. Set SD/Mode input to logic
HIGH
5. SD input pulse width for mode
selection should be > 50 ns.
2. TXD input should remain at
logic LOW
3. Then set SD/Mode to logic
LOW, the HIGH to LOW
negative edge transition will
determine the receiver band-
width
3. After waiting for tS ≥ 25 ns, set
SD/Mode to logic LOW, the
HIGH to LOW negative edge
transition will determine the
receiver bandwidth
Setting the transceiver to FIR
(4.0 Mbit/s) Mode
1. Set SD/Mode input to logic
HIGH
4. After waiting for tH ≥ 100 ns,
set the TXD input to logic LOW
5. SD input pulse width mode
selection should be > 50 ns.
Transceiver I/O Truth Table
Inputs
Outputs
TXD
Light Input to Receiver
SD
LED
RXD
Note
High
Don’t Care
High
Low
Low
Low
High
On
Off
Off
Off
Not Valid
Low
Low
12,13
Low
Low
High
Don’t Care
Notes:
Don’t Care
High
12. In-band IrDA signals and data rates ≤ 4.0 Mbit/s
13. RXD logic low is a pulsed response. The condition is maintained for a duration dependent on pattern and strength of the incident intensity.
3
CAUTIONS: The BiCMOS inherent to the design of this component increases the component’s
susceptibility to damage from electrostatic discharge (ESD). It is advised that normal static precautions
be taken in handling and assembly of this component to prevent damage and/or degradation which may
be induced by ESD.
Absolute Maximum Ratings
For implementations where case to ambient thermal resistance is ≤50°C/W.
Parameter
Symbol
Min.
Max.
Units
Conditions
Storage Temperature
Operating Temperature
LED Anode Voltage
TS
-40
-25
0
+100
+70
6.5
°C
°C
V
TA
VLEDA
VCC
VI
Supply Voltage
0
6.5
V
Input Voltage: TXD, SD/Mode
Output Voltage: RXD
DC LED Transmit Current
Average Transmit Current
0
6.5
V
VO
0
6.5
V
ILED (DC)
50
mA
mA
I
LED (PK)
200
≤90 µs pulse width
≤25% duty cycle
Recommended Operating Conditions
Parameter
Symbol
Min.
Typ.
Max.
Units
Conditions
Supply Voltage
VCC
2.7
3.6
V
V
V
V
Input/Output Voltage
IOVcc
VIH
1.8
Vcc
IOVcc
0.4
Logic High
Logic Low
IOVcc – 0.5
Logic Input Voltage
for TXD, SD/Mode
VIL
0
EIH, min
0.0081 mW/cm2
9.6kbit/s ≤ in-band signals
≤1.152 Mbit/s[14]
Logic High
Receiver Input Irradiance
0.020
500
mW/cm2
mW/cm2
1.152 Mbit/s < in-band signals
≤ 4.0 Mbit/s[14]
EIH, max
9.6 kbit/s ≤ in-band signals
≤ 4.0 Mbit/s[14]
Logic Low
EIL
0.3
µW/cm2
For in-band signals[14]
LED (Logic High) Current
Pulse Amplitude
ILEDA
150
mA
Receiver Data Rate
0.0096
4.0
Mbit/s
Note :
14. An in-band optical signal is a pulse/sequence where the peak wavelength, λp, is defined as 850 ≤ λp ≤ 900 nm, and the pulse characteristics are
compliant with the IrDA Serial Infrared Physical Layer Link Specification v1.4.
4
Electrical and Optical Specifications
Specifications (Min. and Max. values) hold over the recommended operating conditions unless otherwise noted.
Unspecified test conditions may be anywhere in their operating range. All typical values (Typ.) are at 25°C, Vcc set to 3.0V
and IOVcc set to 1.8V unless otherwise noted.
Parameter
Symbol
Min.
Typ.
Max.
Units
Conditions
Receiver
Viewing Angle
2θ
λp
30
°
Peak Sensitivity Wavelength
880
nm
V
Logic High VOH
Logic Low VOL
IOVCC – 0.2
IOVCC
0.4
IOH = -200 µA, EI ≤ 0.3 µW/cm2
IOL = 200 µA, EI ≥ 8.1 µW/cm2
θ ≤ 15°, CL = 9 pF
RXD Output Voltage
0
V
RXD Pulse Width (SIR)[15]
RXD Pulse Width (MIR)[16]
RXD Pulse Width (FIR) [16]
RXD Rise and Fall Times
Receiver Latency Time[17]
Receiver Wake Up Time[18]
Transmitter
tPW (SIR)
tPW(MIR)
tPW(FIR)
tr, tf
1
4.0
µs
ns
ns
ns
µs
µs
100
80
500
175
θ ≤ 15°, CL = 9 pF
θ ≤ 15°, CL = 9 pF
60
25
50
CL = 9 pF
tL
50
tW
100
Radiant Intensity
IEH
10
30
45
mW/sr
ILEDA= 150 mA, θ ≤ 15°, VTXD ≥ VIH,
VSD ≤ VIL, Ta=25°C
Viewing Angle
2θ
60
°
Peak Wavelength
Spectral Line Half Width
λp
875
35
nm
nm
µA
µA
mA
µs
ns
ns
µs
∆λ
High
Low
IH
10
10
VTXD ≥ VIH
TXD Input Current
IL
0 ≤ VTXD ≤ VIL
LED ON Current
ILEDA
tPW (SIR)
tPW(MIR)
tPW(FIR)
tPW(max.)
tr, tf
150
1.6
217
125
50
VTXD ≥ VIH, R1=5.6ohm, Vled=3.0V
tPW (TXD) = 1.6 µs at 115.2 kbit/s
tPW (TXD) = 217 ns at 1.152 Mbit/s
tPW(TXD)=125 ns at 4.0 Mbit/s
TXD Pulse Width (SIR)
TXD Pulse Width (MIR)
TXD Pulse Width (FIR)
1.5
1.8
148
115
260
135
100
Maximum Optical PW[19]
TXD Rise and fall Time (Optical)
600
40
ns
ns
tPW(TXD) = 1.4 µs at 115.2 kbit/s
tPW (TXD) = 125 ns at 4.0 Mbit/s
LED Anode On-State Voltage
VON(LEDA)
1.6
2.1
V
ILEDA=150 mA, VTXD≥VIH
Transceiver
Supply Current
Shutdown ICC1
Idle ICC2
0.1
1.8
1
µA
VSD ≥ VIH, Ta= 25°C
3.0
mA
VSD ≤ VIL, VTXD ≤ VIL, EI=0
Notes:
15. For in-band signals from 9.6 kbit/s to 115.2 kbit/s, where 9 µW/cm2 ≤ EI ≤ 500 mW/cm2.
16. For in-band signals from 0.576 Mbit/s to 4.0 Mbit/s, where 22.5 µW/cm2 ≤ EI ≤ 500 mW/cm2.
17. Latency time is defined as the time from the last TxD light output pulse until the receiver has recovered full sensitivity.
18. Receiver wake up time is measured from Vcc power on or SD pin high to low transition to a valid RXD output.
19. The maximum optical PW is the maximum time the LED remains on when the TXD is constantly high. This is to prevent long turn on time of the LED
for eye safety protection.
5
t
pw
t
pw
V
OH
LED ON
90%
50%
10%
90%
50%
10%
V
OL
LED OFF
t
t
r
f
t
t
f
r
Figure 5. RxD output waveform.
Figure 6. LED optical waveform.
SD
TXD
LED
RX
LIGHT
RXD
t
t
RW
pw (MAX.)
Figure 7. TxD “Stuck On” protection waveform.
Figure 8. Receiver wakeup time waveform.
120
100
80
60
40
20
0
2.4
2.2
2.0
1.8
1.6
1.4
0.10
0.15
0.20
0.25
0.30
0.35
0.10
0.15
0.20
0.25
0.30
0.35
ILEDA (A)
ILEDA (A)
Figure 9. Radiant Intensity vs ILEDA
.
Figure 10. VLEDA vs ILEDA.
6
HSDL-3220 Package Dimensions
2.0
0.8
0.4
7
HSDL-3220 Tape and Reel Dimensions
4.0 0.1
1.5 0.1
Unit: mm
1.75 0.1
7.5 0.1
Ø1.5+0.1
0
POLARITY
Pin 8: VLED
16.0 0.2
Pin 1: GND
8.4 0.1
0.4 0.05
3.4 0.1
2.8 0.1
8.0 0.1
Progressive Direction
Empty
Parts Mounted
Leader
(400 mm min)
(40 mm min)
Empty
(40 mm min)
Option # "B" "C" Quantity
001
178 60
500
021
330 80
2500
Unit: mm
Detail A
2.0 0.5
13.0 0.5
B
C
R1.0
LABEL
21 0.8
Detail A
16.4 +2
0
2.0 0.5
Note: The carrier tape is compliant to the packaging materials standards for ESD sensitive device, EIA-541
8
Moisture Proof Packaging
All HSDL-3220 options are
shipped in moisture proof
package. Once opened, moisture
absorption begins.
Baking Conditions
This part is compliant to JEDEC
Level 4.
If the parts are not stored in dry
conditions, they must be baked
before reflow to prevent damage
to the parts.
Package
Temp.
Time
In reels
In bulk
60°C
100°C
125°C
150°C
≥ 48 hours
≥ 4 hours
≥ 2 hours
≥ 1 hour
UNITS IN A SEALED
MOISTURE-PROOF
PACKAGE
Baking should only be done once.
PACKAGE IS
OPENED (UNSEALED)
Recommended Storage Conditions
Storage Temperature
Relative Humidity
10°C to 30°C
below 60% RH
ENVIRONMENT
LESS THAN 30°C,
AND LESS THAN
60% RH
Time from Unsealing to Soldering
After removal from the bag, the
parts should be soldered within
three days if stored at the recom-
mended storage conditions. If
times longer than three days are
needed, the parts must be stored
in a dry box.
YES
PACKAGE IS
OPENED LESS
THAN 72 HOURS
NO BAKING
YES
IS NECESSARY
NO
PERFORM RECOMMENDED
BAKING CONDITIONS
NO
Figure 11. Baking conditions chart.
9
Recommended Reflow Profile
MAX. 260°C
R3 R4
255
230
220
200
R2
180
60 sec.
MAX.
ABOVE
220°C
160
120
R1
R5
80
25
0
50
100
150
200
250
300
t-TIME (SECONDS)
P1
HEAT
UP
P2
P3
SOLDER
REFLOW
P4
COOL DOWN
SOLDER PASTE DRY
Process Zone
Symbol
∆T
Maximum ∆T/∆time
Heat Up
P1, R1
P2, R2
P3, R3
P3, R4
P4, R5
25°C to 160°C
160°C to 200°C
4°C/s
Solder Paste Dry
0.5°C/s
4°C/s
-6°C/s
-6°C/s
200°C to 255°C (260°C at 10 seconds max)
255°C to 200°C
Solder Reflow
Cool Down
200°C to 25°C
Process zone P2 should be of
sufficient time duration (60 to
120 seconds) to dry the solder
paste. The temperature is raised
to a level just below the liquidus
point of the solder, usually 200°C reduced to a point below the
(392°F).
growth within the solder connec-
tions becomes excessive, result-
ing in the formation of weak and
unreliable connections. The
The reflow profile is a straight-
line representation of a nominal
temperature profile for a convec-
tive reflow solder process. The
temperature profile is divided
into four process zones, each with
different ∆T/∆time temperature
change rates. The ∆T/∆time rates
are detailed in the above table.
The temperatures are measured
at the component to printed
temperature is then rapidly
solidus temperature of the
solder, usually 200°C (392°F), to
allow the solder within the
connections to freeze solid.
Process zone P3 is the solder
reflow zone. In zone P3, the
temperature is quickly raised
above the liquidus point of solder Process zone P4 is the cool down
circuit board connections.
to 255°C (491°F) for optimum
after solder freeze. The cool down
rate, R5, from the liquidus point
results. The dwell time above the
In process zone P1, the PC board
and HSDL-3220 castellation pins
are heated to a temperature of
160°C to activate the flux in the
solder paste. The temperature
ramp up rate, R1, is limited to
4°C per second to allow for even
heating of both the PC board and
HSDL-3220 castellations.
liquidus point of solder should be of the solder to 25°C (77°F)
between 20 and 60 seconds. It should not exceed 6°C per second
usually takes about 20 seconds to maximum. This limitation is
assure proper coalescing of the necessary to allow the PC board
solder balls into liquid solder and and HSDL-3220 castellations to
the formation of good solder change dimensions evenly,
connections. Beyond a dwell time putting minimal stresses on the
of 60 seconds, the intermetallic HSDL-3220 transceiver.
10
Appendix A: SMT Assembly Application Note
Solder Pad, Mask and Metal Stencil Aperture
STENCIL APERTURE
METAL STENCIL
FOR SOLDER PASTE
PRINTING
LAND PATTERN
SOLDER MASK
PCB
Figure 12. Stencil and PCBA.
Recommended Land Pattern
SHIELD
SOLDER PAD
C
L
1.35
MOUNTING
CENTER
1.25
2.05
0.10
0.775
1.75
FIDUCIAL
0.60
0.475
1.425
UNIT: mm
2.375
3.325
Figure 13. Stencil and PCBA.
11
Recommended Metal Solder
Stencil Aperture
APERTURES AS PER
LAND DIMENSIONS
It is recommended that only a
0.152 mm (0.006 inches) or a
0.127 mm (0.005 inches) thick
stencil be used for solder paste
printing. This is to ensure
adequate printed solder paste
volume and no shorting. See the
table below the drawing for
combinations of metal stencil
aperture and metal stencil
thickness that should be used.
t
w
l
Figure 14. Solder stencil aperature.
Aperture opening for shield pad
is 2.7 mm x 1.25 mm as per land
pattern.
Aperture size (mm)
Stencil thickness, t (mm)
length, l
width, w
0.152 mm
0.127 mm
2.60 0.05
3.00 0.05
0.55 0.05
0.55 0.05
10.1
Adjacent Land Keepout and
Solder Mask Areas
Adjacent land keep-out is the
maximum space occupied by the
unit relative to the land pattern.
There should be no other SMD
components within this area.
0.2
3.85
The minimum solder resist strip
width required to avoid solder
bridging adjacent pads is 0.2 mm.
It is recommended that two
fiducial crosses be place at mid-
length of the pads for unit
alignment.
SOLDER MASK
3.0
UNITS: mm
Note: Wet/Liquid Photo-
Imageable solder resist/mask is
recommended.
Figure 15. Adjacent land keepout and solder mask areas.
12
Appendix B: PCB Layout Suggestion
4. Preferably a multi-layered
board should be used to
module as Vcc, and sandwich
that layer between ground
connected board layers.
Refer to the diagram below for
an example of a 4 layer board.
The following PCB layout guide-
lines should be followed to obtain
a good PSRR and EM immunity
resulting in good electrical
provide sufficient ground
plane. Use the layer under-
neath and near the transceiver
performance. Things to note:
1. The ground plane should be
continuous under the part, but
should not extend under the
shield trace.
TOP LAYER
CONNECT THE METAL SHIELD AND MODULE
GROUND PIN TO BOTTOM GROUND LAYER.
2. The shield trace is a wide, low
inductance trace back to the
system ground. CX1, CX2,
CX3, and CX4 are optional
supply filter capacitors; they
may be left out if a clean
power supply is used.
LAYER 2
CRITICAL GROUND PLANE ZONE. DO NOT
CONNECT DIRECTLY TO THE MODULE
GROUND PIN.
LAYER 3
KEEP DATA BUS AWAY FROM CRITICAL
GROUND PLANE ZONE.
3. Vled can be connected to
either unfiltered or unregu-
lated power supply. If Vled
and Vcc share the same power
supply, CX3 need not be used
and the connections for CX1
and CX2 should be before the
current limiting resistor R1. In
a noisy environment, including
capacitor CX2 can enhance
supply rejection. CX1 is
BOTTOM LAYER (GND)
The area underneath the module
at the second layer, and 3 cm in
all directions around the module
is defined as the critical ground
plane zone. The ground plane
should be maximized in this
zone. Refer to application note
AN1114 or the Agilent IrDA Data
Link Design Guide for details.
The layout below is based on a
2-layer PCB.
generally a ceramic capacitor
of low inductance providing a
wide frequency response while
CX2 and CX3 are tantalum
capacitors of big volume and
fast frequency response. The
use of a tantalum capacitor is
more critical on the Vled line,
which carries a high current.
CX4 is an optional ceramic
capacitor, similar to CX1, for
the IOVcc line.
Figure 16. PCB layout suggestion.
13
Appendix C: General Application Guide for the HSDL-3220
modes. The design of the HSDL-
3220 also includes the following
unique features:
Interface to Recommended I/O chips
The HSDL-3220’s TXD data input
is buffered to allow for CMOS
drive levels. No peaking circuit or
capacitor is required. Data rate
from 9.6 kbit/s up to 4.0 Mbit/s is
available at the RXD pin.
Description
The HSDL-3220, a low-cost and
small form factor infrared trans-
ceiver, is designed to address the
mobile computing market such as
PDAs, as well as small-embedded
mobile products such as digital
cameras and cellular phones. It is
fully compliant to IrDA 1.4 low
power specification from
• Low passive component count.
• Shutdown mode for low power
consumption requirement.
• Interface to input/output logic
circuits as low as 1.8V
The block diagram below shows
how the IR port fits into a mobile
phone and PDA platform.
Selection of Resistor R1
9.6 kbit/s to 4.0 Mbit/s, and
supports HP-SIR and TV Remote
Resistor R1 should be selected to
provide the appropriate peak
pulse LED current over different
ranges of Vcc as shown in the
table below.
Minimum Peak Pulse
Recommended R1
Vcc
Intensity
LED Current
5.6Ω
3.0 V
45 mW/sr
150 mA
SPEAKER
AUDIO INTERFACE
DSP CORE
MICROPHONE
ASIC
CONTROLLER
RF INTERFACE
TRANSCEIVER
MOD/
DE-MODULATOR
IR
MICROCONTROLLER
USER INTERFACE
HSDL-3220
Figure 17. Mobile phone platform.
14
LCD
Panel
RAM
ROM
HSDL-3220
CPU for embedded
application
Touch
Panel
PCMCIA
Controller
RS232C
Driver
COM
Port
Figure 18. PDA platform.
The link distance testing was
done using typical HSDL-3220
units with SMC’s FDC37C669
and FDC37N769 Super I/O
controllers. An IR link distance
of up to 50 cm was demonstrated
for SIR and FIR speeds.
15
Appendix D: Window Designs for HSDL-3220
Optical port dimensions for
height of the window and Z is the comparable, Z' replaces Z in the
HSDL-3220
distance from the HSDL-3220 to
the back of the window. The
distance from the center of the
LED lens to the center of the
photodiode lens, K, is 5.1mm.
The equations for computing the
window dimensions are as
follows:
above equation. Z' is defined as
To ensure IrDA compliance, some
constraints on the height and
width of the window exist. The
minimum dimensions ensure
that the IrDA cone angles are met
without vignetting. The maxi-
mum dimensions minimize the
effects of stray light. The mini-
mum size corresponds to a cone
angle of 30° and the maximum
size corresponds to a cone angle
of 60°.
Z' = Z + t/n
where ‘t’ is the thickness of the
window and ‘n’ is the refractive
index of the window material.
The depth of the LED image
inside the HSDL-3220, D, is
3.17 mm. ‘A’ is the required half
angle for viewing. For IrDA
compliance, the minimum is 15°
and the maximum is 30°. Assum-
ing the thickness of the window
to be negligible, the equations
result in the following tables and
graphs.
X = K + 2 (Z+D) tanA
*
*
Y = 2 (Z+D) tanA
*
*
The above equations assume that
the thickness of the window is
negligible compared to the
distance of the module from the
back of the window (Z). If they are
In the figure below, X is the
width of the window, Y is the
OPAQUE
IR TRANSPARENT WINDOW
MATERIAL
Y
X
K
IR TRANSPARENT
WINDOW
OPAQUE
MATERIAL
Z
A
D
Figure 19. Window design diagram.
16
Module Depth
(z) mm
Aperture Width (x, mm)
Aperture Height (y, mm)
Max.
Min.
Max.
Min.
0
1
2
3
4
5
6
7
8
9
8.76
6.80
3.66
1.70
2.33
2.77
3.31
3.84
4.38
4.91
5.45
5.99
6.52
9.92
7.33
4.82
11.07
12.22
13.38
14.53
15.69
16.84
18.00
19.15
7.87
5.97
8.41
7.12
8.94
8.28
9.48
9.43
10.01
10.55
11.09
11.62
10.59
11.74
12.90
14.05
APERTURE WIDTH (X) vs. MODULE DEPTH
25
APERTURE HEIGHT (Y) vs. MODULE DEPTH
16
14
12
10
8
20
15
10
6
4
X MAX.
X MIN.
5
Y MAX.
Y MIN.
2
0
0
0
1
2
3
4
59
6
7
8
0
1
2
3
4
59 6
7
8
MODULE DEPTH (Z) – mm
MODULE DEPTH (Z) – mm
Figure 20. Aperture width (X) vs. module depth.
Figure 21. Aperture height (Y) vs. module depth.
17
Window Material
Shape of the Window
the radiation pattern is depen-
dent upon the material chosen
for the window, the radius of the
front and back curves, and the
distance from the back surface to
Almost any plastic material will
work as a window material.
Polycarbonate is recommended.
The surface finish of the plastic
should be smooth, without any
texture. An IR filter dye may be
used in the window to make it
look black to the eye, but the
total optical loss of the window
should be 10% or less for best
optical performance. Light loss
should be measured at 875 nm.
The recommended plastic
From an optics standpoint, the
window should be flat. This
ensures that the window will not
alter either the radiation pattern
of the LED, or the receive pattern the transceiver. Once these items
of the photodiode.
are known, a lens design can be
made which will eliminate the
If the window must be curved for effect of the front surface curve.
mechanical or industrial design
reasons, place the same curve on
the back side of the window that
has an identical radius as the
front side. While this will not
completely eliminate the lens
effect of the front curved surface, made of polycarbonate plastic,
it will significantly reduce the
effects. The amount of change in
The following drawings show the
effects of a curved window on the
radiation pattern. In all cases,
the center thickness of the
materials for use as a cosmetic
window are available from
General Electric Plastics.
window is 1.5 mm, the window is
and the distance from the
transceiver to the back surface of
the window is 3 mm.
Recommended Plastic Materials:
Material #
Light Transmission
Haze
Refractive Index
Lexan 141
88%
85%
85%
1%
1%
1%
1.586
1.586
1.586
Lexan 920A
Lexan 940A
Note: 920A and 940A are more flame retardant than 141.
Flat Window
(FirstChoice)
Curved Front and Back
(Second Choice)
Curved Front, Flat Back
(Do Not Use)
Figure 22. Shape of windows.
18
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Data subject to change.
Copyright © 2003-2005 Agilent Technologies, Inc.
Obsoletes 5989-3140EN
August 18, 2005
5989-3640EN
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