FCD4B14CCB_技术文档

Features

• Sensitive Layer Over a 0.8 µm CMOS Array

• Image Zone: 0.4 x 14 mm = 0.02" x 0.55"

• Image Array: 8 x 280 = 2240 pixels

• Pixel Pitch: 50 µm x 50 µm = 500 dpi

• Pixel Clock: up to 2 MHz Enabling up to 1780 Frames per Second

• Die Size: 1.7 x 17.3 mm

• Operating Voltage: 3V to 5.5V

• Naturally Protected Against ESD: > 16 kV Air Discharge

• Power Consumption: 20 mW at 3.3V, 1 MHz, 25°C

• Operating Temperature Range: 0°C to +70°C: C suffix

• Resistant to Abrasion: >1 Million Finger Sweeps

• Chip-On-Board (COB) package or 20-lead Ceramic DIP available for development, with

Specific Protective Layer

Thermal

Fingerprint

Sensor with

0.4 mm x 14 mm

(0.02" x 0.55")

Sensing Area

and

Applications

• PDA (Access Control, Data Protection)

• Cellular Phones, SmartPhone (Access e-business)

• Notebook, PC-add on (Access Control, e-business)

• PIN Code Replacement

• Automated Teller Machine, POS

• Building Access

• Electronic Keys (Cars, Home,...)

• Portable Fingerprint Imaging for Law Enforcement

• TV Access

Digital Output

(On-chip ADC)

Figure 1. Fingerchip Packages

Step for easy

integration

Chip-on-Board Package

(COB)

FCD4B14

Sensing area

FingerChip^™

Wire protection

(not drawn)

20-pin, 0.3" Dual-Inline

Ceramic Package

(DIP20)

Rev. 1962C–01/02

1

Table 1. Pin Description For DIP Ceramic Package

Pin Number

Name

GND

AVE

TPP

VCC

RST

OE

Type

1

2

GND

Analog output

Power

3

4

Power

5

Digital input

Digital output

GND

6

7

De0

De1

De2

De3

FPL

Do3

Do2

Do1

Do0

GND

ACKN

PCLK

TPE

AVO

8

9

10

11

12

13

14

15

16

17

18

19

20

Digital output

GND

Digital output

Digital input

Analog output

Die Attach is connected to pin 1 and 16, and must be grounded. FPL pin must be

grounded.

1

20

19

18

17

16

15

14

13

12

11

AVO

TPE

PCLK

ACKN

GND

Do0

GND

AVE

2

3

4

TPP

VCC

5

6

7

8

RST

OE

Do1

De0

De1

Do2

9

Do3

De2

De3

10

FPL

2

FCD4B14

1962C–01/02

FCD4B14

Table 2. Pin Description For Chip-On-Board Package

Pin Number

Name

GND

AVE

AVO

TPP

TPE

VCC

GND

RST

PCLK

OE

Type

1

2

GND

Analog output

Power

3

4

5

Digital input

Power

6

7

GND

8

Digital input

Digital output

GND

9

10

11

12

13

14

15

16

17

18

19

20

21

ACKN

De0

Do0

De1

Do1

De2

Do2

De3

Do3

FPL

GND

Die Attach is connected to pin 1, 7 and 21, and must be grounded. FPL pin must be

grounded.

GND

AVE

AVO

TPP

TPE

VCC

GND

RST

PCLK

OE

ACKN

De0

Do0

De1

Do1

De2

Do2

De3

Do3

FPL

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

GND

21

3

1962C–01/02

Description

FCD4B14 is part of the FingerChip Atmel monolithic fingerprint sensor family for which

no optics, no prism and no light source are required.

FCD4B14 is a single chip, high performance, low cost sensor based on temperature

physical effects for fingerprint sensing.

FCD4B14 has a linear shape, allowing for the capture of a fingerprint image by sweep-

ing the finger across the sensing area. After capturing several images, Atmel proprietary

software can reconstruct a full 8-bit fingerprint image, if needed.

FCD4B14 has a small surface combined with CMOS technology, and a Chip-On-Board

or ceramic dual-in-line package assembly. These facts contribute to a low-cost device.

FCD4B14 delivers a programmable number of images per second, while an integrated

Analog to Digital Converter delivers a digital signal adapted to interfaces such as an

EPP parallel port, USB microcontroller or directly to micro-processors. Thus, no frame

grabber or glue interface is necessary to send the frames. These facts make FCD4B14

an easy device to include in any system for identification or verification applications.

Table 3. Absolute Maximum Ratings⁽¹⁾

Parameter

Symbol

V_CC

Comments

Value

Unit

V

Positive supply voltage

Temperature stabilization power

Front plane

GND to 6.5

GND to V_CC

-50 to +85

TPP

V

FPL

V

Digital input voltage

RST PCLK

T_stg

V

Storage temperature

°C

Do not solder

DIP: socket mandatory

Lead temperature (soldering, 10 seconds.)

T_leads

Forbidden

°C

Note:

1. Absolute maximum ratings are limiting values, to be applied individually, while other parameters are within specified operat-

ing conditions. Long exposure to maximum ratings may affect device reliability.

Table 4. Recommended Conditions Of Use

Parameter

Symbol

V_CC

Comments

Min

Typ

5V

Max

Unit

V

Positive supply voltage

Front plane

3V

5.5V

FPL

Must be grounded

GND

V

Digital input voltage

Digital output voltage

Digital load

CMOS levels

V

C_L

50

pF

C_A

R_A

pF

Analog load

Not connected

kΩ

Operating temperature range

Maximum current on TPP

T_amb

Civil: “C” grade

0 to +70

°C

ITPP

0

100

mA

4

FCD4B14

1962C–01/02

FCD4B14

Table 5. Resistance

Parameter

Min Value

Standard Method

ESD

On pins. HBM (Human Body Model) CMOS I/O

2 kV

MIL-STD-883- method 3015.7

NF EN 6100-4-2

On die surface (Zapgun)

Air discharge

16 kV

MECHANICAL ABRASION

Number of cycles without lubricant multiply by a

factor of 20 for correlation with a real finger

200 000

4 hours

MIL E 12397B

CHEMICAL RESISTANCE

Cleaning agent, acid, grease, alcohol, diluted

acetone

Internal method

Table 6. Specifications

Explanation Of Test Levels

I

100% production tested at +25°C

II

100% production tested at +25°C, and sample tested at specified temperatures (AC testing done on sample)

Sample tested only

III

IV

V

VI

D

Parameter is guaranteed by design and/or characterization testing

Parameter is a typical value only

100% production tested at temperature extremes

100% probe tested on wafer at T_amb= +25°C

Parameter

Symbol

Test Level

Min

Typ

50

Max

Unit

micron

pixel

Resolution

IV

I

Size

8x280

Yield: number of bad pixels

Equivalent resistance on TPP pin

15

47

bad pixels

Ω

I

23

30

5

1962C–01/02

Table 7. 5V. Power supply = +5V; T_amb= 25°C; F_PCLK= 1 MHz; Duty cycle = 50%;

_load120 pF on digital outputs, analog outputs disconnected otherwise specified.

C

Parameter

Symbol

Test Level

Min

Typ

Max

Unit

Power Requirements

Positive supply voltage

V_CC

4.5

5

5.5

V

Digital positive supply current on V_CCpin

I

7

5

10

6

mA

C_load= 0

I_CC

IV

Power dissipation on V_CC

I

35

25

50

30

mW

C_load= 0

P_CC

IV

Current on V_CCin NAP mode

Analog Output

I_CCNAP

I

10

µA

Voltage range

V_AVx

0

2.9

V

Digital Inputs

Logic compatibility

Logic “0” voltage

Logic “1” voltage

Logic “0” current

Logic “1”current

CMOS

V_IL

V_IH

I_IL

I

0

3.6

-10

0

1.2

VCC

0

V

µA

I_IH

10

Digital Outputs

Logic compatibility

Logic “0” voltage⁽¹⁾

Logic “1” voltage⁽¹⁾

CMOS

V_OL

V_OH

I

1.5

V

3.5

Note:

1. With I_OL= 1 mA and I_OH= -1 mA

6

FCD4B14

1962C–01/02

FCD4B14

.

Table 8. 3.3V. Power supply = +3.3V; T_amb= 25°C; F_PCLK= 1 MHz; Duty cycle = 50%;

C

_load120 pF on digital outputs, analog outputs disconnected otherwise specified

Parameter

Symbol

Test Level

Min

Typ

Max

Unit

Power Requirements

Positive supply voltage

V_CC

I_CC

3.0

3.3

3.6

V

Digital positive supply current on V_CCpin

C_load= 0

I

6

5

10

6

mA

IV

Power dissipation on V_CC

C_load= 0

I

20

17

33

20

mW

P_CC

IV

Current on V_CCin NAP mode

Analog Output

I_CCNAP

I

10

µA

Voltage range

V_AVx

0

2.9

V

Digital Inputs

Logic compatibility

Logic “0” voltage

Logic “1” voltage

Logic “0” current

Logic “1”current

CMOS

V_IL

V_IH

I_IL

I

0

0.8

VCC

0

V

2.3

-10

0

µA

I_IH

10

Digital Outputs

Logic compatibility

Logic “0” voltage⁽¹⁾

Logic “1” voltage⁽¹⁾

CMOS

V_OL

V_OH

I

0.6

V

2.4

Note:

1. With I_OL= 1 mA and I_OH= -1 mA

7

1962C–01/02

.

Table 9. Switching Performances. T_amb= 25°C; F_PCLK= 1 MHz; Duty cycle = 50%;

C

_load120 pF on digital and analog outputs otherwise specified

Parameter

Symbol

f_PCLK

Test level

Min

0.5

Typ

Max

Unit

MHz

ns

Clock frequency

I

1

2

Clock pulse width (high)

Clock pulse width (low)

Clock setup time (high)/reset falling edge

No data change

t_HCLK

250

t_LCLK

I

ns

t_Setup

I

0

ns

t_NOOE

IV

100

ns

Table 10. 5.0V. All power supplies = +5 V

Parameter

Symbol

t_PLHACKN

t_PHLACKN

t_PDATA

Test level

Min

Typ

Max

85

Unit

ns

Output delay from PCLK to ACKN rising edge

Output delay from PCLK to ACKN falling edge

Output delay from PCLK to Data output Dxi

Output delay from PCLK to Analog output Avx

Output delay from OE to data high-Z

Output delay from OE to data output

I

80

ns

I

70

ns

t_PAVIDEO

t_DATAZ

I

170

ns

IV

25

29

ns

t_ZDATA

ns

Table 11. 3.3V. All power supplies = +3.3 V

Parameter

Symbol

t_PLHACKN

t_PHLACKN

t_PDATA

Test level

Min

Typ

Max

110

95

Unit

ns

Output delay from PCLK to ACKN rising edge

Output delay from PCLK to ACKN falling edge

Output delay from PCLK to Data output Dxi

Output delay from PCLK to Analog output AVx

Output delay from OE to data high-Z

Output delay from OE to data output

I

ns

I

85

ns

t_PAVIDEO

t_DATAZ

I

190

ns

IV

34

47

ns

t_ZDATA

ns

8

FCD4B14

1962C–01/02

FCD4B14

Figure 2. Reset

t

HRST

Reset RST

Clock PCLK

t

SETUP

Figure 3. Read One Byte/Two Pixels

F

PCLK

t

HCLK

LCLK

Clock

PCLK

Acknowledge

ACKN

t

PLHACK

PHLACKN

Data output

Data # N-1

Data # N

Data # N+1

t

PDATA

Do0-3, De0-3

Data #N+1

Data #N+2

Data #N

Video analog output

AVO, AVE

t

PAVIDEO

9

1962C–01/02

Figure 4. Output Enable

Output Enable

OE

t

DATAZ

ZDATA

Hi-Z

Data output

Do0-3, De0-3

Figure 5. No data change

t_NOOE

PCLK

OE

Note:

OE must not change during TNOOE after the PCLK falls. This is to ensure that the output drivers of the data is not driving cur-

rent, to reduce the noise level on the power supply.

10

FCD4B14

1962C–01/02

FCD4B14

Figure 6. FCD4B14 Block Diagram

clock

reset

ACKN

PCLK

RST

line sel

amp

column selection

even

odd

4

4-bit

ADC

De0-3

Do0-3

1 dummy column

1

8

8 lines of 280 columns of pixels

latches

2240

8

4-bit

ADC

chip

temperature

sensor

chip temperature

stabilization

output

enable

analog

output

TPP

TPE

AVE AVO

OE

Functional Description

The circuit is divided into two main sections: sensor and data conversion. One particular

column among 280+1 is selected in the sensor array (1), then each pixel of the selected

column sends its electrical information to amplifiers (2) (one per line), then two lines at a

time are selected (odd and even) so that two particular pixels send their information to

the input of two 4-bit Analog-to-Digital Converters (3), so 2 pixels can be read for each

clock pulse (4).

Figure 7. Functional Description

1

2

3

4

column selection

line sel

even

odd

4

4-bit

ADC

De0-3

Do0-3

8

8 lines of 280 columns of pixels

1 dummy column

amp

latches

8

4-bit

ADC

chip

temperature

sensor

Sensor

Each pixel is a sensor in itself. The sensor detects a temperature differential between

the beginning of acquisition and the reading of information: this is the integration time.

The integration time begins with a reset of the pixel to a predefined initial state. Note that

the integration time reset has nothing to do with the reset of the digital section.

Then, at a rate depending on the sensitivity of the pyroelectric layer, on the temperature

variation between the reset and the end of the integration time, and on the duration of

the integration time, electrical charges are generated at the pixel level.

11

1962C–01/02

Analog-to-Digital

Converter/

An Analog-to-Digital Converter (ADC) is used to convert the analog signal coming from

the pixel into digital data that can be used by a processor.

Reconstructing an 8-bit

Fingerprint Image

As the data rate for parallel port and USB is in the range of 1 MB per second and at least

a rate of 500 frames per second is needed to reconstruct the image with a fair sweeping

speed for the finger, two 4-bit ADCs have been used to output 2 pixels at a time on 1

byte.

Start Sequence

A reset is not necessary between each frame acquisition!

Start sequence must consist of:

1. Set the RST pin to high

2. Set the RST pin to low

3. Send 4 clock pulses (due to pipe-line)

4. Send clock pulses to skip the first frame

Note that the first frame never contains relevant information because the integration

time is not correct.

Figure 8. Start Sequence

Reset RST

4+1124 clock pulses to skip the first frame

Clock PCLK

1

2

3

4

1

1124

1

Reading the Frames

A frame consists of 280 true columns + 1 dummy column of 8 pixels. As two pixels are

output at a time, a system must send 281x4 = 1124 clock pulses to read one frame.

Reset must be low when reading the frames.

Read One Byte/Output

Enable

Clock is taken into account on the falling edge and data are output on the rising edge.

For each clock pulse, after the start sequence, a new byte is output on the Do0-3, De0-

3 pins. This byte contains 2 pixels: 4-bit on Do0-3 (odd pixels), 4-bit on De0-3 (even

pixels).

To output the data, the output enable (OE) pin must be low. When OE is high, the Do0-

3 and De0-3 pins are in high impedance state. This enables an easy connection to a

microprocessor bus without additional circuitry-it will enable data output by using a chip

select signal. Note that the FCD4B14 is always sending data: there is no data exchange

to perform using read/write mode.

Power Supply Noise

Video Output

IMPORTANT: When a falling edge is applied on OE (i.e when the Output Enable

becomes active), then some current is drained from the power supply to drive the 8 out-

puts, producing some noise. It is important to avoid such noise just after the falling edge

of the clock PCLK, when the pixels information is evaluated: the timing diagram figure 5

and time T_NOOEdefines the interval time where the power supply must be as quiet as

possible.

An analog signal is also available on pins AVE and AVO. Note that video output is avail-

able one clock pulse before the corresponding digital output (one clock pipe-line delay

for the analog to digital conversion).

12

FCD4B14

1962C–01/02

FCD4B14

Pixel Order

After a reset, pixel number one is located on the upper left corner, looking at the chip

with bond pads to the right. For each column of 8 pixels, pixels 1-3-5-7 are output on

odd data Do0-3 pins, pixels 2-4-6-8 are output on even data De0-3 pins. Most significant

bit is bit #3, least significant is bit #0.

Figure 9. Pixel Order

Pixel #2233 (280,1)

Pixel #1 (1,1)

Bond pads

Pixel #8 (1,8)

Pixel #2240 (280,8)

Synchronization: The

Dummy Column

A dummy column has been added to the sensor to act as a specific pattern to detect the

first pixel. So, 280 true columns + 1 dummy column are read for each frame.

The 4 bytes of the dummy column contain a fixed pattern on the two first bytes, and tem-

perature information on the last two bytes.

Dummy Byte

Odd

111X

rrrr

Even

0000

nnnn

pppp

Dummy Byte 1 DB1:

Dummy Byte 2 DB2:

Dummy Byte 3 DB3:

Dummy Byte 4 DB4:

tttt

Note:

x represents 0 or 1

The sequence 111X0000 111X0000 appears on every frame (exactly every 1124 clock

pulses), so it is an easy pattern to recognize for synchronization purposes.

13

1962C–01/02

Thermometer

The dummy bytes DB3 and DB4 contains some internal and temperature information.

The even nibble nnnn in DB3 can be used to measure an increase (or decrease) of the

chip temperature, using the difference between two measures of the same physical

device. The following table gives values in Kelvin.

nnnn

Temperature differential with code 8 in

Kelvin

Decimal

Binary

15

14

13

12

11

10

9

1111

1110

1101

1100

1011

1010

1001

1000

0111

0110

0101

0100

0011

0010

0001

0000

11.2

8.4

7

5.6

4.2

2.8

1.4

8

0

-1.4

-2.8

-4.2

-5.6

-7

7

6

5

4

3

2

-8.4

-11.2

< -16.8

1

0

For code 0 and 15, the absolute value is a minimum (saturation).

When the image contrast becomes low because of a low temperature difference

between the finger and the sensor, it is recommended to use the temperature stabiliza-

tion circuitry to increase the temperature of two codes (i.e. from 8 to 10), to get at least

an increase >1.4 Kelvin of the sensor. This enables to recover enough contrast to get a

proper fingeprint for recognition purpose.

14

FCD4B14

1962C–01/02

FCD4B14

Integration Time and

Clock Jitter

The FCD4B14 is not very sensitive to clock jitter (clock variation). The most important

requirement is a regular integration time that ensures the frame reading rate is also as

regular as possible, in order to get consistent fingerprint slices.

If the integration time is not regular, contrast will vary from one frame to another.

Note that it is possible to introduce some waiting time between each set of 1124 clock

pulses, but the overall time of one frame read must be regular. This waiting time is gen-

erally the time needed by the processor to perform some calculation over the frame (to

detect the finger, for instance).

Figure 10. Read One Frame

Reset RST is low

Column 1

3

Column 2

6

Column 280

Dummy Column 281

1

2

4

5

1119 1120 1121 1122 1123 1124

Clock PCLK

Pixels 1 & 2 3 & 4 5 & 6 7 & 8 1 & 2 3 & 4

7 & 8

DB1

DB2

DB3 DB4

Figure 11. Regular Integration Time

REGULAR INTEGRATION TIME

Frame n

Frame n+1

Frame n+2

Frame n+3

Clock PCLK

1124 pulses

15

1962C–01/02

Power Management

Nap Mode

Several strategies are possible to reduce power consumption when not in use.

The simplest and most efficient is to cut the power supply, using external means.

A nap mode is also implemented in the FCD4B14. To activate this nap mode, user must:

1. Set the reset RST pin to high. Doing this, all analog sections of the device are

internally powered down.

2. Set the clock PCLK pin to high (or low), thus stopping the entire digital section.

3. Set the TPE pin to low or disconnect TPP to stop the temperature stabilization

feature.

4. Set Output Enable OE pin to high, so that output are forced in HiZ.

Figure 12. Nap Mode

Nap mode

Reset RST

Nap

Clock PCLK

In Nap Mode, all internal transistors are in shut mode. Only leakage current is drained in

power supply, generally less than the tested value.

Static Current

Consumption

When the clock is stopped (set to 1) and the reset is low (set to 0), the analog sections

of the device drain some current and the digital section does not consume current if the

outputs are connected to a standard CMOS input (= no current is drained in the I/O). In

this case the typical current value is 5 mA. This current does not depend on the voltage

(i.e. it is almost the same from 3V to 5.5V).

Dynamic Current

Consumption

When the clock is running, the digital sections are consuming current, and particularly

the outputs if they are heavily loaded. In any case, it should be less than the testing

machine (120 pF load on each I/O), 50 pF maximum is recommended.

Connected to a USB interface chip (see application note 26 related to the FCDEMO4

kit) at 5V, and running at about 1 MHz, the FCD4B14 consumes less than 7 mA on VCC

pin.

Temperature

Stabilization Power

When the TPE pin is set to 1, current is drained via the TPP pin. The current is limited by

the internal equivalent resistance given in table 4 and a possible external resistor.

Consumption (TPP pin)

Most of the time, TPE is set to 0 and no current is drained in TPP. When the image con-

trast becomes low because of a low temperature differential (less than one Kelvin), then

it is recommended to set TPE to 1 during a short time so that the dissipated power in the

chip elevates the temperature, enabling to recover contrast. The necessary time to

increase the chip temperature of one Kelvin depends on the dissipated power, the ther-

mal capacity of the silicon sensor and the thermal resistance between the sensor and

the surroundings.

As a rule of thumb, dissipating 300 mW in the chip elevates the temperature of 1 Kelvin

in one second. With the 30 Ω typical value, 300 mW is 3V applied on TPP.

16

FCD4B14

1962C–01/02

FCD4B14

Packaging:

Mechanical Data

Figure 13. COB: Top View (all dimensions in mm)

0.2 A

+0.07

-0.01

17.51

at 0.4 height from B ref.

0.89 0.3

5.45 0.30

14

0.35

2.32 0.5

2.95 0.50

5.90 max

9.45 0.5*

+ 0.07

- 0.01

1.66

A

at 0.4 height from B ref.

0.83 0.50

5.20 max

0.2 min

26.6 0.25*

*: including burrs

Dam and Fill

B

1.5 max

0.790

max

0.2 max

Figure 14. COB: Bottom View (all dimensions in mm)

1 0.075

3.5 0.075

1.15 0.15

0.5 0.075

2.15 0.15

1.5 0.075

1

0.15

6.30 0.1

+0.08

(x3)

R0.75

2

0.075

0.15

-0.12

2

+0.33

-0.25

23.85 0.1

0.75

+0.15

(x3)

1.5

-0.23

17

1962C–01/02

Figure 15. DIL Package (all dimensions in mm)

0.08

60°

0.81 0.05

0.46 0.05

2.54 0.13

22.86 0.13

3.15 0.32

25.4 0.25

9.36 0.15 6.34 0.15

(2.45)

0.1 min

NO.11

NO.20

NO.10

NO.1

(0.20)

0.75 max

0.08

5.4 max

18

FCD4B14

1962C–01/02

FCD4B14

Ordering Information

Package Device

C

—

FC

D4B14

Atmel prefix

Quality level

FingerChip family

— : s tandard

Device type

Package

C: DIP Ceramic 20 pins

CB: Chip On Board (COB)

Temperature range

Com: 0° to +70°C

19

1962C–01/02

Atmel Headquarters

Atmel Operations

Corporate Headquarters

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San Jose, CA 95131

TEL 1(408) 441-0311

FAX 1(408) 487-2600

Memory

RF/Automotive

Atmel Corporate

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FAX 1(408) 436-4314

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Europe

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TEL (81) 3-3523-3551

FAX (81) 3-3523-7581

FAX 1(719) 540-1759

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e-mail

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Web Site

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Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty

which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors

which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does

not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted

by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical

components in life support devices or systems.

ATMEL^®is the registered trademarks of Atmel.

Other terms and product names may be the trademarks of others.

1962C–01/02/xM


型号：	FCD4B14CCB
厂家：	ATMEL
描述：	Thermal Fingerprint Sensor with 0.4 mm x 14 mm Sensing Area and Digital Output 热指纹传感器0.4毫米× 14毫米感光面积和数字输出传感器
文件：	总20页 (文件大小：255K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FCD4B14CCB [ATMEL]

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