ATXMEGA256A3B-AUR_技术文档

Features

• High-performance, Low-power AVR 8/16-bit XMEGA Microcontroller

• Non-volatile Program and Data Memories

– 64K - 256K Bytes of In-System Self-Programmable Flash

– 4K - 8K Boot Code Section with Independent Lock Bits

– 2K - 4K Bytes EEPROM

– 4K - 16K Bytes Internal SRAM

• Peripheral Features

– Four-channel DMA Controller with support for external requests

– Eight-channel Event System

8/16-bit

XMEGA A3

Microcontroller

– Seven 16-bit Timer/Counters

Four Timer/Counters with 4 Output Compare or Input Capture channels

Three Timer/Counters with 2 Output Compare or Input Capture channels

High Resolution Extensions on all Timer/Counters

Advanced Waveform Extension on one Timer/Counter

– Seven USARTs

IrDA Extension on 1 USART

ATxmega256A3

ATxmega192A3

ATxmega128A3

ATxmega64A3

– AES and DES Crypto Engine

– Two Two-wire Interfaces with dual address match(I²C and SMBus compatible)

– Three SPI (Serial Peripheral Interfaces)

– 16-bit Real Time Counter with Separate Oscillator

– Two Eight-channel, 12-bit, 2 Msps Analog to Digital Converters

– One Two-channel, 12-bit, 1 Msps Digital to Analog Converter

– Four Analog Comparators with Window compare function

– External Interrupts on all General Purpose I/O pins

– Programmable Watchdog Timer with Separate On-chip Ultra Low Power Oscillator

• Special Microcontroller Features

Preliminary

– Power-on Reset and Programmable Brown-out Detection

– Internal and External Clock Options with PLL

– Programmable Multi-level Interrupt Controller

– Sleep Modes: Idle, Power-down, Standby, Power-save, Extended Standby

– Advanced Programming, Test and Debugging Interfaces

JTAG (IEEE 1149.1 Compliant) Interface for test, debug and programming

PDI (Program and Debug Interface) for programming, test and debugging

• I/O and Packages

– 50 Programmable I/O Lines

– 64-lead TQFP

– 64-pad MLF

• Operating Voltage

– 1.6 – 3.6V

• Speed performance

– 0 – 12 MHz @ 1.6 – 3.6V

– 0 – 32 MHz @ 2.7 – 3.6V

Typical Applications

• Industrial control

• Factory automation

• Building control

• Board control

• Climate control

• ZigBee

• Hand-held battery applications

• Power tools

• HVAC

• Metering

• Medical Applications

• Motor control

• Networking

• Optical

• White Goods

8068E–AVR–08/08

XMEGA A3

1. Ordering Information

Ordering Code

Flash (B)

256K + 8K

192K + 8K

128K + 8K

64K + 4K

256K + 8K

192K + 8K

128K + 8K

64K + 4K

E²(B)

4K

SRAM (B)

16K

8K

Speed (MHz) Power Supply Package^(1)(2)(3)

Temp

ATxmega256A3-AU

ATxmega192A3-AU

ATxmega128A3-AU

ATxmega64A3-AU

ATxmega256A3-MU

ATxmega192A3-MU

ATxmega128A3-MU

ATxmega64A3-MU

32

1.6 - 3.6V

4K

64A

2K

4K

-40⋅ - 85⋅C

4K

16K

8K

4K

64M1

2K

4K

Notes:

1.

2.

3.

This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information.

Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.

For packaging information, see ”Packaging information” on page 66.

Package Type

64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm, 5.40 mm Exposed Pad, Micro Lead Frame Package (MLF)

64A

64M1

2. Pinout/Block Diagram

Figure 2-1. Block diagram and TQFP-pinout.

INDEX CORNER

PA3

PA4

PA5

PA6

PA7

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

GND

VCC

PC0

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

PF2

PF1

PF0

VCC

GND

PE7

PE6

PE5

PE4

PE3

PE2

PE1

PE0

VCC

GND

PD7

Port R

2

DATA BU S

3

ADC A

AC A0

AC A1

4

OSC/CLK

Control

BOD

TEMP

VREF

POR

OCD

5

RTC

6

Power

Control

FLASH

7

CPU

DMA

8

RAM

ADC B

DAC B

AC B0

AC B1

Reset

Control

9

E²PROM

10

11

12

13

14

15

16

Interrupt Controller

Event System ctrl

DATA BU S

Watchdog

EVENT ROUTING NETWORK

Port C

Port D

Port E

Port F

Note:

1. For full details on pinout and alternate pin functions refer to ”Pinout and Pin Functions” on page 48.

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XMEGA A3

3. Overview

The XMEGA A3 is a family of low power, high performance and peripheral rich CMOS 8/16-bit

microcontrollers based on the AVR^®enhanced RISC architecture. By executing powerful

instructions in a single clock cycle, the XMEGA A3 achieves throughputs approaching 1 Million

Instructions Per Second (MIPS) per MHz allowing the system designer to optimize power con-

sumption versus processing speed.

The AVR CPU combines a rich instruction set with 32 general purpose working registers. All the

32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction, executed in one clock cycle. The resulting

architecture is more code efficient while achieving throughputs many times faster than conven-

tional single-accumulator or CISC based microcontrollers.

The XMEGA A3 devices provide the following features: In-System Programmable Flash with

Read-While-Write capabilities, Internal EEPROM and SRAM, four-channel DMA Controller,

eight-channel Event System, Programmable Multi-level Interrupt Controller, 50 general purpose

I/O lines, 16-bit Real Time Counter (RTC), seven flexible 16-bit Timer/Counters with compare

modes and PWM, seven USARTs, two Two Wire Serial Interfaces (TWIs), three Serial Periph-

eral Interfaces (SPIs), AES and DES crypto engine, two 8-channel 12-bit ADCs with optional

differential input with programmable gain, one 2-channel 12-bit DACs, four analog comparators

with window mode, programmable Watchdog Timer with separate Internal Oscillator, accurate

internal oscillators with PLL and prescaler and programmable Brown-Out Detection.

The Program and Debug Interface (PDI), a fast 2-pin interface for programming and debugging,

is available. The devices also have an IEEE std. 1149.1 compliant JTAG test interface, and this

can also be used for On-chip Debug and programming.

The XMEGA A3 devices have five software selectable power saving modes. The Idle mode

stops the CPU while allowing the SRAM, DMA Controller, Event System, Interrupt Controller and

all peripherals to continue functioning. The Power-down mode saves the SRAM and register

contents but stops the oscillators, disabling all other functions until the next TWI or pin-change

interrupt, or Reset. In Power-save mode, the asynchronous Real Time Counter continues to run,

allowing the application to maintain a timer base while the rest of the device is sleeping. In

Standby mode, the Crystal/Resonator Oscillator is kept running while the rest of the device is

sleeping. This allows very fast start-up from external crystal combined with low power consump-

tion. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue

to run. To further reduce power consumption, the peripheral clock for each individual peripheral

can optionally be stopped in Active mode and Idle sleep mode.

The device is manufactured using Atmel's high-density nonvolatile memory technology. The pro-

gram Flash memory can be reprogrammed in-system through the PDI or JTAG. A Bootloader

running in the device can use any interface to download the application program to the Flash

memory. The Bootloader software in the Boot Flash section will continue to run while the Appli-

cation Flash section is updated, providing true Read-While-Write operation. By combining an

8/16-bit RISC CPU with In-System Self-Programmable Flash, the Atmel XMEGA A3 is a power-

ful microcontroller family that provides a highly flexible and cost effective solution for many

embedded applications.

The XMEGA A3 devices are supported with a full suite of program and system development

tools including: C compilers, macro assemblers, program debugger/simulators, programmers,

and evaluation kits.

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XMEGA A3

3.1

Block Diagram

Figure 3-1. XMEGA A3 Block Diagram

PR[0..1]

XTAL1

XTAL2

Oscillator

Circuits/

Clock

Watchdog

Oscillator

Real Time

Counter

Generation

Watchdog

Timer

DATA BUS

SRAM

VCC

GND

Power

Supervision

POR/BOD &

RESET

Event System

Controller

Oscillator

Control

PA[0..7]

PORT A (8)

DMA

Controller

Sleep

Controller

ACA

RESET/

PDI_CLK

PDI

ADCA

PDI_DATA

BUS

Controller

Prog/Debug

Controller

AREFA

JTAG

PORT B

Internal

Reference

DES

OCD

AREFB

CPU

Interrupt

Controller

AES

ADCB

ACB

NVM Controller

USARTF0

TCF0

PB[0..7]/

JTAG

PORT B (8)

DACB

PF[0..7]

Flash

EEPROM

IRCOM

DATA BUS

EVENT ROUTING NETWORK

To Clock

Generator

PORT C (8)

PORT D (8)

PORT E (8)

TOSC1

TOSC2

PC[0..7]

PD[0..7]

PE[0..7]

4

8068E–AVR–08/08

XMEGA A3

4. Resources

A comprehensive set of development tools, application notes and datasheets are available for

download on http://www.atmel.com/avr.

4.1

Recommended reading

• XMEGA A Manual

• XMEGA A Application Notes

This device data sheet only contains part specific information and a short description of each

peripheral and module. The XMEGA A Manual describes the modules and peripherals in depth.

The XMEGA A application notes contain example code and show applied use of the modules

and peripherals.

The XMEGA A Manual and Application Notes are available from http://www.atmel.com/avr.

5. Disclaimer

For devices that are not available yet, typical values contained in this datasheet are based on

simulations and characterization of other AVR XMEGA microcontrollers manufactured on the

same process technology. Min. and Max values will be available after the device is

characterized.

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XMEGA A3

6. AVR CPU

6.1

Features

• 8/16-bit high performance AVR RISC Architecture

– 138 instructions

– Hardware multiplier

• 32x8-bit registers directly connected to the ALU

• Stack in RAM

• Stack Pointer accessible in I/O memory space

• Direct addressing of up to 16M bytes of program and data memory

• True 16/24-bit access to 16/24-bit I/O registers

• Support for 8-, 16- and 32-bit Arithmetic

• Configuration Change Protection of system critical features

6.2

Overview

The XMEGA A3 uses an 8/16-bit AVR CPU. The main function of the AVR CPU is to ensure cor-

rect program execution. The CPU must therefore be able to access memories, perform

calculations and control peripherals. Interrupt handling is described in a separate section. Figure

6-1 on page 6 shows the CPU block diagram.

Figure 6-1. CPU block diagram

DATA BUS

Flash

Program

Counter

Memory

32 x 8 General

Purpose

Registers

Instruction

Register

OCD

STATUS/

CONTROL

Instruction

Decode

Multiplier/

DES

ALU

DATA BUS

Peripheral

Module 1

Peripheral

Module 2

SRAM

EEPROM

PMIC

The AVR uses a Harvard architecture - with separate memories and buses for program and

data. Instructions in the program memory are executed with a single level pipeline. While one

instruction is being executed, the next instruction is pre-fetched from the program memory.

6

8068E–AVR–08/08

XMEGA A3

This concept enables instructions to be executed in every clock cycle. The program memory is

In-System Re-programmable Flash memory.

6.3

6.4

Register File

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single

clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-

ical ALU operation, two operands are output from the Register File, the operation is executed,

and the result is stored back in the Register File - in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data

Space addressing - enabling efficient address calculations. One of these address pointers can

also be used as an address pointer for look up tables in Flash program memory.

ALU - Arithmetic Logic Unit

The high performance Arithmetic Logic Unit (ALU) supports arithmetic and logic operations

between registers or between a constant and a register. Single register operations can also be

executed. Within a single clock cycle, arithmetic operations between general purpose registers

or between a register and an immediate are executed. After an arithmetic or logic operation, the

Status Register is updated to reflect information about the result of the operation.

The ALU operations are divided into three main categories – arithmetic, logical, and bit-func-

tions. Both 8- and 16-bit arithmetic is supported, and the instruction set allows for easy

implementation of 32-bit arithmetic. The ALU also provides a powerful multiplier supporting both

signed and unsigned multiplication and fractional format.

6.5

Program Flow

When the device is powered on, the CPU starts to execute instructions from the lowest address

in the Flash Program Memory ‘0’. The Program Counter (PC) addresses the next instruction to

be fetched. After a reset, the PC is set to location ‘0’.

Program flow is provided by conditional and unconditional jump and call instructions, capable of

addressing the whole address space directly. Most AVR instructions use a 16-bit word format,

while a limited number uses a 32-bit format.

During interrupts and subroutine calls, the return address PC is stored on the Stack. The Stack

is effectively allocated in the general data SRAM, and consequently the Stack size is only limited

by the total SRAM size and the usage of the SRAM. After reset the Stack Pointer (SP) points to

the highest address in the internal SRAM. The SP is read/write accessible in the I/O memory

space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can

easily be accessed through the five different addressing modes supported in the AVR CPU.

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8068E–AVR–08/08

XMEGA A3

7. Memories

7.1

Features

• Flash Program Memory

– One linear address space

– In-System programmable

– Self-Programming and Bootloader support

– Application Section for application code

– Application Table Section for application code or data storage

– Boot Section for application code or bootloader code

– Separate lock bits and protection for all sections

• Data Memory

– One linear address space

– Single cycle access from CPU

– SRAM

– EEPROM

Byte or page accessible

Optional memory mapping for direct load and store

– I/O Memory

Configuration and Status register for all peripherals and modules

16-bit accessible General Purpose Register for global variables or flags

– External Memory support

– Bus arbitration

Safe and deterministic handling of CPU and DMA Controller priority

– Separate buses for SRAM, EEPROM, I/O Memory and External Memory access

Simultaneous bus access for CPU and DMA Controller

• Calibration Row Memory for factory programmed data

Oscillator calibration bytes

Serial number

Device ID for each device type

• User Signature Row

One flash page in size

Can be read and written from software

Data is kept after Chip Erase

7.2

Overview

The AVR architecture has two main memory spaces, the Program Memory and the Data Mem-

ory. In addition, the XMEGA A3 features an EEPROM Memory for non-volatile data storage. All

three memory spaces are linear and require no paging. The available memory size configura-

tions are shown in ”Ordering Information” on page 2. In addition each device has a Flash

memory signature row for calibration data, device identification, serial number etc.

Non-volatile memory spaces can be locked for further write or read/write operations. This pre-

vents unrestricted access to the application software.

8

8068E–AVR–08/08

XMEGA A3

7.3

In-System Programmable Flash Program Memory

The XMEGA A3 devices contains On-chip In-System Programmable Flash memory for program

storage, see Figure 7-1 on page 9. Since all AVR instructions are 16- or 32-bits wide, each Flash

address location is 16 bits.

The Program Flash memory space is divided into Application and Boot sections. Both sections

have dedicated Lock Bits for setting restrictions on write or read/write operations. The Store Pro-

gram Memory (SPM) instruction must reside in the Boot Section when used to write to the Flash

memory.

A third section inside the Application section is referred to as the Application Table section which

has separate Lock bits for storage of write or read/write protection. The Application Table sec-

tion can be used for storing non-volatile data or application software.

Figure 7-1. Flash Program Memory (Hexadecimal address)

Word Address

0

Application Section

(256K/192K/128K/64K)

...

1EFFF

1F000

1FFFF

20000

20FFF

/

16FFF

17000

17FFF

18000

18FFF

/

EFFF

F000

/

77FF

7800

7FFF

8000

87FF

Application Table Section

(8K/8K/8K/4K)

FFFF

10000

10FFF

Boot Section

(8K/8K/8K/4K)

The Application Table Section and Boot Section can also be used for general application

software.

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8068E–AVR–08/08

XMEGA A3

7.4

Data Memory

The Data Memory consist of the I/O Memory, EEPROM and SRAM memories, all within one lin-

ear address space, see Figure 7-2 on page 10. To simplify development, the memory map for all

devices in the family is identical and with empty, reserved memory space for smaller devices.

Figure 7-2. Data Memory Map (Hexadecimal address)

Byte Address

ATxmega192A3

Byte Address

ATxmega128A3

Byte Address

ATxmega64A3

0

I/O Registers

(4KB)

I/O Registers

(4KB)

I/O Registers

(4KB)

FFF

1000

17FF

FFF

1000

17FF

1000

EEPROM

(2K)

EEPROM

(2K)

EEPROM

(4K)

RESERVED

1FFF

2000

3FFF

2000

2FFF

Internal SRAM

(16K)

Internal SRAM

(8K)

Internal SRAM

(4K)

5FFF

6000

4000

3000

External Memory

(0 - 16 MB)

External Memory

(0 - 16 MB)

External Memory

(0 - 16 MB)

FFFFFF

Byte Address

ATxmega256A3

0

FFF

I/O Registers

(4KB)

1000

EEPROM

(4K)

1FFF

2000

Internal SRAM

(16K)

5FFF

6000

External Memory

(0 - 16 MB)

FFFFFF

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8068E–AVR–08/08

XMEGA A3

7.4.1

I/O Memory

All peripherals and modules are addressable through I/O memory locations in the data memory

space. All I/O memory locations can be accessed by the Load (LD/LDS/LDD) and Store

(ST/STS/STD) instructions, transferring data between the 32 general purpose registers in the

CPU and the I/O Memory.

The IN and OUT instructions can address I/O memory locations in the range 0x00 - 0x3F

directly.

I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and

CBI instructions. The value of single bits can be checked by using the SBIS and SBIC instruc-

tions on these registers.

The I/O memory address for all peripherals and modules in XMEGA A3 is shown in the ”Periph-

eral Module Address Map” on page 53.

7.4.2

7.4.3

SRAM Data Memory

The XMEGA A3 devices has internal SRAM memory for data storage.

EEPROM Data Memory

The XMEGA A3 devices has internal EEPROM memory for non-volatile data storage. It is

addressable either in a separate data space or it can be memory mapped into the normal data

memory space. The EEPROM memory supports both byte and page access.

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8068E–AVR–08/08

XMEGA A3

7.5

Calibration Row

The Calibration Row is a separate memory section for factory programmed data. It contains cal-

ibration data for functions such as oscillators, device ID, and a factory programmed serial

number that is unique for each device. The device ID for the available XMEGA A3 devices is

shown in Table 7-1 on page 12. Some of the calibration values will be automatically loaded to

the corresponding module or peripheral unit during reset. The Calibration Row can not be written

or erased. It can be read from application software and external programming.

Table 7-1.

Device ID bytes for XMEGA A3 devices.

Device

Device ID bytes

Byte 2

Byte 1

96

Byte 0

1E

ATxmega64A3

ATxmega128A3

ATxmega192A3

ATxmega256A3

42

44

42

97

1E

97

1E

98

1E

7.6

User Signature Row

The User Signature Row is a separate memory section that is fully accessible (read and write)

from application software and external programming. The User Signature Row is one flash page

in size, and is meant for static user parameter storage, such as calibration data, custom serial

numbers, random number seeds etc. This section is not erased by Chip Erase, and requires a

dedicated erase command. This ensures parameter storage during multiple program/erase ses-

sion and On-Chip Debug sessions.

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8068E–AVR–08/08

XMEGA A3

7.7

Flash and EEPROM Page Size

The Flash Program Memory and EEPROM data memory is organized in pages. The pages are

word accessible for the Flash and byte accessible for the EEPROM.

Table 7-2 on page 13 shows the Flash Program Memory organization. Flash write and erase

operations are performed on one page at the time, while reading the Flash is done one byte at

the time. For Flash access the Z-pointer (Z[m:n]) is used for addressing. The most significant

bits in the address (FPAGE) gives the page number and the least significant address bits

(FWORD) gives the word in the page.

Table 7-2.

Number of words and Pages in the Flash.

Devices

Flash

Page Size

(words)

128

FWORD

FPAGE

Application

Boot

No of Pages

Size (Bytes)

64K + 4K

Size

No of Pages

Size

4K

ATxmega64A3

ATxmega128A3

ATxmega192A3

ATxmega256A3

Z[7:1]

Z[8:1]

Z[16:8]

Z[17:9]

Z[18:9]

64K

256

384

512

16

128K + 8K

192K + 8K

256K + 8K

256

128K

192K

256K

8K

256

8K

256

8K

Table 7-3 on page 13 shows EEPROM memory organization for the XMEGA A3 devices.

EEEPROM write and erase operations can be performed one page or one byte at the time, while

reading the EEPROM is done one byte at the time. For EEPROM access the NVM Address

Register (ADDR[m:n] is used for addressing. The most significant bits in the address (E2PAGE)

gives the page number and the least significant address bits (E2BYTE) gives the byte in the

page.

Table 7-3.

Number of bytes and Pages in the EEPROM.

Devices

EEPROM

Page Size

E2BYTE

E2PAGE

No of Pages

Size (Bytes)

(Bytes)

32

ATxmega64A3

ATxmega128A3

ATxmega192A3

ATxmega256A3

2K

4K

ADDR[4:0]

ADDR[10:5]

ADDR[11:5]

64

32

64

32

128

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8068E–AVR–08/08

XMEGA A3

8. DMAC - Direct Memory Access Controller

8.1

Features

• Allows High-speed data transfer

– From memory to peripheral

– From memory to memory

– From peripheral to memory

– From peripheral to peripheral

• 4 Channels

• From 1 byte and up to 16 M bytes transfers in a single transaction

• Multiple addressing modes for source and destination address

– Increment

– Decrement

– Static

• 1, 2, 4, or 8 bytes Burst Transfers

• Programmable priority between channels

8.2

Overview

The XMEGA A3 has a Direct Memory Access (DMA) Controller to move data between memories

and peripherals in the data space. The DMA controller uses the same data bus as the CPU to

transfer data.

It has 4 channels that can be configured independently. Each DMA channel can perform data

transfers in blocks of configurable size from 1 to 64K bytes. A repeat counter can be used to

repeat each block transfer for single transactions up to 16M bytes. Each DMA channel can be

configured to access the source and destination memory address with incrementing, decrement-

ing or static addressing. The addressing is independent for source and destination address.

When the transaction is complete the original source and destination address can automatically

be reloaded to be ready for the next transaction.

The DMAC can access all the peripherals through their I/O memory registers, and the DMA may

be used for automatic transfer of data to/from communication modules, as well as automatic

data retrieval from ADC conversions, data transfer to DAC conversions, or data transfer to or

from port pins. A wide range of transfer triggers is available from the peripherals, Event System

and software. Each DMA channel has different transfer triggers.

To allow for continuous transfers, two channels can be interlinked so that the second takes over

the transfer when the first is finished and vice versa.

The DMA controller can read from memory mapped EEPROM, but it cannot write to the

EEPROM or access the Flash.

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XMEGA A3

9. Event System

9.1

Features

• Inter-peripheral communication and signalling with minimum latency

• CPU and DMA independent operation

• 8 Event Channels allows for up to 8 signals to be routed at the same time

• Events can be generated by

– Timer/Counters (TCxn)

– Real Time Counter (RTC)

– Analog to Digital Converters (ADCx)

– Analog Comparators (ACx)

– Ports (PORTx)

– System Clock (Clk_SYS

)

– Software (CPU)

• Events can be used by

– Timer/Counters (TCxn)

– Analog to Digital Converters (ADCx)

– Digital to Analog Converters (DACx)

– Ports (PORTx)

– DMA Controller (DMAC)

– IR Communication Module (IRCOM)

• The same event can be used by multiple peripherals for synchronized timing

• Advanced Features

– Manual Event Generation from software (CPU)

– Quadrature Decoding

– Digital Filtering

• Functions in Active and Idle mode

9.2

Overview

The Event System is a set of features for inter-peripheral communication. It enables the possibil-

ity for a change of state in one peripheral to automatically trigger actions in one or more

peripherals. What changes in a peripheral that will trigger actions in other peripherals are config-

urable by software. It is a simple, but powerful system as it allows for autonomous control of

peripherals without any use of interrupts, CPU or DMA resources.

The indication of a change in a peripheral is referred to as an event, and is usually the same as

the interrupt conditions for that peripheral. Events are passed between peripherals using a dedi-

cated routing network called the Event Routing Network. Figure 9-1 on page 16 shows a basic

block diagram of the Event System with the Event Routing Network and the peripherals to which

it is connected. This highly flexible system can be used for simple routing of signals, pin func-

tions or for sequencing of events.

The maximum latency is two CPU clock cycles from when an event is generated in one periph-

eral, until the actions are triggered in one or more other peripherals.

The Event System is functional in both Active and Idle modes.

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XMEGA A3

Figure 9-1. Event system block diagram.

ClkSYS

PORTx

CPU

ADCx

RTC

ACx

Event Routing

Network

DACx

IRCOM

DMAC

T/Cxn

The Event Routing Network can directly connect together ADCs, DACs, Analog Comparators

(ACx), I/O ports (PORTx), the Real-time Counter (RTC), Timer/Counters (T/C) and the IR Com-

munication Module (IRCOM). Events can also be generated from software (CPU).

All events from all peripherals are always routed into the Event Routing Network. This consist of

eight multiplexers where each can be configured in software to select which event to be routed

into that event channel. All eight event channels are connected to the peripherals that can use

events, and each of these peripherals can be configured to use events from one or more event

channels to automatically trigger a software selectable action.

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10. System Clock and Clock options

10.1 Features

• Fast start-up time

• Safe run-time clock switching

• Internal Oscillators:

– 32 MHz run-time calibrated RC oscillator

– 2 MHz run-time calibrated RC oscillator

– 32 kHz calibrated RC oscillator

– 32 kHz Ultra Low Power (ULP) oscillator

• External clock options

– 0.4 - 16 MHz Crystal Oscillator

– 32 kHz Crystal Oscillator

– External clock

• PLL with internal and external clock options with 2 to 31x multiplication

• Clock Prescalers with 2 to 2048x division

• Fast peripheral clock running at 2 and 4 times the CPU clock speed

• Automatic Run-Time Calibration of internal oscillators

• Crystal Oscillator failure detection

10.2 Overview

XMEGA A3 has an advanced clock system, supporting a large number of clock sources. It incor-

porates both integrated oscillators, external crystal oscillators and resonators. A high frequency

Phase Locked Loop (PLL) and clock prescalers can be controlled from software to generate a

wide range of clock frequencies from the clock source input.

It is possible to switch between clock sources from software during run-time. After reset the

device will always start up running from the 2 Mhz internal oscillator.

A calibration feature is available, and can be used for automatic run-time calibration of the inter-

nal 2 MHz and 32 MHz oscillators. This reduce frequency drift over voltage and temperature.

A Crystal Oscillator Failure Monitor can be enabled to issue a Non-Maskable Interrupt and

switch to internal oscillator if the external oscillator fails. Figure 10-1 on page 18 shows the prin-

cipal clock system in XMEGA A3.

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Figure 10-1. Clock system overview

clk_ULP

clk_RTC

WDT/BOD

RTC

32 kHz ULP

Internal Oscillator

32.768 kHz

Calibrated Internal

Oscillator

PERIPHERALS

ADC

2 MHz

Run-Time Calibrated

Internal Oscillator

DAC

PORTS

...

CLOCK CONTROL

UNIT

32 MHz

Run-time Calibrated

Internal Oscillator

clk_PER

with PLL and

Prescaler

DMA

INTERRUPT

EVSYS

32.768 KHz

Crystal Oscillator

RAM

0.4 - 16 MHz

Crystal Oscillator

CPU

NVM MEMORY

FLASH

clk_CPU

External

Clock Input

EEPROM

Each clock source is briefly described in the following sub-sections.

10.3 Clock Options

10.3.1

32 kHz Ultra Low Power Internal Oscillator

The 32 kHz Ultra Low Power (ULP) Internal Oscillator is a very low power consumption clock

source. It is used for the Watchdog Timer, Brown-Out Detection and as an asynchronous clock

source for the Real Time Counter. This oscillator cannot be used as the system clock source,

and it cannot be directly controlled from software.

10.3.2

32.768 kHz Calibrated Internal Oscillator

The 32.768 kHz Calibrated Internal Oscillator is a high accuracy clock source that can be used

as the system clock source or as an asynchronous clock source for the Real Time Counter. It is

calibrated during protection to provide a default frequency which is close to its nominal

frequency.

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10.3.3

10.3.4

10.3.5

32.768 kHz Crystal Oscillator

The 32.768 kHz Crystal Oscillator is a low power driver for an external watch crystal. It can be

used as system clock source or as asynchronous clock source for the Real Time Counter.

0.4 - 16 MHz Crystal Oscillator

The 0.4 - 16 MHz Crystal Oscillator is a driver intended for driving both external resonators and

crystals ranging from 400 kHz to 16 MHz.

2 MHz Run-time Calibrated Internal Oscillator

The 2 MHz Run-time Calibrated Internal Oscillator is a high frequency oscillator. It is calibrated

during protection to provide a default frequency which is close to its nominal frequency. The

oscillator can use the 32 kHz Calibrated Internal Oscillator or the 32 kHz Crystal Oscillator as a

source for calibrating the frequency run-time to compensate for temperature and voltage drift

hereby optimizing the accuracy of the oscillator.

10.3.6

32 MHz Run-time Calibrated Internal Oscillator

The 32 MHz Run-time Calibrated Internal Oscillator is a high frequency oscillator. It is calibrated

during protection to provide a default frequency which is close to its nominal frequency. The

oscillator can use the 32 kHz Calibrated Internal Oscillator or the 32 kHz Crystal Oscillator as a

source for calibrating the frequency run-time to compensate for temperature and voltage drift

hereby optimizing the accuracy of the oscillator.

10.3.7

10.3.8

External Clock input

The external clock input gives the possibility to connect a clock from an external source.

PLL with Multiplication factor 2 - 31x

The PLL provides the possibility of multiplying a frequency by any number from 2 to 31. In com-

bination with the prescalers, this gives a wide range of output frequencies from all clock sources.

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11. Power Management and Sleep Modes

11.1 Features

• 5 sleep modes

– Idle

– Power-down

– Power-save

– Standby

– Extended standby

• Power Reduction registers to disable clocks to unused peripherals

11.2 Overview

The XMEGA A3 provides various sleep modes tailored to reduce power consumption to a mini-

mum. All sleep modes are available and can be entered from Active mode. In Active mode the

CPU is executing application code. The application code decides when and what sleep mode to

enter. Interrupts from enabled peripherals and all enabled reset sources can restore the micro-

controller from sleep to Active mode.

In addition, Power Reduction registers provide a method to stop the clock to individual peripher-

als from software. When this is done, the current state of the peripheral is frozen and there is no

power consumption from that peripheral. This reduces the power consumption in Active mode

and Idle sleep mode.

11.3 Sleep Modes

11.3.1

Idle Mode

In Idle mode the CPU and Non-Volatile Memory are stopped, but all peripherals including the

Interrupt Controller, Event System and DMA Controller are kept running. Interrupt requests from

all enabled interrupts will wake the device.

11.3.2

Power-down Mode

In Power-down mode all system clock sources, and the asynchronous Real Time Counter (RTC)

clock source, are stopped. This allows operation of asynchronous modules only. The only inter-

rupts that can wake up the MCU are the Two Wire Interface address match interrupts, and

asynchronous port interrupts, e.g pin change.

11.3.3

11.3.4

Power-save Mode

Power-save mode is identical to Power-down, with one exception: If the RTC is enabled, it will

keep running during sleep and the device can also wake up from RTC interrupts.

Standby Mode

Standby mode is identical to Power-down with the exception that all enabled system clock

sources are kept running, while the CPU, Peripheral and RTC clocks are stopped. This reduces

the wake-up time when external crystals or resonators are used.

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11.3.5

Extended Standby Mode

Extended Standby mode is identical to Power-save mode with the exception that all enabled

system clock sources are kept running while the CPU and Peripheral clocks are stopped. This

reduces the wake-up time when external crystals or resonators are used.

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12. System Control and Reset

12.1 Features

• Multiple reset sources for safe operation and device reset

– Power-On Reset

– External Reset

– Watchdog Reset

The Watchdog Timer runs from separate, dedicated oscillator

– Brown-Out Reset

Accurate, programmable Brown-Out levels

– JTAG Reset

– PDI reset

– Software reset

• Asynchronous reset

– No running clock in the device is required for reset

• Reset status register

12.2 Resetting the AVR

During reset, all I/O registers are set to their initial values. The SRAM content is not reset. Appli-

cation execution starts from the Reset Vector. The instruction placed at the Reset Vector should

be an Absolute Jump (JMP) instruction to the reset handling routine. By default the Reset Vector

address is the lowest Flash program memory address, ‘0’, but it is possible to move the Reset

Vector to the first address in the Boot Section.

The I/O ports of the AVR are immediately tri-stated when a reset source goes active.

The reset functionality is asynchronous, so no running clock is required to reset the device.

After the device is reset, the reset source can be determined by the application by reading the

Reset Status Register.

12.3 Reset Sources

12.3.1

12.3.2

12.3.3

Power-On Reset

The MCU is reset when the supply voltage VCC is below the Power-on Reset threshold voltage.

External Reset

The MCU is reset when a low level is present on the RESET pin.

Watchdog Reset

The MCU is reset when the Watchdog Timer period expires and the Watchdog Reset is enabled.

The Watchdog Timer runs from a dedicated oscillator independent of the System Clock. For

more details see ”WDT - Watchdog Timer” on page 23.

12.3.4

Brown-Out Reset

The MCU is reset when the supply voltage VCC is below the Brown-Out Reset threshold voltage

and the Brown-out Detector is enabled. The Brown-out threshold voltage is programmable.

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12.3.5

JTAG reset

The MCU is reset as long as there is a logic one in the Reset Register in one of the scan chains

of the JTAG system. Refer to IEEE 1149.1 (JTAG) Boundary-scan for details.

12.3.6

12.3.7

PDI reset

The MCU can be reset through the Program and Debug Interface (PDI).

Software reset

The MCU can be reset by the CPU writing to a special I/O register through a timed sequence.

12.4 WDT - Watchdog Timer

12.4.1

Features

• 11 selectable timeout periods, from 8 ms to 8s.

• Two operation modes

– Standard mode

– Window mode

• Runs from the 1 kHz output of the 32 kHz Ultra Low Power oscillator

• Configuration lock to prevent unwanted changes

12.4.2

Overview

The XMEGA A3 has a Watchdog Timer (WDT). The WDT will run continuously when turned on

and if the Watchdog Timer is not reset within a software configurable time-out period, the micro-

controller will be reset. The Watchdog Reset (WDR) instruction must be run by software to reset

the WDT, and prevent microcontroller reset.

The WDT has a Window mode. In this mode the WDR instruction must be run within a specified

period called a window. Application software can set the minimum and maximum limits for this

window. If the WDR instruction is not executed inside the window limits, the microcontroller will

be reset.

A protection mechanism using a timed write sequence is implemented in order to prevent

unwanted enabling, disabling or change of WDT settings.

For maximum safety, the WDT also has an Always-on mode. This mode is enabled by program-

ming a fuse. In Always-on mode, application software can not disable the WDT.

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13. PMIC - Programmable Multi-level Interrupt Controller

13.1 Features

• Separate interrupt vector for each interrupt

• Short, predictable interrupt response time

• Programmable Multi-level Interrupt Controller

– 3 programmable interrupt levels

– Selectable priority scheme within low level interrupts (round-robin or fixed)

– Non-Maskable Interrupts (NMI)

• Interrupt vectors can be moved to the start of the Boot Section

13.2 Overview

XMEGA A3 has a Programmable Multi-level Interrupt Controller (PMIC). All peripherals can

define three different priority levels for interrupts; high, medium or low. Medium level interrupts

may interrupt low level interrupt service routines. High level interrupts may interrupt both low-

and medium level interrupt service routines. Low level interrupts have an optional round robin

scheme to make sure all interrupts are serviced within a certain amount of time.

The built in oscillator failure detection mechanism can issue a Non-Maskable Interrupt (NMI).

13.3 Interrupt vectors

When an interrupt is serviced, the program counter will jump to the interrupt vector address. The

interrupt vector is the sum of the peripheral’s base interrupt address and the offset address for

specific interrupts in each peripheral. The base addresses for the XMEGA A3 devices are shown

in Table 13-1. Offset addresses for each interrupt available in the peripheral are described for

each peripheral in the XMEGA A manual. For peripherals or modules that have only one inter-

rupt, the interrupt vector is shown in Table 13-1. The program address is the word address.

Table 13-1. Reset and Interrupt Vectors

Program Address

(Base Address)

Source

Interrupt Description

0x000

0x002

0x004

0x008

0x00C

0x014

0x018

0x01C

0x028

0x030

0x032

0x03D

0x03E

RESET

OSCF_INT_vect

PORTC_INT_base

PORTR_INT_base

DMAC_INT_base

RTC_INT_base

TWIC_INT_base

TIMERC0_INT_base

TIMERC1_INT_base

SPIC_INT_vect

USARTC0_INT_base

USARTC1_INT_base

AES_INT_vect

Crystal Oscillator Failure Interrupt vector (NMI)

Port C Interrupt base

Port R Interrupt base

DMA Controller Interrupt base

Real Time Counter Interrupt base

Two-Wire Interface on Port C Interrupt base

Timer/Counter 0 on port C Interrupt base

Timer/Counter 1 on port C Interrupt base

SPI on port C Interrupt vector

USART 0 on port C Interrupt base

USART 1 on port C Interrupt base

AES Interrupt vector

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Table 13-1. Reset and Interrupt Vectors (Continued)

Program Address

(Base Address)

0x040

0x044

0x048

0x04E

0x056

0x05A

0x05E

0x06A

0x072

0x074

0x07A

0x080

0x084

0x088

0x08E

0x09A

0x0A6

0x0AE

0x0B0

0x0B6

0x0D0

0x0D8

0x0EE

Source

Interrupt Description

NVM_INT_base

Non-Volatile Memory Interrupt base

Port B Interrupt base

PORTB_INT_base

ACB_INT_base

Analog Comparator on Port B Interrupt base

ADCB_INT_base

PORTE_INT_base

TWIE_INT_base

Analog to Digital Converter on Port B Interrupt base

Port E INT base

Two-Wire Interface on Port E Interrupt base

Timer/Counter 0 on port E Interrupt base

Timer/Counter 1 on port E Interrupt base

SPI on port E Interrupt vector

TIMERE0_INT_base

TIMERE1_INT_base

SPIE_INT_vect

USARTE0_INT_base

USARTE1_INT_base

PORTD_INT_base

PORTA_INT_base

ACA_INT_base

USART 0 on port E Interrupt base

USART 1 on port E Interrupt base

Port D Interrupt base

Port A Interrupt base

Analog Comparator on Port A Interrupt base

Analog to Digital Converter on Port A Interrupt base

Timer/Counter 0 on port D Interrupt base

Timer/Counter 1 on port D Interrupt base

SPI D Interrupt vector

ADCA_INT_base

TIMERD0_INT_base

TIMERD1_INT_base

SPID_INT_vector

USARTD0_INT_base

USARTD1_INT_base

PORTF_INT_base

TIMERF0_INT_base

USARTF0_INT_base

USART 0 on port D Interrupt base

USART 1 on port D Interrupt base

Port F Interrupt base

Timer/Counter 0 on port F Interrupt base

USART 0 on port F Interrupt base

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14. I/O Ports

14.1 Features

• Selectable input and output configuration for each pin individually

• Flexible pin configuration through dedicated Pin Configuration Register

• Synchronous and/or asynchronous input sensing with port interrupts and events

– Sense both edges

– Sense rising edges

– Sense falling edges

– Sense low level

• Asynchronous wake-up from all input sensing configurations

• Two port interrupts with flexible pin masking

• Highly configurable output driver and pull settings:

–

Totem-pole

Pull-up/-down

Wired-AND

Wired-OR

Bus-keeper

Inverted I/O

• Optional Slew rate control

• Configuration of multiple pins in a single operation

• Read-Modify-Write (RMW) support

• Toggle/clear/set registers for Output and Direction registers

• Clock output on port pin

• Event Channel 7 output on port pin

• Mapping of port registers (virtual ports) into bit accessible I/O memory space

14.2 Overview

The XMEGA A3 devices have flexible General Purpose I/O Ports. A port consists of up to 8 pins,

ranging from pin 0 to pin 7. The ports implement several functions, including synchronous/asyn-

chronous input sensing, pin change interrupts and configurable output settings. All functions are

individual per pin, but several pins may be configured in a single operation.

14.3 I/O configuration

All port pins (Pn) have programmable output configuration. In addition, all port pins have an

inverted I/O function. For an input, this means inverting the signal between the port pin and the

pin register. For an output, this means inverting the output signal between the port register and

the port pin. The inverted I/O function can be used also when the pin is used for alternate func-

tions. The port pins also have configurable slew rate limitation to reduce electromagnetic

emission.

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14.3.1

Push-pull

Figure 14-1. I/O configuration - Totem-pole

DIRn

OUTn

INn

Pn

14.3.2

Pull-down

Figure 14-2. I/O configuration - Totem-pole with pull-down (on input)

DIRn

OUTn

INn

Pn

14.3.3

Pull-up

Figure 14-3. I/O configuration - Totem-pole with pull-up (on input)

DIRn

OUTn

INn

Pn

14.3.4

Bus-keeper

The bus-keeper’s weak output produces the same logical level as the last output level. It acts as

a pull-up if the last level was ‘1’, and pull-down if the last level was ‘0’.

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Figure 14-4. I/O configuration - Totem-pole with bus-keeper

DIRn

OUTn

INn

Pn

14.3.5

Others

Figure 14-5. Output configuration - Wired-OR with optional pull-down

OUTn

Pn

INn

Figure 14-6. I/O configuration - Wired-AND with optional pull-up

INn

Pn

OUTn

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14.4 Input sensing

• Sense both edges

• Sense rising edges

• Sense falling edges

• Sense low level

Input sensing is synchronous or asynchronous depending on the enabled clock for the ports,

and the configuration is shown in Figure 14-7 on page 29.

Figure 14-7. Input sensing system overview

Asynchronous sensing

EDGE

DETECT

Interrupt

Control

IREQ

Event

Synchronous sensing

Pn

Synchronizer

INn

EDGE

DETECT

Q

D

INVERTEDI/O

R

When a pin is configured with inverted I/O the pin value is inverted before the input sensing.

14.5 Port Interrupt

Each ports have two interrupts with separate priority and interrupt vector. All pins on the port can

be individually selected as source for each of the interrupts. The interrupts are then triggered

according to the input sense configuration for each pin configured as source for the interrupt.

14.6 Alternate Port Functions

In addition to the input/output functions on all port pins, most pins have alternate functions. This

means that other modules or peripherals connected to the port can use the port pins for their

functions, such as communication or pulse-width modulation. ”Pinout and Pin Functions” on

page 48 shows which modules on peripherals that enables alternate functions on a pin, and

what alternate functions that is available on a pin.

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15. T/C - 16-bits Timer/Counter with PWM

15.1 Features

• Seven 16-bit Timer/Counters

– Four Timer/Counters of type 0

– Three Timer/Counters of type 1

• Four Compare or Capture (CC) Channels in Timer/Counter 0

• Two Compare or Capture (CC) Channels in Timer/Counter 1

• Double Buffered Timer Period Setting

• Double Buffered Compare or Capture Channels

• Waveform Generation:

– Single Slope Pulse Width Modulation

– Dual Slope Pulse Width Modulation

– Frequency Generation

• Input Capture:

– Input Capture with Noise Cancelling

– Frequency capture

– Pulse width capture

– 32-bit input capture

• Event Counter with Direction Control

• Timer Overflow and Timer Error Interrupts and Events

• One Compare Match or Capture Interrupt and Event per CC Channel

• Supports DMA Operation

• Hi-Resolution Extension (Hi-Res)

• Advanced Waveform Extension (AWEX)

15.2 Overview

XMEGA A3 has seven Timer/Counters, four Timer/Counter 0 and three Timer/Counter 1. The

difference between them is that Timer/Counter 0 has four Compare/Capture channels, while

Timer/Counter 1 has two Compare/Capture channels.

The Timer/Counters (T/C) are 16-bit and can count any clock, event or external input in the

microcontroller. A programmable prescaler is available to get a useful T/C resolution. Updates of

Timer and Compare registers are double buffered to ensure glitch free operation. Single slope

PWM, dual slope PWM and frequency generation waveforms can be generated using the Com-

pare Channels.

Through the Event System, any input pin or event in the microcontroller can be used to trigger

input capture, hence no dedicated pins is required for this. The input capture has a noise cancel-

ler to avoid incorrect capture of the T/C, and can be used to do frequency and pulse width

measurements.

A wide range of interrupt or event sources are available, including T/C Overflow, Compare

match and Capture for each Compare/Capture channel in the T/C.

PORTC, PORTD and PORTE each has one Timer/Counter 0 and one Timer/Counter1. PORTF

has one Timer/Counter 0. Notation of these are TCC0 (Time/Counter C0), TCC1, TCD0, TCD1,

TCE0, TCE1 and TCF0, respectively.

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Figure 15-1. Overview of a Timer/Counter and closely related peripherals

Timer/Counter

Base Counter

Prescaler

clk_PER

Timer Period

Counter

Control Logic

Event

System

clk_PER4

Compare/Capture Channel D

Compare/Capture Channel C

Compare/Capture Channel B

Compare/Capture Channel A

AWeX

Pattern

Generation

Fault

DTI

Dead-Time

Insertion

Capture

Comparator

Control

Protection

Waveform

Buffer

Generation

The Hi-Resolution Extension can be enabled to increase the waveform generation resolution by

2 bits (4x). This is available for all Timer/Counters. See ”Hi-Res - High Resolution Extension” on

page 33 for more details.

The Advanced Waveform Extension can be enabled to provide extra and more advanced fea-

tures for the Timer/Counter. This are only available for Timer/Counter 0. See ”AWEX - Advanced

Waveform Extension” on page 32 for more details.

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16. AWEX - Advanced Waveform Extension

16.1 Features

• Output with complementary output from each Capture channel

• Four Dead Time Insertion (DTI) Units, one for each Capture channel

• 8-bit DTI Resolution

• Separate High and Low Side Dead-Time Setting

• Double Buffered Dead-Time

• Event Controlled Fault Protection

• Single Channel Multiple Output Operation (for BLDC motor control)

• Double Buffered Pattern Generation

16.2 Overview

The Advanced Waveform Extension (AWEX) provides extra features to the Timer/Counter in

Waveform Generation (WG) modes. The AWEX enables easy and safe implementation of for

example, advanced motor control (AC, BLDC, SR, and Stepper) and power control applications.

Any WG output from a Timer/Counter 0 is split into a complimentary pair of outputs when any

AWEX feature is enabled. These output pairs go through a Dead-Time Insertion (DTI) unit that

enables generation of the non-inverted Low Side (LS) and inverted High Side (HS) of the WG

output with dead time insertion between LS and HS switching. The DTI output will override the

normal port value according to the port override setting. Optionally the final output can be

inverted by using the invert I/O setting for the port pin.

The Pattern Generation unit can be used to generate a synchronized bit pattern on the port it is

connected to. In addition, the waveform generator output from Compare Channel A can be dis-

tributed to, and override all port pins. When the Pattern Generator unit is enabled, the DTI unit is

bypassed.

The Fault Protection unit is connected to the Event System. This enables any event to trigger a

fault condition that will disable the AWEX output. Several event channels can be used to trigger

fault on several different conditions.

The AWEX is available for TCC0. The notation of this is AWEXC.

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17. Hi-Res - High Resolution Extension

17.1 Features

• Increases Waveform Generator resolution by 2-bits (4x)

• Supports Frequency, single- and dual-slope PWM operation

• Supports the AWEX when this is enabled and used for the same Timer/Counter

17.2 Overview

The Hi-Resolution (Hi-Res) Extension is able to increase the resolution of the waveform genera-

tion output by a factor of 4. When enabled for a Timer/Counter, the Fast Peripheral clock running

at four times the CPU clock speed will be as input to the Timer/Counter.

The High Resolution Extension can also be used when an AWEX is enabled and used with a

Timer/Counter.

XMEGA A3 devices have four Hi-Res Extensions that each can be enabled for each

Timer/Counters pair on PORTC, PORTD, PORTE and PORTF. The notation of these are

HIRESC, HIRESD, HIRESE and HIRESF, respectively.

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18. RTC - Real-Time Counter

18.1 Features

• 16-bit Timer

• Flexible Tick resolution ranging from 1 Hz to 32.768 kHz

• One Compare register

• One Period register

• Clear timer on Overflow or Compare Match

• Overflow or Compare Match event and interrupt generation

18.2 Overview

The XMEGA A3 includes a 16-bit Real-time Counter (RTC). The RTC can be clocked from an

accurate 32.768 kHz Crystal Oscillator, the 32.768 kHz Calibrated Internal Oscillator, or from the

32 kHz Ultra Low Power Internal Oscillator. The RTC includes both a Period and a Compare

register. For details, see Figure 18-1.

A wide range of Resolution and Time-out periods can be configured using the RTC. With a max-

imum resolution of 30.5 µs, time-out periods range up to 2000 seconds. With a resolution of 1

second, the maximum time-out period is over 18 hours (65536 seconds).

Figure 18-1. Real-time Counter overview

Period

Overflow

32 kHz

=

10-bit

prescaler

Counter

1 kHz

Compare Match

Compare

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19. TWI - Two Wire Interface

19.1 Features

• Two Identical TWI peripherals

• Simple yet Powerful and Flexible Communication Interface

• Both Master and Slave Operation Supported

• Device can Operate as Transmitter or Receiver

• 7-bit Address Space Allows up to 128 Different Slave Addresses

• Multi-master Arbitration Support

• Up to 400 kHz Data Transfer Speed

• Slew-rate Limited Output Drivers

• Noise Suppression Circuitry Rejects Spikes on Bus Lines

• Fully Programmable Slave Address with General Call Support

• Address Recognition Causes Wake-up when in Sleep Mode

• I²C and System Management Bus (SMBus) compatible

19.2 Overview

The Two-Wire Interface (TWI) is a bi-directional wired-AND bus with only two lines, the clock

(SCL) line and the data (SDA) line. The protocol makes it possible to interconnect up to 128 indi-

vidually addressable devices. Since it is a multi-master bus, one or more devices capable of

taking control of the bus can be connected.

The only external hardware needed to implement the bus is a single pull-up resistor for each of

the TWI bus lines. Mechanisms for resolving bus contention are inherent in the TWI protocol.

PORTC and PORTE each has one TWI. Notation of these peripherals are TWIC and TWIE.

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20. SPI - Serial Peripheral Interface

20.1 Features

• Three Identical SPI peripherals

• Full-duplex, Three-wire Synchronous Data Transfer

• Master or Slave Operation

• LSB First or MSB First Data Transfer

• Seven Programmable Bit Rates

• End of Transmission Interrupt Flag

• Write Collision Flag Protection

• Wake-up from Idle Mode

• Double Speed (CK/2) Master SPI Mode

20.2 Overview

The Serial Peripheral Interface (SPI) allows high-speed full-duplex, synchronous data transfer

between different devices. Devices can communicate using a master-slave scheme, and data is

transferred both to and from the devices simultaneously.

PORTC, PORTD, and PORTE each has one SPI. Notation of these peripherals are SPIC, SPID,

and SPIE respectively.

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21. USART

21.1 Features

• Seven Identical USART peripherals

• Full Duplex Operation (Independent Serial Receive and Transmit Registers)

• Asynchronous or Synchronous Operation

• Master or Slave Clocked Synchronous Operation

• High-resolution Arithmetic Baud Rate Generator

• Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits

• Odd or Even Parity Generation and Parity Check Supported by Hardware

• Data OverRun Detection

• Framing Error Detection

• Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter

• Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete

• Multi-processor Communication Mode

• Double Speed Asynchronous Communication Mode

• Master SPI mode for SPI communication

• IrDA support through the IRCOM module

21.2 Overview

The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a

highly flexible serial communication module. The USART supports full duplex communication,

and both asynchronous and clocked synchronous operation. The USART can also be set in

Master SPI mode to be used for SPI communication.

Communication is frame based, and the frame format can be customized to support a wide

range of standards. The USART is buffered in both direction, enabling continued data transmis-

sion without any delay between frames. There are separate interrupt vectors for receive and

transmit complete, enabling fully interrupt driven communication. Frame error and buffer over-

flow are detected in hardware and indicated with separate status flags. Even or odd parity

generation and parity check can also be enabled.

One USART can use the IRCOM module to support IrDA 1.4 physical compliant pulse modula-

tion and demodulation for baud rates up to 115.2 kbps.

PORTC, PORTD, and PORTE each has two USARTs, while PORTF has one USART only.

Notation of these peripherals are USARTC0, USARTC1, USARTD0, USARTD1, USARTE0,

USARTE1 and USARTF0, respectively.

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XMEGA A3

22. IRCOM - IR Communication Module

22.1 Features

• Pulse modulation/demodulation for infrared communication

• Compatible to IrDA 1.4 physical for baud rates up to 115.2 kbps

• Selectable pulse modulation scheme

– 3/16 of baud rate period

– Fixed pulse period, 8-bit programmable

– Pulse modulation disabled

• Built in filtering

• Can be connected to and used by one USART at the time

22.2 Overview

XMEGA contains an Infrared Communication Module (IRCOM) for IrDA communication with

baud rates up to 115.2 kbps. This supports three modulation schemes: 3/16 of baud rate period,

fixed programmable pulse time based on the Peripheral Clock speed, or pulse modulation dis-

abled. There is one IRCOM available which can be connected to any USART to enable infrared

pulse coding/decoding for that USART.

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XMEGA A3

23. Crypto Engine

23.1 Features

• Data Encryption Standard (DES) CPU instruction

• Advanced Encryption Standard (AES) Crypto module

• DES Instruction

– Encryption and Decryption

– Single-cycle DES instruction

– Encryption/Decryption in 16 clock cycles per 8-byte block

• AES Crypto Module

– Encryption and Decryption

– Support 128-bit keys

– Support XOR data load mode to the State memory for Cipher Block Chaining

– Encryption/Decryption in 375 clock cycles per 16-byte block

23.2 Overview

The Advanced Encryption Standard (AES) and Data Encryption Standard (DES) are two com-

monly used encryption standards. These are supported through an AES peripheral module and

a DES CPU instruction. All communication interfaces and the CPU can optionally use AES and

DES encrypted communication and data storage.

DES is supported by a DES instruction in the AVR XMEGA CPU. The 8-byte key and 8-byte

data blocks must be loaded into the Register file, and then DES must be executed 16 times to

encrypt/decrypt the data block.

The AES Crypto Module encrypts and decrypts 128-bit data blocks with the use of a 128-bit key.

The key and data must be loaded into the key and state memory in the module before encryp-

tion/decryption is started. It takes 375 peripheral clock cycles before the encryption/decryption is

done and decrypted/encrypted data can be read out, and an optional interrupt can be generated.

The AES Crypto Module also has DMA support with transfer triggers when encryption/decryp-

tion is done and optional auto-start of encryption/decryption when the state memory is fully

loaded.

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XMEGA A3

24. ADC - 12-bit Analog to Digital Converter

24.1 Features

• Two ADCs with 12-bit resolution

• 2 Msps sample rate for each ADC

• Signed and Unsigned conversions

• 4 result registers with individual input channel control for each ADC

• 8 single ended inputs for each ADC

• 8x4 differential inputs for each ADC

• Software selectable gain of 2, 4, 8, 16, 32 or 64

• Software selectable resolution of 8- or 12-bit.

• Internal or External Reference selection

• Event triggered conversion for accurate timing

• DMA transfer of conversion results

• Interrupt/Event on compare result

24.2 Overview

XMEGA A3 devices have two Analog to Digital Converters (ADC), see Figure 24-1 on page 41.

The two ADC modules can be operated simultaneously, individually or synchronized.

The ADC converts analog voltages to digital values. The ADC has 12-bit resolution and is capa-

ble of converting up to 2 million samples per second. The input selection is flexible, and both

single-ended and differential measurements can be performed. The ADC can provide both

signed and unsigned results, and an optional gain stage is available to increase the dynamic

range of the ADC.

It is a Successive Approximation Result (SAR) ADC. A SAR ADC measures one bit of the con-

version result at a time. The ADC has a pipeline architecture. This means that a new analog

voltage can be sampled and a new ADC measurement started on each ADC clock cycle. Each

sample will be converted in the pipeline, where the total sample and conversion time is seven

ADC clock cycles for 12-bit result and 5 ADC clock cycles for 8-bit result.

ADC measurements can be started by application software or an incoming event from another

peripheral in the device. Four different result registers with individual channel selection (MUX

registers) are provided to make it easier for the application to keep track of the data. It is also

possible to use DMA to move ADC results directly to memory or peripherals.

Both internal and external analog reference voltages can be used. An accurate internal 1.0V

reference is available.

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XMEGA A3

Figure 24-1. ADC overview

Channel A MUX selection

Channel B MUX selection

Channel C MUX selection

Channel D MUX selection

Configuration

Reference selection

Channel A

Register

Channel B

Register

ADC

Channel C

Register

Channel D

Register

Event

Trigger

1-64 X

Each ADC has four MUX selection registers with a corresponding result register. This means

that four channels can be sampled within 1.5 µs without any intervention by the application other

than starting the conversion. The results will be available in the result registers.

The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (prop-

agation delay) from 3.5 µs for 12-bit to 2.5 µs for 8-bit result.

ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding. This

eases calculation when the result is represented as a signed integer (signed 16-bit number).

PORTA and PORTB each has one ADC. Notation of these peripherals are ADCA and ADCB,

respectively.

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XMEGA A3

25. DAC - 12-bit Digital to Analog Converter

25.1 Features

• One DAC with 12-bit resolution

• Up to 1 Msps conversion rate for each DAC

• Flexible conversion range

• Multiple trigger sources

• 1 continuous output or 2 Sample and Hold (S/H) outputs for each DAC

• Built-in offset and gain calibration

• High drive capabilities

• Low Power Mode

25.2 Overview

The XMEGA A3 devices features two 12-bit, 1 Msps DACs with built-in offset and gain calibra-

tion, see Figure 25-1 on page 42.

A DAC converts a digital value into an analog signal. The DAC may use an internal 1.1 voltage

as the upper limit for conversion, but it is also possible to use the supply voltage or any applied

voltage in-between. The external reference input is shared with the ADC reference input.

Figure 25-1. DAC overview

Configuration

Reference selection

Channel A

Register

Channel A

DAC

Channel B

Register

Event

Trigger

Each DAC has one continuous output with high drive capabilities for both resistive and capaci-

tive loads. It is also possible to split the continuous time channel into two Sample and Hold (S/H)

channels, each with separate data conversion registers.

A DAC conversion may be started from the application software by writing the data conversion

registers. The DAC can also be configured to do conversions triggered by the Event System to

have regular timing, independent of the application software. DMA may be used for transferring

data from memory locations to DAC data registers.

The DAC has a built-in calibration system to reduce offset and gain error when loading with a

calibration value from software.

PORTB each has one DAC. Notation of this peripheral is DACB.

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8068E–AVR–08/08

XMEGA A3

26. AC - Analog Comparator

26.1 Features

• Four Analog Comparators

• Selectable Power vs. Speed

• Selectable hysteresis

– 0, 20 mV, 50 mV

• Analog Comparator output available on pin

• Flexible Input Selection

– All pins on the port

– Output from the DAC

– Bandgap reference voltage.

– Voltage scaler that can perform a 64-level scaling of the internal VCC voltage.

• Interrupt and event generation on

– Rising edge

– Falling edge

– Toggle

• Window function interrupt and event generation on

– Signal above window

– Signal inside window

– Signal below window

26.2 Overview

XMEGA A3 features four Analog Comparators (AC). An Analog Comparator compares two volt-

ages, and the output indicates which input is largest. The Analog Comparator may be configured

to give interrupt requests and/or events upon several different combinations of input change.

Both hysteresis and propagation delays may be adjusted in order to find the optimal operation

for each application.

A wide range of input selection is available, both external pins and several internal signals can

be used.

The Analog Comparators are always grouped in pairs (AC0 and AC1) on each analog port. They

have identical behavior but separate control registers.

Optionally, the state of the comparator is directly available on a pin.

PORTA and PORTB each has one AC pair. Notations are ACA and ACB, respectively.

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XMEGA A3

Figure 26-1. Analog comparator overview

Pin inputs

Internal inputs

+

-

Pin 0 output

Interrupts

AC0

Pin inputs

Internal inputs

VCC scaled

Interrupt

sensitivity

control

Events

Pin inputs

Internal inputs

+

-

AC1

Pin inputs

Internal inputs

VCC scaled

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8068E–AVR–08/08

XMEGA A3

26.3 Input Selection

The Analog comparators have a very flexible input selection and the two comparators grouped

in a pair may be used to realize a window function. One pair of analog comparators is shown in

Figure 26-1 on page 44.

• Input selection from pin

– Pin 0, 1, 2, 3, 4, 5, 6 selectable to positive input of analog comparator

– Pin 0, 1, 3, 5, 7 selectable to negative input of analog comparator

• Internal signals available on positive analog comparator inputs

– Output from 12-bit DAC

• Internal signals available on negative analog comparator inputs

– 64-level scaler of the VCC, available on negative analog comparator input

– Bandgap voltage reference

• Output from 12-bit DAC

26.4 Window Function

The window function is realized by connecting the external inputs of the two analog comparators

in a pair as shown in Figure 26-2.

Figure 26-2. Analog comparator window function

+

AC0

Upper limit of window

-

Interrupts

Events

Interrupt

sensitivity

control

Input signal

+

AC1

Lower limit of window

-

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XMEGA A3

27. OCD - On-chip Debug

27.1 Features

• Complete Program Flow Control

– Go, Stop, Reset, Step into, Step over, Step out, Run-to-Cursor

• Debugging on C and high-level language source code level

• Debugging on Assembler and disassembler level

• 1 dedicated program address or source level breakpoint for AVR Studio / debugger

• 4 Hardware Breakpoints

• Unlimited Number of User Program Breakpoints

• Unlimited Number of User Data Breakpoints, with break on:

– Data location read, write or both read and write

– Data location content equal or not equal to a value

– Data location content is greater or less than a value

– Data location content is within or outside a range

– Bits of a data location are equal or not equal to a value

• Non-Intrusive Operation

– No hardware or software resources in the device are used

• High Speed Operation

– No limitation on debug/programming clock frequency versus system clock frequency

27.2 Overview

The XMEGA A3 has a powerful On-Chip Debug (OCD) system that - in combination with Atmel’s

development tools - provides all the necessary functions to debug an application. It has support

for program and data breakpoints, and can debug an application from C and high level language

source code level, as well as assembler and disassembler level. It has full Non-Intrusive Opera-

tion and no hardware or software resources in the device are used. The ODC system is

accessed through an external debugging tool which connects to the JTAG or PDI physical inter-

faces. Refer to ”Program and Debug Interfaces” on page 47.

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8068E–AVR–08/08

XMEGA A3

28. Program and Debug Interfaces

28.1 Features

• PDI - Program and Debug Interface (Atmel proprietary 2-pin interface)

• JTAG Interface (IEEE std. 1149.1 compliant)

• Boundary-scan capabilities according to the IEEE Std. 1149.1 (JTAG)

• Access to the OCD system

• Programming of Flash, EEPROM, Fuses and Lock Bits

28.2 Overview

The programming and debug facilities are accessed through the JTAG and PDI physical inter-

faces. The PDI physical uses one dedicated pin together with the Reset pin, and no general

purpose pins are used. JTAG uses four general purpose pins on PORTB.

28.3 JTAG interface

The JTAG physical layer handles the basic low-level serial communication over four I/O lines

named TMS, TCK, TDI, and TDO. It complies to the IEEE Std. 1149.1 for test access port and

boundary scan.

28.4 PDI - Program and Debug Interface

The PDI is an Atmel proprietary protocol for communication between the microcontroller and

Atmel’s development tools.

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XMEGA A3

29. Pinout and Pin Functions

The pinout of XMEGA A3 is shown in ”For packaging information, see ”Packaging information”

on page 66.” on page 2. In addition to general I/O functionality, each pin may have several func-

tion. This will depend on which peripheral is enabled and connected to the actual pin. Only one

of the alternate pin functions can be used at time.

29.1 Alternate Pin Function Description

The tables below show the notation for all pin functions available and describe its function.

29.1.1

Operation/Power Supply

VCC

Digital supply voltage

Analog supply voltage

Ground

AVCC

GND

29.1.2

29.1.3

Port Interrupt functions

SYNC

Port pin with full synchronous and limited asynchronous interrupt function

Port pin with full synchronous and full asynchronous interrupt function

ASYNC

Analog functions

ACn

Analog Comparator input pin n

Analog Comparator 0 Output

AC0OUT

ADCn

DACn

AREF

Analog to Digital Converter input pin n

Digital to Analog Converter output pin n

Analog Reference input pin

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8068E–AVR–08/08

XMEGA A3

29.1.4

29.1.5

Timer/Counter and AWEX functions

OCnx

OCxn

Output Compare Channel x for Timer/Counter n

Inverted Output Compare Channel x for Timer/Counter n

Communication functions

SCL

Serial Clock for TWI

SDA

Serial Data for TWI

SCLIN

SCLOUT

SDAIN

SDAOUT

XCKn

RXDn

TXDn

SS

Serial Clock In for TWI when external driver interface is enabled

Serial Clock Out for TWI when external driver interface is enabled

Serial Data In for TWI when external driver interface is enabled

Serial Data Out for TWI when external driver interface is enabled

Transfer Clock for USART n

Receiver Data for USART n

Transmitter Data for USART n

Slave Select for SPI

MOSI

MISO

SCK

Master Out Slave In for SPI

Master In Slave Out for SPI

Serial Clock for SPI

29.1.6

29.1.7

Oscillators, Clock and Event

TOSCn

XTALn

Timer Oscillator pin n

Input/Output for inverting Oscillator pin n

Peripheral Clock Output

CLKOUT

EVOUT

Event Channel 0 Output

Debug/System functions

RESET

PDI_CLK

PDI_DATA

TCK

Reset pin

Program and Debug Interface Clock pin

Program and Debug Interface Data pin

JTAG Test Clock

TDI

JTAG Test Data In

TDO

JTAG Test Data Out

TMS

JTAG Test Mode Select

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8068E–AVR–08/08

XMEGA A3

29.2 Alternate Pin Functions

The tables below show the main and alternate pin functions for all pins on each port. They also

show which peripheral that makes use of or enables the alternate pin function.

Table 29-1. Port A - Alternate functions

ADAA

GAINPOS

ADCA

GAINNEG

PORT A

GND

AVCC

PA0

PIN #

60

61

62

63

64

1

INTERRUPT

ADCA POS

ADCA NEG

ACA POS

ACA NEG

ACA OUT

REFA

SYNC

ADC0

ADC1

ADC2

ADC3

ADC4

ADC5

ADC6

ADC7

ADC0

ADC1

ADC2

ADC3

ADC0

ADC1

ADC2

ADC3

ADC4

ADC5

ADC6

ADC7

AC0

AC1

AC2

AC3

AC4

AC5

AC6

AC0

AC1

AREFA

PA1

PA2

SYNC/ASYNC

SYNC

PA3

AC3

AC5

AC7

PA4

2

SYNC

ADC4

ADC5

ADC6

ADC7

PA5

3

SYNC

PA6

4

SYNC

PA7

5

SYNC

AC0 OUT

Table 29-2. Port B - Alternate functions

ADCB

POS

ADCB

NEG

ADCB

GAINPOS

ADCB

GAINNEG

PORT B

PB0

PIN #

6

INTERRUPT

SYNC

ACB POS

ACB NEG

ACB OUT

DACB

REFB

JTAG

ADC0

ADC1

ADC2

ADC3

ADC4

ADC5

ADC6

ADC7

ADC0

ADC1

ADC2

ADC3

ADC0

ADC1

ADC2

ADC3

ADC4

ADC5

ADC6

ADC7

AC0

AC1

AC2

AC3

AC4

AC5

AC6

AC0

AC1

AREFB

PB1

6

SYNC

PB2

8

SYNC/ASYNC

SYNC

DAC0

DAC1

PB3

9

AC3

AC5

AC7

PB4

10

11

12

13

14

15

SYNC

ADC4

ADC5

ADC6

ADC7

TMS

TDI

PB5

SYNC

PB6

SYNC

TCK

TDO

PB7

SYNC

AC0 OUT

GND

VCC

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8068E–AVR–08/08

XMEGA A3

Table 29-3. Port C - Alternate functions

PORT C

PIN #

INTERRUPT

TCC0

OC0A

OC0B

OC0C

OC0D

AWEXC

OC0A

OC0B

OC0C

OC0D

TCC1

USARTC0

USARTC1

SPIC

TWIC

SDA

SCL

CLOCKOUT

EVENTOUT

PC0

16

SYNC

PC1

17

SYNC

XCK0

RXD0

TXD0

PC2

18

SYNC/ASYNC

SYNC

PC3

19

PC4

20

SYNC

OC1A

OC1B

SS

PC5

21

SYNC

XCK1

RXD1

TXD1

MOSI

MISO

SCK

PC6

22

SYNC

PC7

23

SYNC

CLKOUT

EVOUT

GND

VCC

24

25

Table 29-4. Port D - Alternate functions

PORT D

PIN #

INTERRUPT

TCD0

OC0A

OC0B

OC0C

OC0D

TCD1

USARTD0

USARTD1

SPID

CLOCKOUT

EVENTOUT

PD0

26

SYNC

PD1

27

SYNC

XCK0

RXD0

TXD0

PD2

28

SYNC/ASYNC

SYNC

PD3

29

PD4

30

SYNC

OC1A

OC1B

SS

PD5

31

SYNC

XCK1

RXD1

TXD1

MOSI

MISO

SCK

PD6

32

SYNC

PD7

33

SYNC

CLKOUT

EVOUT

GND

VCC

34

35

Table 29-5. Port E - Alternate functions

PORT E

PIN #

INTERRUPT

TCE0

OC0A

OC0B

OC0C

OC0D

TCE1

USARTE0

USARTE1

SPIE

TWIE

CLOCKOUT

EVENTOUT

TOSC

PE0

36

SYNC

SDA

SCL

PE1

37

SYNC

XCK0

RXD0

TXD0

PE2

38

SYNC/ASYNC

SYNC

PE3

39

PE4

40

SYNC

OC1A

OC1B

SS

PE5

41

SYNC

XCK1

RXD1

TXD1

MOSI

MISO

SCK

PE6

42

SYNC

TOSC1

PE7

43

SYNC

CLKOUT

EVOUT

GND

VCC

44

45

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8068E–AVR–08/08

XMEGA A3

Table 29-6. Port F - Alternate functions

PORT F

PIN #

INTERRUPT

TCF0

OC0A

OC0B

OC0C

OC0D

USARTF0

PF0

46

SYNC

PF1

47

SYNC

XCK0

RXD0

TXD0

PF2

48

SYNC/ASYNC

SYNC

PF3

49

PF4

50

SYNC

PF5

51

SYNC

PF6

54

SYNC

PF7

55

SYNC

GND

VCC

52

53

Table 29-7. Port R - Alternate functions

PORT R

PDI

PIN #

56

INTERRUPT

PROGR

XTAL

PDI_DATA

PDI_CLOCK

RESET

PRO

57

58

SYNC

XTAL2

XTAL1

PR1

59

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XMEGA A3

30. Peripheral Module Address Map

The address maps show the base address for each peripheral and module in XMEGA A3. For

complete register description and summary for each peripheral module, refer to the XMEGA A

Manual.

Base Address

Name

Description

0x0000

0x0010

0x0014

0x0018

0x001C

0x0030

0x0040

0x0048

0x0050

0x0060

0x0068

0x0070

0x0078

0x0080

0x0090

0x00A0

0x00B0

0x00C0

0x0100

0x0180

0x01C0

0x0200

0x0240

0x0320

0x0380

0x0390

0x0400

0x0480

0x04A0

0x0600

0x0620

0x0640

0x0660

0x0680

0x06A0

0x07E0

0x0800

0x0840

0x0880

0x0890

0x08A0

0x08B0

0x08C0

0x08F8

0x0900

0x0940

0x0990

0x09A0

0x09B0

0x09C0

0x0A00

0x0A40

0x0A80

0x0A90

0x0AA0

0x0AB0

0x0AC0

0x0B00

0x0B90

0x0BA0

GPIO

General Purpose IO Registers

Virtual Port 0

Virtual Port 1

Virtual Port 2

CPU

Clock Control

Sleep Controller

Oscillator Control

DFLL for the 32 MHz Internal RC Oscillator

DFLL for the 2 MHz RC Oscillator

Power Reduction

Reset Controller

Watch-Dog Timer

MCU Control

Programmable MUltilevel Interrupt Controller

Port Configuration

AES Module

DMA Controller

VPORT0

VPORT1

VPORT2

VPORT3

CPU

CLK

SLEEP

OSC

DFLLRC32M

DFLLRC2M

PR

RST

WDT

MCU

PMIC

PORTCFG

AES

DMA

EVSYS

NVM

ADCA

ADCB

DACB

Event System

Non Volatile Memory (NVM) Controller

Analog to Digital Converter on port A

Analog to Digital Converter on port B

Digital to Analog Converter on port B

Analog Comparator pair on port A

Analog Comparator pair on port B

Real Time Counter

Two Wire Interface on port C

Two Wire Interfaceon port E

Port A

Port B

Port C

Port D

Port E

Port F

Port R

ACA

ACB

RTC

TWIC

TWIE

PORTA

PORTB

PORTC

PORTD

PORTE

PORTF

PORTR

TCC0

Timer/Counter 0 on port C

Timer/Counter 1 on port C

Advanced Waveform Extension on port C

High Resolution Extension on port C

USART 0 on port C

TCC1

AWEXC

HIRESC

USARTC0

USARTC1

SPIC

IRCOM

TCD0

TCD1

HIRESD

USARTD0

USARTD1

SPID

TCE0

TCE1

AWEXE

HIRESE

USARTE0

USARTE1

SPIE

TCF0

HIRESF

USARTF0

USART 1 on port C

Serial Peripheral Interface on port C

Infrared Communication Module

Timer/Counter 0 on port D

Timer/Counter 1 on port D

High Resolution Extension on port D

USART 0 on port D

USART 1 on port D

Serial Peripheral Interface on port D

Timer/Counter 0 on port E

Timer/Counter 1 on port E

Advanced Waveform Extensionon port E

High Resolution Extension on port E

USART 0 on port E

USART 1 on oirt E

Serial Peripheral Interface on port E

Timer/Counter 0 on port F

High Resolution Extension on port F

USART 0 on port F

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XMEGA A3

31. Interrupt Vector Summary.

31.1 USART Interrupt vectors

Table 31-1. USART Interrupt vectors

Offset

Source

RXC

Interrupt Description

0

2

4

USART Receive Complete Interrupt vector offset

USART Data Register Empty Interrupt vector offset

USART Transmit Complete Interrupt vector offset

DRE

TXC

31.2 Timer/Counter Interrupt vectors

Table 31-2. Timer/Counter Interrupt vectors

Offset

Source

OVF

Interrupt Description

0

Timer/Counter Overflow/Underflow Interrupt vector offset

Timer/Counter Error Interrupt vector offset

2

4

ERR

CCA

Timer/Counter Compare or Capture Channel A Interrupt vector offset

Timer/Counter Compare or Capture Channel B Interrupt vector offset

Timer/Counter Compare or Capture Channel C Interrupt vector offset

Timer/Counter Compare or Capture Channel D Interrupt vector offset

6

CCB

8

CCC⁽¹⁾

CCD⁽¹⁾

0x0A

Note:

1. Only available on Timer/Counter with 4 Compare or Capture channels 16-bit.

31.3 SPI Interrupt vectors

Table 31-3. SPI Interrupt vectors

Offset

Source

Interrupt Description

0

SPI

SPI Interrupt vector offset

31.4 TWI Interrupt vectors

Table 31-4. TWI Interrupt vectors

Offset

Source

MASTER

SLAVE

Interrupt Description

0

2

TWI Master Interrupt vector offset

TWI Slave Interrupt vector offset

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XMEGA A3

31.5 DMA Interrupt vectors

Table 31-5. DMA Interrupt vectors

Offset

Source

CH0

Interrupt Description

0

2

4

6

DMA Controller Channel 0 Interrupt vector offset

DMA Controller Channel 1 Interrupt vector offset

DMA Controller Channel 2 Interrupt vector offset

DMA Controller Channel 3 Interrupt vector offset

CH1

CH2

CH3

31.6 Crystal Oscillator Failure Interrupt vector

Table 31-6. Crystal Oscillator Failure Interrupt vector

Offset

Source

Interrupt Description

0

OSCF

Crystal Oscillator Failure Interrupt vector (NMI) offset

31.7 RTC Interrupt vectors

Table 31-7. RTC Interrupt vectors

Offset

Source

COMP

PER

Interrupt Description

0

2

Real Time Counter Compare Match Interrupt vector offset

Real Time Counter Period Interrupt vector offset

31.8 AES Interrupt vector

Table 31-8. AES Interrupt vector

Offset

Source

Interrupt Description

0

AES

AES Interrupt vector offset

31.9 NVM Interrupt vectors

Table 31-9. NVM Interrupt vectors

Offset

Source

SPM

EE

Interrupt Description

0

2

Non-Volatile Memory SPM Interrupt level vector offset

Non-Volatile Memory EEPROM Interrupt level vector offset

55

8068E–AVR–08/08

XMEGA A3

31.10 Analog Comparator Interrupt vectors

Table 31-10. Analog Comparator Interrupt vectors

Offset

Source

COMP0

COMP1

WINDOW

Interrupt Description

0

2

4

Analog Comparator 0 Interrupt vector offset

Analog Comparator 1 Interrupt vector offset

Analog Comparator Window Interrupt vector offset

31.11 ADC Interrupt vectors

Table 31-11. Analog to Digital Converter Interrupt vectors

Offset

Source

CH0

Interrupt Description

0

2

4

6

Analog to Digital Converter Channel 0 Interrupt vector offset

Analog to Digital Converter Channel 1 Interrupt vector offset

Analog to Digital Converter Channel 2 Interrupt vector offset

Analog to Digital Converter Channel 3 Interrupt vector offset

CH1

CH2

CH3

31.12 PORTS Interrupt vectors

Table 31-12. Ports Interrupt vectors

Offset

Source

INT0

Interrupt Description

0

2

Port Interrupt vector 0 offset

Port Interrupt vector 1 offset

INT1

56

8068E–AVR–08/08

XMEGA A3

32. Instruction Set Summary

Mnemonics

Operands

Description

Operation

Flags

#Clocks

Arithmetic and Logic Instructions

ADD

ADC

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd

Add without Carry

Rd

←

Rd + Rr

Z,C,N,V,S,H

Z,C,N,V,S

Z,C,N,V,S,H

Z,C,N,V,S

Z,N,V,S

Z,C,N,V,S

Z,C,N,V,S,H

Z,N,V,S

None

1

2

1

2

1

2

1/2

Add with Carry

Rd + Rr + C

Rd + 1:Rd + K

Rd - Rr

ADIW

SUB

Add Immediate to Word

Subtract without Carry

Subtract Immediate

Subtract with Carry

Subtract Immediate with Carry

Subtract Immediate from Word

Logical AND

SUBI

SBC

Rd - K

Rd - Rr - C

Rd - K - C

Rd + 1:Rd - K

Rd • Rr

SBCI

SBIW

AND

ANDI

OR

Rd + 1:Rd

Rd

Logical AND with Immediate

Logical OR

Rd

Rd • K

Rd

Rd v Rr

ORI

Logical OR with Immediate

Exclusive OR

Rd

Rd v K

EOR

COM

NEG

SBR

Rd

Rd ⊕ Rr

One’s Complement

Two’s Complement

Set Bit(s) in Register

Clear Bit(s) in Register

Increment

Rd

$FF - Rd

Rd

$00 - Rd

Rd,K

Rd

Rd v K

CBR

INC

Rd

Rd • ($FFh - K)

Rd + 1

Rd

DEC

TST

Rd

Decrement

Rd

Rd - 1

Rd

Test for Zero or Minus

Clear Register

Rd

Rd • Rd

CLR

Rd

Rd ⊕ Rd

SER

Rd

Set Register

Rd

$FF

MUL

MULS

MULSU

FMUL

FMULS

FMULSU

DES

Rd,Rr

K

Multiply Unsigned

R1:R0

Rd x Rr (UU)

Rd x Rr (SS)

Rd x Rr (SU)

Rd x Rr<<1 (UU)

Rd x Rr<<1 (SS)

Rd x Rr<<1 (SU)

Z,C

Multiply Signed

Z,C

Multiply Signed with Unsigned

Fractional Multiply Unsigned

Fractional Multiply Signed

Fractional Multiply Signed with Unsigned

Data Encryption

Z,C

if (H = 0) then R15:R0

else if (H = 1) then R15:R0

←

Encrypt(R15:R0, K)

Decrypt(R15:R0, K)

Branch Instructions

RJMP

IJMP

k

Relative Jump

PC

←

PC + k + 1

None

2

Indirect Jump to (Z)

PC(15:0)

PC(21:16)

←

Z,

0

EIJMP

Extended Indirect Jump to (Z)

PC(15:0)

PC(21:16)

←

Z,

EIND

None

2

JMP

k

Jump

PC

←

k

None

3

RCALL

ICALL

Relative Call Subroutine

Indirect Call to (Z)

PC + k + 1

2 / 3⁽¹⁾

PC(15:0)

PC(21:16)

←

Z,

0

EICALL

Extended Indirect Call to (Z)

PC(15:0)

PC(21:16)

←

Z,

EIND

None

3⁽¹⁾

57

8068E–AVR–08/08

XMEGA A3

Mnemonics

CALL

RET

Operands

Description

Operation

Flags

None

I

#Clocks

3 / 4⁽¹⁾

4 / 5⁽¹⁾

1 / 2 / 3

1

k

call Subroutine

PC

←

k

Subroutine Return

STACK

PC + 2 or 3

RETI

Interrupt Return

PC

CPSE

CP

Rd,Rr

Compare, Skip if Equal

Compare

if (Rd = Rr) PC

None

Z,C,N,V,S,H

None

Rd,Rr

Rd - Rr

CPC

Rd,Rr

Compare with Carry

Rd - Rr - C

1

CPI

Rd,K

Compare with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Rd - K

1

SBRC

SBRS

SBIC

Rr, b

if (Rr(b) = 0) PC

if (Rr(b) = 1) PC

if (I/O(A,b) = 0) PC

If (I/O(A,b) =1) PC

if (SREG(s) = 1) then PC

if (SREG(s) = 0) then PC

if (Z = 1) then PC

if (Z = 0) then PC

if (C = 1) then PC

if (C = 0) then PC

if (C = 1) then PC

if (N = 1) then PC

if (N = 0) then PC

if (N ⊕ V= 0) then PC

if (N ⊕ V= 1) then PC

if (H = 1) then PC

if (H = 0) then PC

if (T = 1) then PC

if (T = 0) then PC

if (V = 1) then PC

if (V = 0) then PC

if (I = 1) then PC

if (I = 0) then PC

←

PC + 2 or 3

PC + k + 1

1 / 2 / 3

2 / 3 / 4

1 / 2

Rr, b

A, b

s, k

k

SBIS

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

BRVC

BRIE

1 / 2

k

Branch if Not Equal

1 / 2

k

Branch if Carry Set

1 / 2

k

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

1 / 2

k

1 / 2

k

1 / 2

k

Branch if Minus

1 / 2

k

Branch if Plus

1 / 2

k

Branch if Greater or Equal, Signed

Branch if Less Than, Signed

Branch if Half Carry Flag Set

Branch if Half Carry Flag Cleared

Branch if T Flag Set

1 / 2

k

1 / 2

k

1 / 2

k

1 / 2

k

1 / 2

k

Branch if T Flag Cleared

Branch if Overflow Flag is Set

Branch if Overflow Flag is Cleared

Branch if Interrupt Enabled

Branch if Interrupt Disabled

1 / 2

k

1 / 2

k

1 / 2

k

1 / 2

BRID

k

1 / 2

Data Transfer Instructions

MOV

MOVW

LDI

Rd, Rr

Rd, K

Rd, k

Copy Register

Rd

Rd+1:Rd

Rd

←

Rr

None

1

Copy Register Pair

Load Immediate

Rr+1:Rr

1

K

1

LDS

LD

Load Direct from data space

Load Indirect

Rd

(k)

(X)

2⁽¹⁾⁽²⁾

1⁽¹⁾⁽²⁾

Rd, X

Rd, X+

Rd

LD

Load Indirect and Post-Increment

Rd

X

←

(X)

X + 1

LD

Rd, -X

Load Indirect and Pre-Decrement

X ← X - 1,

Rd ← (X)

←

X - 1

(X)

None

2⁽¹⁾⁽²⁾

LD

Rd, Y

Load Indirect

Rd ← (Y)

←

(Y)

None

1⁽¹⁾⁽²⁾

Rd, Y+

Load Indirect and Post-Increment

Rd

Y

←

(Y)

Y + 1

58

8068E–AVR–08/08

XMEGA A3

Mnemonics

Operands

Description

Operation

Flags

#Clocks

LD

Rd, -Y

Load Indirect and Pre-Decrement

Y

Rd

←

Y - 1

(Y)

None

2⁽¹⁾⁽²⁾

LDD

LD

Rd, Y+q

Rd, Z

Load Indirect with Displacement

Load Indirect

Rd

←

(Y + q)

(Z)

None

2⁽¹⁾⁽²⁾

1⁽¹⁾⁽²⁾

LD

Rd, Z+

Load Indirect and Post-Increment

Rd

Z

←

(Z),

Z+1

LD

Rd, -Z

Load Indirect and Pre-Decrement

Z

Rd

←

Z - 1,

(Z)

None

2⁽¹⁾⁽²⁾

LDD

STS

ST

Rd, Z+q

k, Rr

Load Indirect with Displacement

Store Direct to Data Space

Store Indirect

Rd

(k)

(X)

←

(Z + q)

Rd

None

2⁽¹⁾⁽²⁾

2⁽¹⁾

X, Rr

Rr

1⁽¹⁾

ST

X+, Rr

Store Indirect and Post-Increment

(X)

X

←

Rr,

X + 1

1⁽¹⁾

ST

-X, Rr

Store Indirect and Pre-Decrement

X

(X)

←

X - 1,

Rr

None

2⁽¹⁾

ST

Y, Rr

Store Indirect

(Y)

←

Rr

None

1⁽¹⁾

Y+, Rr

Store Indirect and Post-Increment

(Y)

Y

←

Rr,

Y + 1

ST

-Y, Rr

Store Indirect and Pre-Decrement

Y

(Y)

←

Y - 1,

Rr

None

2⁽¹⁾

STD

ST

Y+q, Rr

Z, Rr

Store Indirect with Displacement

Store Indirect

(Y + q)

(Z)

←

Rr

None

2⁽¹⁾

1⁽¹⁾

ST

Z+, Rr

Store Indirect and Post-Increment

(Z)

Z

←

Rr

Z + 1

ST

-Z, Rr

Store Indirect and Pre-Decrement

Store Indirect with Displacement

Load Program Memory

Z

(Z + q)

R0

←

Z - 1

Rr

None

2⁽¹⁾

3

STD

LPM

Z+q,Rr

(Z)

Rd, Z

Load Program Memory

Rd

(Z)

3

Rd, Z+

Load Program Memory and Post-Increment

Rd

Z

←

(Z),

Z + 1

3

ELPM

Extended Load Program Memory

R0

Rd

←

(RAMPZ:Z)

None

3

Rd, Z

Rd, Z+

Extended Load Program Memory and Post-

Increment

Rd

Z

←

(RAMPZ:Z),

Z + 1

SPM

Store Program Memory

(RAMPZ:Z)

←

R1:R0

None

-

Z+

Store Program Memory and Post-Increment

by 2

(RAMPZ:Z)

Z

←

R1:R0,

Z + 2

IN

Rd, A

A, Rr

Rr

In From I/O Location

Out To I/O Location

Rd

I/O(A)

STACK

Rd

←

I/O(A)

Rr

None

1

OUT

PUSH

POP

1

Push Register on Stack

Pop Register from Stack

Rr

1⁽¹⁾

2⁽¹⁾

Rd

STACK

Bit and Bit-test Instructions

LSL

LSR

Rd

Logical Shift Left

Logical Shift Right

Rd(n+1)

Rd(0)

C

←

Rd(n),

0,

Rd(7)

Z,C,N,V,H

Z,C,N,V

1

Rd(n)

Rd(7)

C

←

Rd(n+1),

0,

Rd(0)

59

8068E–AVR–08/08

XMEGA A3

Mnemonics

Operands

Description

Operation

Flags

#Clocks

ROL

Rd

Rotate Left Through Carry

Rd(0)

Rd(n+1)

C

←

C,

Rd(n),

Rd(7)

Z,C,N,V,H

1

ROR

Rd

Rotate Right Through Carry

Rd(7)

Rd(n)

C

←

C,

Z,C,N,V

1

Rd(n+1),

Rd(0)

ASR

SWAP

BSET

BCLR

SBI

Rd

Arithmetic Shift Right

Swap Nibbles

Rd(n)

←

↔

←

Rd(n+1), n=0..6

Z,C,N,V

1

Rd

Rd(3..0)

Rd(7..4)

None

s

Flag Set

SREG(s)

1

SREG(s)

s

Flag Clear

SREG(s)

0

SREG(s)

A, b

Rr, b

Rd, b

Set Bit in I/O Register

Clear Bit in I/O Register

Bit Store from Register to T

Bit load from T to Register

Set Carry

I/O(A, b)

1

None

CBI

I/O(A, b)

0

None

BST

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

SEI

T

Rr(b)

T

1

T

Rd(b)

C

N

Z

None

C

N

Z

Clear Carry

0

Set Negative Flag

1

Clear Negative Flag

Set Zero Flag

0

1

Clear Zero Flag

Z

0

Z

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Two’s Complement Overflow

Clear Two’s Complement Overflow

Set T in SREG

I

1

I

CLI

I

0

I

SES

CLS

SEV

CLV

SET

CLT

S

1

S

V

T

S

0

V

1

V

0

T

1

Clear T in SREG

T

0

T

SEH

CLH

Set Half Carry Flag in SREG

Clear Half Carry Flag in SREG

H

1

H

0

MCU Control Instructions

BREAK

NOP

Break

(See specific descr. for BREAK)

None

1

No Operation

Sleep

SLEEP

WDR

(see specific descr. for Sleep)

Watchdog Reset

(see specific descr. for WDR)

Notes: 1. Cycle times for Data memory accesses assume internal memory accesses, and are not valid

for accesses via the external RAM interface.

2. One extra cycle must be added when accessing Internal SRAM.

60

8068E–AVR–08/08

XMEGA A3

33. Electrical Characteristics - TBD

33.1 Absolute Maximum Ratings*

*NOTICE:

Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect

device reliability.

Operating Temperature....................................-55⋅C to +125⋅C

Storage Temperature.......................................-65⋅C to +150⋅C

Voltage on any Pin with respect to Ground..-0.5V to V_CC+0.5V

Maximum Operating Voltage ............................................ 3.6V

DC Current per I/O Pin ............................................... 20.0 mA

DC Current V_CCand GND Pins................................ 200.0 mA

33.2 DC Characteristics

T_A= -40⋅C to 85⋅C, V_CC= 1.6V to 3.6V (unless otherwise noted)

Symbol

V_IL

Parameter

Condition

Min.

Typ.

Max.

Units

Input Low Voltage, except XTAL1 pin

Input Low Voltage, XTAL1 pins

Input High Voltage, except XTAL1 pin

Input High Voltage, XTAL1 pin

Output Low Voltage

V

V_IL1

V_IH

V_IH1

V_OL

V_OH

Output High Voltage

Input Leakage

Current I/O Pin

I_IL

µA

Input Leakage

Current I/O Pin

I_IH

R_RST

R_PU

Reset Pull-up Resistor

I/O Pin Pull-up Resistor

kΩ

Active 32 MHz

Active 20 MHz

Active 8MHz

mA

µA

Power Supply Current

Power-down mode

Idle 32 MHz

I_CC

Idle 20 MHz

WDT disabled

WDT slow sampling

WDT fast sampling

µA

Note:

1. “Max” means the highest value where the pin is guaranteed to be read as low

2. “Min” means the lowest value where the pin is guaranteed to be read as high

61

8068E–AVR–08/08

XMEGA A3

33.3 Speed

The maximum frequency of the XMEGA A3 devices is depending on VCC. As shown in Figure

33-1 on page 62 the Frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V.

Figure 33-1. Maximum Frequency vs. Vcc

MHz

32

Safe Operating Area

12

V

1.6

1.8

2.7

3.6

62

8068E–AVR–08/08

XMEGA A3

33.4 ADC Characteristics – TBD

Table 33-1. ADC Characteristics

Symbol

Parameter

Condition

Min

Typ

Max

Units

LSB

µs

Resolution

Integral Non-Linearity (INL)

Differential Non-Linearity (DNL)

Gain Error

Offset Error

Conversion Time

ADC Clock Frequency

DC Supply Voltage

Source Impedance

Start-up time

MHz

mA

Ω

µs

AVCC

Analog Supply Voltage

VCC - 0.3

VCC + 0.3

V

Table 33-2. ADC Gain Stage Characteristics

Symbol

Parameter

Condition

Min

Typ

Max

Units

Gain

Input Capacitance

Offset Error

Gain Error

pF

mV

%

Signal Range

DC Supply Current

V

mA

# clk

cycles

Start-up time

63

8068E–AVR–08/08

XMEGA A3

33.5 DAC Characteristics – TBD

Table 33-3. DAC Characteristics

Symbol

Parameter

Condition

Min

Typ

Max

Units

LSB

V

Resolution

Integral Non-Linearity (INL)

Differential Non-Linearity (DNL)

Gain Error

Offset Error

Calibrated Gain/Offset Error

Output Range

Output Settling Time

Output Capacitance

Output Resistance

Reference Input Voltage

Reference Input Capacitance

Reference Input Resistance

Current Consumption

Start-up time

µs

nF

kΩ

V

pF

kΩ

mA

µs

33.6 Analog Comparator Characteristics – TBD

Table 33-4. Analog Comparator Characteristics

Symbol

Parameter

Condition

Min

Typ

Max

Units

Offset

mV

No

Hysteresis

Low

High

mV

ns

High Speed mode

Low power mode

High Speed mode

Low power mode

Propagation Delay

Current Consumption

Start-up time

µA

µs

64

8068E–AVR–08/08

XMEGA A3

34. Typical Characteristics - TBD

65

8068E–AVR–08/08

XMEGA A3

35. Packaging information

35.1 64A

PIN 1

B

PIN 1 IDENTIFIER

E1

E

e

D1

D

C

0˚~7˚

A2

A

A1

L

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

–

MAX

1.20

NOM

NOTE

SYMBOL

A

–

A1

A2

D

0.05

0.95

11.75

9.90

11.75

9.90

0.30

0.09

0.45

0.15

1.00

12.00

10.00

12.00

10.00

–

1.05

12.25

D1

E

10.10 Note 2

12.25

Notes:

1. This package conforms to JEDEC reference MS-026, Variation ACB.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable

protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum

plastic body size dimensions including mold mismatch.

E1

B

10.10 Note 2

0.45

C

–

0.20

3. Lead coplanarity is 0.10 mm maximum.

L

–

0.75

e

0.80 TYP

10/5/2001

TITLE

DRAWING NO. REV.

2325 Orchard Parkway

San Jose, CA 95131

44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,

0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

44A

B

R

66

8068E–AVR–08/08

XMEGA A3

35.2 64M1

D

Marked Pin# 1 ID

E

SEATING PLANE

C

A1

TOP VIEW

A

K

0.08

C

L

Pin #1 Corner

SIDE VIEW

D2

Pin #1

Triangle

Option A

1

2

3

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

0.80

–

MAX

1.00

0.05

0.30

9.10

NOM

0.90

0.02

0.25

9.00

NOTE

SYMBOL

E2

Option B

Option C

A

Pin #1

Chamfer

(C 0.30)

A1

b

0.18

8.90

D

D2

E

5.20

8.90

5.40

9.00

5.60

9.10

K

Pin #1

Notch

(0.20 R)

e

b

E2

e

5.20

5.40

0.50 BSC

0.40

5.60

BOTTOM VIEW

L

0.35

1.25

0.45

1.55

K

1.40

1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD.

2. Dimension and tolerance conform to ASMEY14.5M-1994.

Note:

5/25/06

DRAWING NO. REV.

64M1

TITLE

2325 Orchard Parkway

San Jose, CA 95131

64M1, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm,

5.40 mm Exposed Pad, Micro Lead Frame Package (MLF)

G

R

67

8068E–AVR–08/08

XMEGA A3

36. Errata

36.1 All rev.

No known errata.

68

8068E–AVR–08/08

XMEGA A3

37. Datasheet Revision History

37.1 8068E – 08/08

1.

2.

Updated ”Block Diagram” on page 4.

Inserted ”Interrupt Vector Summary.” on page 54.

37.2 8068D – 06/08

37.3 8068C – 06/08

1.

References to External Bus Interface (EBI) removed from ”Features” on page 1.

1.

2.

3.

4.

5.

6.

7.

Updated ”Features” on page 1.

Updated Figure 2-1 on page 2.

Updated ”Overview” on page 3.

Updated Table 7-2 on page 13.

Replaced Figure 24-1 on page 41 by a correct one.

Updated “Features” and ”Overview” on page 42.

Updated all tables in section ”Alternate Pin Functions” on page 50.

37.4 8068B – 06/08

1.

2.

Updated ”Features” on page 1.

Updated ”For packaging information, see ”Packaging information” on page 66.” on page 2 and

”Pinout and Pin Functions” on page 48.

3.

4.

5.

6.

7.

8.

9.

Updated ”Ordering Information” on page 2.

Updated ”Overview” on page 3, included the XMEGA A3 explanation text on page 6.

Added XMEGA A3 Block Diagram, Figure 3-1 on page 4.

Updated AVR CPU ”Overview” on page 6 and Updated Figure 6-1 on page 6.

Updated Event System block diagram, Figure 9-1 on page 16.

Updated ”PMIC - Programmable Multi-level Interrupt Controller” on page 24.

Updated ”AC - Analog Comparator” on page 43.

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10.

11.

12.

13.

14.

Updated ”I/O configuration” on page 26.

Inserted a new Figure 15-1 on page 31.

Updated ”Peripheral Module Address Map” on page 53.

Inserted ”Instruction Set Summary” on page 57.

Added Speed grades in ”Speed” on page 62.

37.5 8068A – 02/08

1.

Initial revision.

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Table of Contents

Features ..................................................................................................... 1

Typical Applications ................................................................................ 1

1

2

3

Ordering Information ............................................................................... 2

Pinout/Block Diagram .............................................................................. 2

Overview ................................................................................................... 3

3.1Block Diagram ...........................................................................................................4

4

Resources ................................................................................................. 5

4.1Recommended reading .............................................................................................5

5

6

Disclaimer ................................................................................................. 5

AVR CPU ................................................................................................... 6

6.1Features ....................................................................................................................6

6.2Overview ....................................................................................................................6

6.3Register File ..............................................................................................................7

6.4ALU - Arithmetic Logic Unit .......................................................................................7

6.5Program Flow ............................................................................................................7

7

Memories .................................................................................................. 8

7.1Features ....................................................................................................................8

7.2Overview ....................................................................................................................8

7.3In-System Programmable Flash Program Memory ...................................................9

7.4Data Memory ...........................................................................................................10

7.5Calibration Row .......................................................................................................12

7.6User Signature Row ................................................................................................12

7.7Flash and EEPROM Page Size ...............................................................................13

8

9

DMAC - Direct Memory Access Controller .......................................... 14

8.1Features ..................................................................................................................14

8.2Overview ..................................................................................................................14

Event System .......................................................................................... 15

9.1Features ..................................................................................................................15

9.2Overview ..................................................................................................................15

10 System Clock and Clock options ......................................................... 17

10.1Features ................................................................................................................17

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10.2Overview ................................................................................................................17

10.3Clock Options ........................................................................................................18

11 Power Management and Sleep Modes ................................................. 20

11.1Features ................................................................................................................20

11.2Overview ................................................................................................................20

11.3Sleep Modes ..........................................................................................................20

12 System Control and Reset .................................................................... 22

12.1Features ................................................................................................................22

12.2Resetting the AVR .................................................................................................22

12.3Reset Sources .......................................................................................................22

12.4WDT - Watchdog Timer .........................................................................................23

13 PMIC - Programmable Multi-level Interrupt Controller ....................... 24

13.1Features ................................................................................................................24

13.2Overview ................................................................................................................24

13.3Interrupt vectors .....................................................................................................24

14 I/O Ports .................................................................................................. 26

14.1Features ................................................................................................................26

14.2Overview ................................................................................................................26

14.3I/O configuration ....................................................................................................26

14.4Input sensing .........................................................................................................29

14.5Port Interrupt ..........................................................................................................29

14.6Alternate Port Functions ........................................................................................29

15 T/C - 16-bits Timer/Counter with PWM ................................................. 30

15.1Features ................................................................................................................30

15.2Overview ................................................................................................................30

16 AWEX - Advanced Waveform Extension ............................................. 32

16.1Features ................................................................................................................32

16.2Overview ................................................................................................................32

17 Hi-Res - High Resolution Extension ..................................................... 33

17.1Features ................................................................................................................33

17.2Overview ................................................................................................................33

18 RTC - Real-Time Counter ....................................................................... 34

18.1Features ................................................................................................................34

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18.2Overview ................................................................................................................34

19 TWI - Two Wire Interface ....................................................................... 35

19.1Features ................................................................................................................35

19.2Overview ................................................................................................................35

20 SPI - Serial Peripheral Interface ............................................................ 36

20.1Features ................................................................................................................36

20.2Overview ................................................................................................................36

21 USART ..................................................................................................... 37

21.1Features ................................................................................................................37

21.2Overview ................................................................................................................37

22 IRCOM - IR Communication Module ..................................................... 38

22.1Features ................................................................................................................38

22.2Overview ................................................................................................................38

23 Crypto Engine ......................................................................................... 39

23.1Features ................................................................................................................39

23.2Overview ................................................................................................................39

24 ADC - 12-bit Analog to Digital Converter ............................................. 40

24.1Features ................................................................................................................40

24.2Overview ................................................................................................................40

25 DAC - 12-bit Digital to Analog Converter ............................................. 42

25.1Features ................................................................................................................42

25.2Overview ................................................................................................................42

26 AC - Analog Comparator ....................................................................... 43

26.1Features ................................................................................................................43

26.2Overview ................................................................................................................43

26.3Input Selection .......................................................................................................45

26.4Window Function ...................................................................................................45

27 OCD - On-chip Debug ............................................................................ 46

27.1Features ................................................................................................................46

27.2Overview ................................................................................................................46

28 Program and Debug Interfaces ............................................................. 47

28.1Features ................................................................................................................47

28.2Overview ................................................................................................................47

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28.3JTAG interface .......................................................................................................47

28.4PDI - Program and Debug Interface ......................................................................47

29 Pinout and Pin Functions ...................................................................... 48

29.1Alternate Pin Function Description ........................................................................48

29.2Alternate Pin Functions .........................................................................................50

30 Peripheral Module Address Map .......................................................... 53

31 Interrupt Vector Summary. .................................................................... 54

31.1USART Interrupt vectors .......................................................................................54

31.2Timer/Counter Interrupt vectors .............................................................................54

31.3SPI Interrupt vectors ..............................................................................................54

31.4TWI Interrupt vectors .............................................................................................54

31.5DMA Interrupt vectors ............................................................................................55

31.6Crystal Oscillator Failure Interrupt vector ..............................................................55

31.7RTC Interrupt vectors ............................................................................................55

31.8AES Interrupt vector ..............................................................................................55

31.9NVM Interrupt vectors ............................................................................................55

31.10Analog Comparator Interrupt vectors ..................................................................56

31.11ADC Interrupt vectors ..........................................................................................56

31.12PORTS Interrupt vectors .....................................................................................56

32 Instruction Set Summary ....................................................................... 57

33 Electrical Characteristics - TBD ............................................................ 61

33.1Absolute Maximum Ratings* .................................................................................61

33.2DC Characteristics .................................................................................................61

33.3Speed ....................................................................................................................62

33.4ADC Characteristics – TBD ...................................................................................63

33.5DAC Characteristics – TBD ...................................................................................64

33.6Analog Comparator Characteristics – TBD ...........................................................64

34 Typical Characteristics - TBD ............................................................... 65

35 Packaging information .......................................................................... 66

35.164A ........................................................................................................................66

35.264M1 ......................................................................................................................67

36 Errata ....................................................................................................... 68

36.1All rev. ....................................................................................................................68

iv

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37 Datasheet Revision History ................................................................... 69

37.18068E – 08/08 .......................................................................................................69

37.28068D – 06/08 .......................................................................................................69

37.38068C – 06/08 .......................................................................................................69

37.48068B – 06/08 .......................................................................................................69

37.58068A – 02/08 .......................................................................................................70

Table of Contents....................................................................................... i

v

8068E–AVR–08/08

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8068E–AVR–08/08


型号：	ATXMEGA256A3B-AUR
厂家：	ATMEL
描述：	RISC Microcontroller, 16-Bit, FLASH, AVR RISC CPU, 32MHz, CMOS, PQFP64, 14 X 14 MM, 1 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, MS-026AEB, TQFP-64 微控制器
文件：	总76页 (文件大小：947K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ATXMEGA256A3B-AUR [ATMEL]

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