ATXMEGA256A3BU-AU [ATMEL]
8/16-bit Atmel XMEGA A3BUMicrocontroller; 8位/ 16位爱特梅尔XMEGA A3BUMicrocontroller
| 型号： | ATXMEGA256A3BU-AU |
| 厂家： | 
ATMEL |
| 描述： | 8/16-bit Atmel XMEGA A3BUMicrocontroller |
| 文件： | 总143页 (文件大小：4630K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8/16-bit Atmel XMEGA A3BUMicrocontroller
ATxmega256A3BU
Features
High-performance, low-power Atmel®AVR®XMEGA® 8/16-bit Microcontroller
Nonvolatile program and data memories
256KBytes of in-system self-programmable flash
8KBytes boot section
4KBytes EEPROM
16KBytes internal SRAM
Peripheral features
Four-channel DMA controller
Eight-channel event system
Seven 16-bit timer/counters
Four timer/counters with four output compare or input capture channels
Three timer/counters with two output compare or input capture channels
High resolution extension on all timer/counters
Advanced waveform extension (AWeX) on one timer/counter
One USB device interface
USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant
32 Endpoints with full configuration flexibility
Six USARTs with IrDA support for one USART
Two two-wire interfaces with dual address match (I2C and SMBus compatible)
Two serial peripheral interfaces (SPIs)
AES and DES crypto engine
CRC-16 (CRC-CCITT) and CRC-32 (IEEE® 802.3) generator
32-bit real time counter (RTC) with separate oscillator and battery backup system
Two sixteen-channel, 12-bit, 2msps Analog to Digital Converters
One two-channel, 12-bit, 1msps Digital to Analog Converter
Four Analog Comparators with window compare function, and current sources
External interrupts on all general purpose I/O pins
Programmable watchdog timer with separate on-chip ultra low power oscillator
QTouch® library support
Capacitive touch buttons, sliders and wheels
Special microcontroller features
Power-on reset and programmable brown-out detection
Internal and external clock options with PLL and prescaler
Programmable multilevel interrupt controller
Five sleep modes
Programming and debug interfaces
JTAG (IEEE 1149.1 compliant) interface, including boundary scan
PDI (Program and Debug Interface)
I/O and packages
47 programmable I/O pins
64-lead TQFP
64-pad QFN
Operating voltage
1.6 – 3.6V
Operating frequency
0 – 12MHz from 1.6V
0 – 32MHz from 2.7V
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1.
Ordering Information
Ordering code
Flash (bytes)
EEPROM (bytes)
SRAM (bytes)
Speed (MHz)
Power supply
Package (1)(2)(3)
Temp.
ATxmega256A3BU-AU
ATxmega256A3BU-AUR (4)
ATxmega256A3BU-MH
ATxmega256A3BU-MHR (4)
256K + 8K
4K
16K
32
1.6 - 3.6V
64A
-40C-85C
256K + 8K
4K
16K
32
1.6 - 3.6V
64M2
Notes:
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.
3. For packaging information, see “Packaging information” on page 67.
4. Tape and reel.
Package type
64A
64-lead, 14 x 14mm body size, 1.0mm body thickness, 0.8mm lead pitch, thin profile plastic quad flat package (TQFP)
64-pad, 9 x 9 x 1.0mm body, lead pitch 0.50mm, 7.65mm exposed pad, quad flat no-lead package (QFN)
64M2
Typical Applications
Industrial control
Factory automation
Building control
Climate control
RF and ZigBee®
USB connectivity
Sensor control
Optical
Low power battery applications
Power tools
HVAC
Board control
Utility metering
White goods
Medical applications
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2.
Pinout/Block Diagram
Figure 2-1. Block diagram and pinout.
Power
Ground
Digital function
Analog function / Oscillators
Programming, debug, test
External clock / Crystal pins
General Purpose I /O
Port R
XOSC
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
GND
VCC
PC0
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PF2
PF1
DATA BUS
3
PF0
OSC/CLK
Control
Internal
oscillators
Watchdog
oscillator
Power
Supervision
4
VCC
GND
TOSC1
TOSC2
PE5
AREF
ADC
Sleep
Controller
Real Time
Counter
Watchdog
Timer
Reset
Controller
5
AC0:1
6
Event System
Controller
Crypto /
CRC
Prog/Debug
Interface
OCD
7
Interrupt
Controller
BUS
matrix
AREF
ADC
8
Internal
references
DMA
Controller
CPU
9
PE4
DAC
AC0:1
JTAG
10
11
12
13
14
15
16
PE3
Battery
Backup
FLASH
EEPROM
SRAM
PE2
PE1
DATA BUS
EVENT ROUTING NETWORK
PE0
VCC
GND
PD7
Port C
Port D
Port E
Port F
Notes:
1. For full details on pinout and pin functions refer to “Pinout and Pin Functions” on page 55.
2. The large center pad underneath the QFN/MLF package should be soldered to ground on the board to ensure good mechanical stability.
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3.
Overview
The Atmel AVR XMEGA is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers based
on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the AVR XMEGA device
achieves CPU throughput approaching one million instructions per second (MIPS) per megahertz, allowing the system
designer to optimize power consumption versus processing speed.
The AVR CPU combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly
connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in a single instruction,
executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many times
faster than conventional single-accumulator or CISC based microcontrollers.
The XMEGA A3BU devices provide the following features: in-system programmable flash with read-while-write
capabilities; internal EEPROM and SRAM; four-channel DMA controller; eight-channel event system and programmable
multilevel interrupt controller; 47 general purpose I/O lines; 32-bit real-time counter (RTC) with battery backup system;
seven flexible 16-bit Timer/Counters with compare modes and PWM; one full speed USB 2.0 interface; six USARTs; two
two-wire serial interfaces (TWIs); two serial peripheral interfaces (SPIs); AES and DES cryptographic engine; two 16-
channel, 12-bit ADCs with programmable gain; one 2-channel 12-bit DAC; four analog comparators (ACs) with window
mode; programmable watchdog timer with separate internal oscillator; accurate internal oscillators with PLL and
prescaler; and programmable brown-out detection.
The program and debug interface (PDI), a fast, two-pin interface for programming and debugging, is available. The
devices also have an IEEE std. 1149.1 compliant JTAG interface, and this can also be used for boundary scan, on-chip
debug and programming.
The XMEGA A3BU devices have five software selectable power saving modes. The idle mode stops the CPU while
allowing the SRAM, DMA controller, event system, interrupt controller, and all peripherals to continue functioning. The
power-down mode saves the SRAM and register contents, but stops the oscillators, disabling all other functions until the
next TWI, USB resume, or pin-change interrupt, or reset. In power-save mode, the asynchronous real-time counter
continues to run, allowing the application to maintain a timer base while the rest of the device is sleeping. In standby
mode, the external crystal oscillator keeps running while the rest of the device is sleeping. This allows very fast startup
from the external crystal, combined with low power consumption. In extended standby mode, both the main oscillator and
the asynchronous timer continue to run. To further reduce power consumption, the peripheral clock to each individual
peripheral can optionally be stopped in active mode and idle sleep mode.
Atmel offers a free QTouch library for embedding capacitive touch buttons, sliders and wheels functionality into AVR
microcontrollers.
The devices are manufactured using Atmel high-density, nonvolatile memory technology. The program flash memory can
be reprogrammed in-system through the PDI or JTAG interfaces. A boot loader running in the device can use any
interface to download the application program to the flash memory. The boot loader software in the boot flash section will
continue to run while the application flash section is updated, providing true read-while-write operation. By combining an
8/16-bit RISC CPU with in-system, self-programmable flash, the AVR XMEGA is a powerful microcontroller family that
provides a highly flexible and cost effective solution for many embedded applications.
All Atmel AVR XMEGA devices are supported with a full suite of program and system development tools, including C
compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits.
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3.1
Block Diagram
Figure 3-1. XMEGA A3BU block diagram.
PR[0..1]
XTAL1
Digital function
Analog function
Programming, debug, test
Oscillator/Crystal/Clock
General purpose I/O
XTAL2
Oscillator
Circuits/
Clock
Watchdog
Oscillator
PORT R (2)
Generation
DATA BUS
SRAM
Watchdog
Timer
PA[0..7]
PORT A (8)
Event System
Controller
Oscillator
Control
VCC
GND
Power
Supervision
POR/BOD &
RESET
ACA
DMA
Controller
Sleep
Controller
ADCA
RESET/
PDI_CLK
AREFA
VCC/10
Int. Refs.
Tempref
AREFB
PDI
Prog/Debug
Controller
BUS Matrix
PDI_DATA
AES
DES
CRC
JTAG
PORT B
OCD
Interrupt
Controller
CPU
ADCB
ACB
NVM Controller
USARTF0
TCF0
PB[0..7]/
JTAG
PORT B (8)
DACB
PF[0..4,6..7]
Flash
EEPROM
IRCOM
DATA BUS
EVENT ROUTING NETWORK
Real Time
Counter
Battery Backup
Controller
VBAT
Power
Supervision
32.768 kHz
XOSC
VBAT
PORT C (8)
PORT D (8)
PORT E (6)
TOSC1
TOSC2
PC[0..7]
PD[0..7]
PE[0..5]
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4.
Resources
A comprehensive set of development tools, application notes and datasheets are available for download on
http://www.atmel.com/avr.
4.1
Recommended reading
Atmel AVR XMEGA AU manual
XMEGA application notes
This device data sheet only contains part specific information with a short description of each peripheral and module. The
XMEGA AU manual describes the modules and peripherals in depth. The XMEGA application notes contain example
code and show applied use of the modules and peripherals.
All documentations are available from www.atmel.com/avr.
5.
Capacitive touch sensing
The Atmel QTouch library provides a simple to use solution to realize touch sensitive interfaces on most Atmel AVR
microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully debounced
reporting of touch keys and includes Adjacent Key Suppression® (AKS®) technology for unambiguous detection of key
events. The QTouch library includes support for the QTouch and QMatrix acquisition methods.
Touch sensing can be added to any application by linking the appropriate Atmel QTouch library for the AVR
microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the
touch sensing API’s to retrieve the channel information and determine the touch sensor states.
The QTouch library is FREE and downloadable from the Atmel website at the following location:
www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the QTouch library user guide -
also available for download from the Atmel website.
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6.
AVR CPU
6.1
Features
8/16-bit, high-performance Atmel AVR RISC CPU
142 instructions
Hardware multiplier
32x8-bit registers directly connected to the ALU
Stack in RAM
Stack pointer accessible in I/O memory space
Direct addressing of up to 16MB of program memory and 16MB of data memory
True 16/24-bit access to 16/24-bit I/O registers
Efficient support for 8-, 16-, and 32-bit arithmetic
Configuration change protection of system-critical features
6.2
6.3
Overview
All Atmel AVR XMEGA devices use the 8/16-bit AVR CPU. The main function of the CPU is to execute the code and
perform all calculations. The CPU is able to access memories, perform calculations, control peripherals, and execute the
program in the flash memory. Interrupt handling is described in a separate section, refer to “Interrupts and Programmable
Multilevel Interrupt Controller” on page 28.
Architectural Overview
In order to maximize performance and parallelism, the AVR CPU uses a Harvard architecture with separate memories
and buses for program and data. Instructions in the program memory are executed with single-level pipelining. While one
instruction is being executed, the next instruction is pre-fetched from the program memory. This enables instructions to
be executed on every clock cycle. For details of all AVR instructions, refer to http://www.atmel.com/avr.
Figure 6-1. Block diagram of the AVR CPU architecture.
Program
Register File
Counter
R31 (ZH)
R29 (YH)
R27 (XH)
R25
R30 (ZL)
R28 (YL)
R26 (XL)
R24
R23
R22
R21
R20
R19
R18
Flash Program
Memory
R17
R16
R15
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
Instruction
Register
R1
R0
Instruction
Decode
Data Memory
Stack
Pointer
Status
Register
ALU
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The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a
register. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status register is
updated to reflect information about the result of the operation.
The ALU is directly connected to the fast-access register file. The 32 x 8-bit general purpose working registers all have
single clock cycle access time allowing single-cycle arithmetic logic unit (ALU) operation between registers or between a
register and an immediate. Six of the 32 registers can be used as three 16-bit address pointers for program and data
space addressing, enabling efficient address calculations.
The memory spaces are linear. The data memory space and the program memory space are two different memory
spaces.
The data memory space is divided into I/O registers, SRAM, and external RAM. In addition, the EEPROM can be
memory mapped in the data memory.
All I/O status and control registers reside in the lowest 4KB addresses of the data memory. This is referred to as the I/O
memory space. The lowest 64 addresses can be accessed directly, or as the data space locations from 0x00 to 0x3F.
The rest is the extended I/O memory space, ranging from 0x0040 to 0x0FFF. I/O registers here must be accessed as
data space locations using load (LD/LDS/LDD) and store (ST/STS/STD) instructions.
The SRAM holds data. Code execution from SRAM is not supported. It can easily be accessed through the five different
addressing modes supported in the AVR architecture. The first SRAM address is 0x2000.
Data addresses 0x1000 to 0x1FFF are reserved for memory mapping of EEPROM.
The program memory is divided in two sections, the application program section and the boot program section. Both
sections have dedicated lock bits for write and read/write protection. The SPM instruction that is used for self-
programming of the application flash memory must reside in the boot program section. The application section contains
an application table section with separate lock bits for write and read/write protection. The application table section can
be used for safe storing of nonvolatile data in the program memory.
6.4
ALU - Arithmetic Logic Unit
The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a
register. Single-register operations can also be executed. The ALU operates in direct connection with all 32 general
purpose registers. In a single clock cycle, arithmetic operations between general purpose registers or between a register
and an immediate are executed and the result is stored in the register file. After an arithmetic or logic operation, the
status register is updated to reflect information about the result of the operation.
ALU operations are divided into three main categories – arithmetic, logical, and bit functions. Both 8- and 16-bit
arithmetic is supported, and the instruction set allows for efficient implementation of 32-bit aritmetic. The hardware
multiplier supports signed and unsigned multiplication and fractional format.
6.4.1 Hardware Multiplier
The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware multiplier supports different
variations of signed and unsigned integer and fractional numbers:
Multiplication of unsigned integers
Multiplication of signed integers
Multiplication of a signed integer with an unsigned integer
Multiplication of unsigned fractional numbers
Multiplication of signed fractional numbers
Multiplication of a signed fractional number with an unsigned one
A multiplication takes two CPU clock cycles.
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6.5
Program Flow
After reset, the CPU starts to execute instructions from the lowest address in the flash programmemory ‘0.’ The program
counter (PC) addresses the next instruction to be fetched.
Program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole
address space directly. Most AVR instructions use a 16-bit word format, while a limited number use a 32-bit format.
During interrupts and subroutine calls, the return address PC is stored on the stack. The stack is allocated in the general
data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. After
reset, the stack pointer (SP) points to the highest address in the internal SRAM. The SP is read/write accessible in the
I/O memory space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can easily be
accessed through the five different addressing modes supported in the AVR CPU.
6.6
Status Register
The status register (SREG) contains information about the result of the most recently executed arithmetic or logic
instruction. This information can be used for altering program flow in order to perform conditional operations. Note that
the status register is updated after all ALU operations, as specified in the instruction set reference. This will in many
cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
The status register is not automatically stored when entering an interrupt routine nor restored when returning from an
interrupt. This must be handled by software.
The status register is accessible in the I/O memory space.
6.7
Stack and Stack Pointer
The stack is used for storing return addresses after interrupts and subroutine calls. It can also be used for storing
temporary data. The stack pointer (SP) register always points to the top of the stack. It is implemented as two 8-bit
registers that are accessible in the I/O memory space. Data are pushed and popped from the stack using the PUSH and
POP instructions. The stack grows from a higher memory location to a lower memory location. This implies that pushing
data onto the stack decreases the SP, and popping data off the stack increases the SP. The SP is automatically loaded
after reset, and the initial value is the highest address of the internal SRAM. If the SP is changed, it must be set to point
above address 0x2000, and it must be defined before any subroutine calls are executed or before interrupts are enabled.
During interrupts or subroutine calls, the return address is automatically pushed on the stack. The return address can be
two or three bytes, depending on program memory size of the device. For devices with 128KB or less of program
memory, the return address is two bytes, and hence the stack pointer is decremented/incremented by two. For devices
with more than 128KB of program memory, the return address is three bytes, and hence the SP is
decremented/incremented by three. The return address is popped off the stack when returning from interrupts using the
RETI instruction, and from subroutine calls using the RET instruction.
The SP is decremented by one when data are pushed on the stack with the PUSH instruction, and incremented by one
when data is popped off the stack using the POP instruction.
To prevent corruption when updating the stack pointer from software, a write to SPL will automatically disable interrupts
for up to four instructions or until the next I/O memory write.
After reset the stack pointer is initialized to the highest address of the SRAM. See Figure 7-2 on page 13.
6.8
Register File
The register file consists of 32 x 8-bit general purpose working registers with single clock cycle access time. The register
file supports the following input/output schemes:
One 8-bit output operand and one 8-bit result input
Two 8-bit output operands and one 8-bit result input
Two 8-bit output operands and one 16-bit result input
One 16-bit output operand and one 16-bit result input
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Six of the 32 registers can be used as three 16-bit address register pointers for data space addressing, enabling efficient
address calculations. One of these address pointers can also be used as an address pointer for lookup tables in flash
program memory.
7.
Memories
7.1
Features
Flash program memory
One linear address space
In-system programmable
Self-programming and boot loader support
Application section for application code
Application table section for application code or data storage
Boot section for application code or boot loader code
Separate read/write protection lock bits for all sections
Built in fast CRC check of a selectable flash program memory section
Data memory
One linear address space
Single-cycle access from CPU
SRAM
EEPROM
Byte and page accessible
Optional memory mapping for direct load and store
I/O memory
Configuration and status registers for all peripherals and modules
16 bit-accessible general purpose registers for global variables or flags
Bus arbitration
Deterministic priority handling between CPU, DMA controller, and other bus masters
Separate buses for SRAM, EEPROM and I/O memory
Simultaneous bus access for CPU and DMA controller
Production signature row memory for factory programmed data
ID for each microcontroller device type
Serial number for each device
Calibration bytes for factory calibrated peripherals
User signature row
One flash page in size
Can be read and written from software
Content is kept after chip erase
7.2
Overview
The Atmel AVR architecture has two main memory spaces, the program memory and the data memory. Executable code
can reside only in the program memory, while data can be stored in the program memory and the data memory. The data
memory includes the internal SRAM, and EEPROM for nonvolatile data storage. All memory spaces are linear and
require no memory bank switching. Nonvolatile memory (NVM) spaces can be locked for further write and read/write
operations. This prevents unrestricted access to the application software.
A separate memory section contains the fuse bytes. These are used for configuring important system functions, and can
only be written by an external programmer.
The available memory size configurations are shown in “Ordering Information” on page 2. In addition, each device has a
Flash memory signature row for calibration data, device identification, serial number etc.
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7.3
Flash Program Memory
The Atmel AVR XMEGA devices contain on-chip, in-system reprogrammable flash memory for program storage. The
flash memory can be accessed for read and write from an external programmer through the PDI or from application
software running in the device.
All AVR CPU instructions are 16 or 32 bits wide, and each flash location is 16 bits wide. The flash memory is organized
in two main sections, the application section and the boot loader section. The sizes of the different sections are fixed, but
device-dependent. These two sections have separate lock bits, and can have different levels of protection. The store
program memory (SPM) instruction, which is used to write to the flash from the application software, will only operate
when executed from the boot loader section.
The application section contains an application table section with separate lock settings. This enables safe storage of
nonvolatile data in the program memory.
Figure 7-1. Flash Program Memory (Hexadecimal address).
Word Address
0
Application Section
(256K)
...
1EFFF
1F000
1FFFF
20000
20FFF
Application Table Section
(8K)
Boot Section
(8K)
7.3.1 Application Section
The Application section is the section of the flash that is used for storing the executable application code. The protection
level for the application section can be selected by the boot lock bits for this section. The application section can not store
any boot loader code since the SPM instruction cannot be executed from the application section.
7.3.2 Application Table Section
The application table section is a part of the application section of the flash memory that can be used for storing data.
The size is identical to the boot loader section. The protection level for the application table section can be selected by
the boot lock bits for this section. The possibilities for different protection levels on the application section and the
application table section enable safe parameter storage in the program memory. If this section is not used for data,
application code can reside here.
7.3.3 Boot Loader Section
While the application section is used for storing the application code, the boot loader software must be located in the boot
loader section because the SPM instruction can only initiate programming when executing from this section. The SPM
instruction can access the entire flash, including the boot loader section itself. The protection level for the boot loader
section can be selected by the boot loader lock bits. If this section is not used for boot loader software, application code
can be stored here.
7.3.4 Production Signature Row
The production signature row is a separate memory section for factory programmed data. It contains calibration data for
functions such as oscillators and analog modules. Some of the calibration values will be automatically loaded to the
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corresponding module or peripheral unit during reset. Other values must be loaded from the signature row and written to
the corresponding peripheral registers from software. For details on calibration conditions, refer to “Electrical
Characteristics” on page 69.
The production signature row also contains an ID that identifies each microcontroller device type and a serial number for
each manufactured device. The serial number consists of the production lot number, wafer number, and wafer
coordinates for the device. The device ID for the available devices is shown in Table 7-1.
The production signature row cannot be written or erased, but it can be read from application software and external
programmers.
Table 7-1. Device ID bytes for Atmel AVR XMEGA A3BU devices.
Device
Device ID bytes
Byte 1
98
Byte 2
43
Byte 0
1E
ATxmega256A3BU
7.3.5 User Signature Row
The user signature row is a separate memory section that is fully accessible (read and write) from application software
and external programmers. It is one flash page in size, and is meant for static user parameter storage, such as calibration
data, custom serial number, identification numbers, random number seeds, etc. This section is not erased by chip erase
commands that erase the flash, and requires a dedicated erase command. This ensures parameter storage during
multiple program/erase operations and on-chip debug sessions.
7.4
Fuses and Lock bits
The fuses are used to configure important system functions, and can only be written from an external programmer. The
application software can read the fuses. The fuses are used to configure reset sources such as brownout detector and
watchdog, startup configuration, JTAG enable, and JTAG user ID.
The lock bits are used to set protection levels for the different flash sections (that is, if read and/or write access should be
blocked). Lock bits can be written by external programmers and application software, but only to stricter protection levels.
Chip erase is the only way to erase the lock bits. To ensure that flash contents are protected even during chip erase, the
lock bits are erased after the rest of the flash memory has been erased.
An unprogrammed fuse or lock bit will have the value one, while a programmed fuse or lock bit will have the value zero.
Both fuses and lock bits are reprogrammable like the flash program memory.
7.5
Data Memory
The data memory contains the I/O memory, internal SRAM, optionally memory mapped EEPROM, and external memory
if available. The data memory is organized as one continuous memory section, see Figure 7-2. To simplify development,
I/O Memory, EEPROM and SRAM will always have the same start addresses for all Atmel AVR XMEGA devices.
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Figure 7-2. Data memory map (Hexadecimal address).
Byte Address
ATxmega256A3BU
0
FFF
I/O Registers
(4K)
1000
EEPROM
(4K)
1FFF
2000
5FFF
Internal SRAM
(16K)
7.6
7.7
EEPROM
XMEGA AU devices have EEPROM for nonvolatile data storage. It is either addressable in a separate data space
(default) or memory mapped and accessed in normal data space. The EEPROM supports both byte and page access.
Memory mapped EEPROM allows highly efficient EEPROM reading and EEPROM buffer loading. When doing this,
EEPROM is accessible using load and store instructions. Memory mapped EEPROM will always start at hexadecimal
address 0x1000.
I/O Memory
The status and configuration registers for peripherals and modules, including the CPU, are addressable through I/O
memory locations. All I/O locations can be accessed by the load (LD/LDS/LDD) and store (ST/STS/STD) instructions,
which are used to transfer data between the 32 registers in the register file and the I/O memory. The IN and OUT
instructions can address I/O memory locations in the range of 0x00 to 0x3F directly. In the address range 0x00 - 0x1F,
single-cycle instructions for manipulation and checking of individual bits are available.
The I/O memory address for all peripherals and modules in XMEGA A3BU is shown in the “Peripheral Module Address
Map” on page 60.
7.7.1 General Purpose I/O Registers
The lowest 16 I/O memory addresses are reserved as general purpose I/O registers. These registers can be used for
storing global variables and flags, as they are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
7.8
7.9
Data Memory and Bus Arbitration
Since the data memory is organized as four separate sets of memories, the different bus masters (CPU, DMA controller
read and DMA controller write, etc.) can access different memory sections at the same time.
Memory Timing
Read and write access to the I/O memory takes one CPU clock cycle. A write to SRAM takes one cycle, and a read from
SRAM takes two cycles. For burst read (DMA), new data are available every cycle. EEPROM page load (write) takes one
cycle, and three cycles are required for read. For burst read, new data are available every second cycle. Refer to the
instruction summary for more details on instructions and instruction timing.
7.10 Device ID and Revision
Each device has a three-byte device ID. This ID identifies Atmel as the manufacturer of the device and the device type. A
separate register contains the revision number of the device.
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7.11 JTAG Disable
It is possible to disable the JTAG interface from the application software. This will prevent all external JTAG access to the
device until the next device reset or until JTAG is enabled again from the application software. As long as JTAG is
disabled, the I/O pins required for JTAG can be used as normal I/O pins.
7.12 I/O Memory Protection
Some features in the device are regarded as critical for safety in some applications. Due to this, it is possible to lock the
I/O register related to the clock system, the event system, and the advanced waveform extensions. As long as the lock is
enabled, all related I/O registers are locked and they can not be written from the application software. The lock registers
themselves are protected by the configuration change protection mechanism.
7.13 Flash and EEPROM Page Size
The flash program memory and EEPROM data memory are organized in pages. The pages are word accessible for the
flash and byte accessible for the EEPROM.
Table 7-2 on page 14 shows the Flash Program Memory organization and Program Counter (PC) size. Flash write and
erase operations are performed on one page at a time, while reading the Flash is done one byte at a time. For Flash
access the Z-pointer (Z[m:n]) is used for addressing. The most significant bits in the address (FPAGE) give the page
number and the least significant address bits (FWORD) give the word in the page.
Table 7-2. Number of words and pages in the flash.
Devices
PC size
Flash size
Page size
FWORD
FPAGE
Application
Boot
No of
pages
No of
pages
[bits]
[bytes]
[words]
Size
Size
8K
ATxmega256A3B
U
18
256K + 8K
256
Z[8:1]
Z[18:9]
256K
512
16
Table 7-3 on page 14 shows EEPROM memory organization. EEPROM write and erase operations can be performed
one page or one byte at a time, while reading the EEPROM is done one byte at a time. For EEPROM access the NVM
address register (ADDR[m:n]) is used for addressing. The most significant bits in the address (E2PAGE) give the page
number and the least significant address bits (E2BYTE) give the byte in the page.
Table 7-3. Number of bytes and pages in the EEPROM.
Devices
EEPROM
size
Page size
[bytes]
32
E2BYTE
E2PAGE
No of pages
ATxmega256A3BU
4K
ADDR[4:0]
ADDR[11:5]
128
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8.
DMAC – Direct Memory Access Controller
8.1
Features
Allows high speed data transfers with minimal CPU intervention
from data memory to data memory
from data memory to peripheral
from peripheral to data memory
from peripheral to peripheral
Four DMA channels with separate
transfer triggers
interrupt vectors
addressing modes
Programmable channel priority
From 1 byte to 16MB of data in a single transaction
Up to 64KB block transfers with repeat
1, 2, 4, or 8 byte burst transfers
Multiple addressing modes
Static
Incremental
Decremental
Optional reload of source and destination addresses at the end of each
Burst
Block
Transaction
Optional interrupt on end of transaction
Optional connection to CRC generator for CRC on DMA data
8.2
Overview
The four-channel direct memory access (DMA) controller can transfer data between memories and peripherals, and thus
offload these tasks from the CPU. It enables high data transfer rates with minimum CPU intervention, and frees up CPU
time. The four DMA channels enable up to four independent and parallel transfers.
The DMA controller can move data between SRAM and peripherals, between SRAM locations and directly between
peripheral registers. With access to all peripherals, the DMA controller can handle automatic transfer of data to/from
communication modules. The DMA controller can also read from memory mapped EEPROM.
Data transfers are done in continuous bursts of 1, 2, 4, or 8 bytes. They build block transfers of configurable size from
1 byte to 64KB. A repeat counter can be used to repeat each block transfer for single transactions up to 16MB. Source
and destination addressing can be static, incremental or decremental. Automatic reload of source and/or destination
addresses can be done after each burst or block transfer, or when a transaction is complete. Application software,
peripherals, and events can trigger DMA transfers.
The four DMA channels have individual configuration and control settings. This include source, destination, transfer
triggers, and transaction sizes. They have individual interrupt settings. Interrupt requests can be generated when a
transaction is complete or when the DMA controller detects an error on a DMA channel.
To allow for continuous transfers, two channels can be interlinked so that the second takes over the transfer when the
first is finished, and vice versa.
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9.
Event System
9.1
Features
System for direct peripheral-to-peripheral communication and signaling
Peripherals can directly send, receive, and react to peripheral events
CPU and DMA controller independent operation
100% predictable signal timing
Short and guaranteed response time
Eight event channels for up to eight different and parallel signal routing configurations
Events can be sent and/or used by most peripherals, clock system, and software
Additional functions include
Quadrature decoders
Digital filtering of I/O pin state
Works in active mode and idle sleep mode
9.2
Overview
The event system enables direct peripheral-to-peripheral communication and signaling. It allows a change in one
peripheral’s state to automatically trigger actions in other peripherals. It is designed to provide a predictable system for
short and predictable response times between peripherals. It allows for autonomous peripheral control and interaction
without the use of interrupts, CPU, or DMA controller resources, and is thus a powerful tool for reducing the complexity,
size and execution time of application code. It also allows for synchronized timing of actions in several peripheral
modules.
A change in a peripheral’s state is referred to as an event, and usually corresponds to the peripheral’s interrupt
conditions. Events can be directly passed to other peripherals using a dedicated routing network called the event routing
network. How events are routed and used by the peripherals is configured in software.
Figure 9-1 on page 17 shows a basic diagram of all connected peripherals. The event system can directly connect
together analog and digital converters, analog comparators, I/O port pins, the real-time counter, timer/counters, IR
communication module (IRCOM), and USB interface. It can also be used to trigger DMA transactions (DMA controller).
Events can also be generated from software and the peripheral clock.
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Figure 9-1. Event system overview and connected peripherals.
CPU /
Software
DMA
Controller
Event Routing Network
clkPER
Prescaler
ADC
AC
Real Time
Counter
Event
System
Controller
Timer /
Counters
DAC
USB
Port pins
IRCOM
The event routing network consists of eight software-configurable multiplexers that control how events are routed and
used. These are called event channels, and allow for up to eight parallel event routing configurations. The maximum
routing latency is two peripheral clock cycles. The event system works in both active mode and idle sleep mode.
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10. System Clock and Clock options
10.1 Features
Fast start-up time
Safe run-time clock switching
Internal oscillators:
32MHz run-time calibrated and tuneable oscillator
2MHz run-time calibrated oscillator
32.768kHz calibrated oscillator
32kHz ultra low power (ULP) oscillator with 1kHz output
External clock options
0.4MHz - 16MHz crystal oscillator
32.768kHz crystal oscillator
External clock
PLL with 20MHz - 128MHz output frequency
Internal and external clock options and 1x to 31x multiplication
Lock detector
Clock prescalers with 1x to 2048x division
Fast peripheral clocks running at two and four times the CPU clock
Automatic run-time calibration of internal oscillators
External oscillator and PLL lock failure detection with optional non-maskable interrupt
10.2 Overview
Atmel AVR XMEGA A3BU devices have a flexible clock system supporting a large number of clock sources. It
incorporates both accurate internal oscillators and external crystal oscillator and resonator support. A high-frequency
phase locked loop (PLL) and clock prescalers can be used to generate a wide range of clock frequencies. A calibration
feature (DFLL) is available, and can be used for automatic run-time calibration of the internal oscillators to remove
frequency drift over voltage and temperature. An oscillator failure monitor can be enabled to issue a non-maskable
interrupt and switch to the internal oscillator if the external oscillator or PLL fails.
When a reset occurs, all clock sources except the 32kHz ultra low power oscillator are disabled. After reset, the device
will always start up running from the 2MHz internal oscillator. During normal operation, the system clock source and
prescalers can be changed from software at any time.
Figure 10-1 on page 19 presents the principal clock system in the XMEGA A3BU family of devices. Not all of the clocks
need to be active at a given time. The clocks for the CPU and peripherals can be stopped using sleep modes and power
reduction registers, as described in “Power Management and Sleep Modes” on page 21
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Figure 10-1. The clock system, clock sources and clock distribution.
Real Time
Counter
Non-Volatile
Memory
Peripherals
RAM
AVR CPU
clkPER
clkPER2
clkPER4
clkCPU
USB
clkUSB
System Clock Prescalers
clkSYS
Brown-out
Detector
Watchdog
Timer
Prescaler
clkRTC
System Clock Multiplexer
(SCLKSEL)
USBSRC
PLL
PLLSRC
XOSCSEL
32kHz
Int. ULP
32.768kHz
Int. OSC
32.768kHz
TOSC
0.4 – 16MHz
XTAL
32MHz
Int. Osc
2MHz
Int. Osc
10.3 Clock Sources
The clock sources are divided in two main groups: internal oscillators and external clock sources. Most of the clock
sources can be directly enabled and disabled from software, while others are automatically enabled or disabled,
depending on peripheral settings. After reset, the device starts up running from the 2MHz internal oscillator. The other
clock sources, DFLLs and PLL, are turned off by default.
The internal oscillators do not require any external components to run. For details on characteristics and accuracy of the
internal oscillators, refer to the device datasheet.
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10.3.1 32kHz Ultra Low Power Internal Oscillator
This oscillator provides an approximate 32kHz clock. The 32kHz ultra low power (ULP) internal oscillator is a very low
power clock source, and it is not designed for high accuracy. The oscillator employs a built-in prescaler that provides a
1kHz output. The oscillator is automatically enabled/disabled when it is used as clock source for any part of the device.
10.3.2 32.768kHz Calibrated Internal Oscillator
This oscillator provides an approximate 32.768kHz clock. It is calibrated during production to provide a default frequency
close to its nominal frequency. The calibration register can also be written from software for run-time calibration of the
oscillator frequency. The oscillator employs a built-in prescaler, which provides both a 32.768kHz output and a 1.024kHz
output.
10.3.3 32.768kHz Crystal Oscillator
A 32.768kHz crystal oscillator can be connected between the TOSC1 and TOSC2 pins and enables a dedicated low
frequency oscillator input circuit. A low power mode with reduced voltage swing on TOSC2 is available. This oscillator
can be used as a clock source for the system clock and RTC, and as the DFLL reference clock.
10.3.4 0.4 - 16MHz Crystal Oscillator
This oscillator can operate in four different modes optimized for different frequency ranges, all within 0.4 - 16MHz.
10.3.5 2MHz Run-time Calibrated Internal Oscillator
The 2MHz run-time calibrated internal oscillator is the default system clock source after reset. It is calibrated during
production to provide a default frequency close to its nominal frequency. A DFLL can be enabled for automatic run-time
calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator accuracy.
10.3.6 32MHz Run-time Calibrated Internal Oscillator
The 32MHz run-time calibrated internal oscillator is a high-frequency oscillator. It is calibrated during production to
provide a default frequency close to its nominal frequency. A digital frequency looked loop (DFLL) can be enabled for
automatic run-time calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator
accuracy. This oscillator can also be adjusted and calibrated to any frequency between 30MHz and 55MHz. The
production signature row contains 48MHz calibration values intended used when the oscillator is used a full-speed USB
clock source.
10.3.7 External Clock Sources
The XTAL1 and XTAL2 pins can be used to drive an external oscillator, either a quartz crystal or a ceramic resonator.
XTAL1 can be used as input for an external clock signal. The TOSC1 and TOSC2 pins is dedicated to driving a
32.768kHz crystal oscillator.
10.3.8 PLL with 1x-31x Multiplication Factor
The built-in phase locked loop (PLL) can be used to generate a high-frequency system clock. The PLL has a user-
selectable multiplication factor of from 1 to 31. In combination with the prescalers, this gives a wide range of output
frequencies from all clock sources.
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11. Power Management and Sleep Modes
11.1 Features
Power management for adjusting power consumption and functions
Five sleep modes
Idle
Power down
Power save
Standby
Extended standby
Power reduction register to disable clock and turn off unused peripherals in active and idle modes
11.2 Overview
Various sleep modes and clock gating are provided in order to tailor power consumption to application requirements.
This enables the Atmel AVR XMEGA microcontroller to stop unused modules to save power.
All sleep modes are available and can be entered from active mode. In active mode, the CPU is executing application
code. When the device enters sleep mode, program execution is stopped and interrupts or a reset is used to wake the
device again. The application code decides which sleep mode to enter and when. Interrupts from enabled peripherals
and all enabled reset sources can restore the microcontroller from sleep to active mode.
In addition, power reduction registers provide a method to stop the clock to individual peripherals from software. When
this is done, the current state of the peripheral is frozen, and there is no power consumption from that peripheral. This
reduces the power consumption in active mode and idle sleep modes and enables much more fine-tuned power
management than sleep modes alone.
11.3 Sleep Modes
Sleep modes are used to shut down modules and clock domains in the microcontroller in order to save power. XMEGA
microcontrollers have five different sleep modes tuned to match the typical functional stages during application
execution. A dedicated sleep instruction (SLEEP) is available to enter sleep mode. Interrupts are used to wake the
device from sleep, and the available interrupt wake-up sources are dependent on the configured sleep mode. When an
enabled interrupt occurs, the device will wake up and execute the interrupt service routine before continuing normal
program execution from the first instruction after the SLEEP instruction. If other, higher priority interrupts are pending
when the wake-up occurs, their interrupt service routines will be executed according to their priority before the interrupt
service routine for the wake-up interrupt is executed. After wake-up, the CPU is halted for four cycles before execution
starts.
The content of the register file, SRAM and registers are kept during sleep. If a reset occurs during sleep, the device will
reset, start up, and execute from the reset vector.
11.3.1 Idle Mode
In idle mode the CPU and nonvolatile memory are stopped (note that any ongoing programming will be completed), but
all peripherals, including the interrupt controller, event system and DMA controller are kept running. Any enabled
interrupt will wake the device.
11.3.2 Power-down Mode
In power-down mode, all clocks, including the real-time counter clock source, are stopped. This allows operation only of
asynchronous modules that do not require a running clock. The only interrupts that can wake up the MCU are the two-
wire interface address match interrupt, asynchronous port interrupts, and the USB resume interrupt.
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11.3.3 Power-save Mode
Power-save mode is identical to power down, with one exception. If the real-time counter (RTC) is enabled, it will keep
running during sleep, and the device can also wake up from either an RTC overflow or compare match interrupt.
11.3.4 Standby Mode
Standby mode is identical to power down, with the exception that the enabled system clock sources are kept running
while the CPU, peripheral, and RTC clocks are stopped. This reduces the wake-up time.
11.3.5 Extended Standby Mode
Extended standby mode is identical to power-save mode, with the exception that the enabled system clock sources are
kept running while the CPU and peripheral clocks are stopped. This reduces the wake-up time.
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12. System Control and Reset
12.1 Features
Reset the microcontroller and set it to initial state when a reset source goes active
Multiple reset sources that cover different situations
Power-on reset
External reset
Watchdog reset
Brownout reset
PDI reset
Software reset
Asynchronous operation
No running system clock in the device is required for reset
Reset status register for reading the reset source from the application code
12.2 Overview
The reset system issues a microcontroller reset and sets the device to its initial state. This is for situations where
operation should not start or continue, such as when the microcontroller operates below its power supply rating. If a reset
source goes active, the device enters and is kept in reset until all reset sources have released their reset. The I/O pins
are immediately tri-stated. The program counter is set to the reset vector location, and all I/O registers are set to their
initial values. The SRAM content is kept. However, if the device accesses the SRAM when a reset occurs, the content of
the accessed location can not be guaranteed.
After reset is released from all reset sources, the default oscillator is started and calibrated before the device starts
running from the reset vector address. By default, this is the lowest program memory address, 0, but it is possible to
move the reset vector to the lowest address in the boot section.
The reset functionality is asynchronous, and so no running system clock is required to reset the device. The software
reset feature makes it possible to issue a controlled system reset from the user software.
The reset status register has individual status flags for each reset source. It is cleared at power-on reset, and shows
which sources have issued a reset since the last power-on.
12.3 Reset Sequence
A reset request from any reset source will immediately reset the device and keep it in reset as long as the request is
active. When all reset requests are released, the device will go through three stages before the device starts running
again:
Reset counter delay
Oscillator startup
Oscillator calibration
If another reset requests occurs during this process, the reset sequence will start over again.
12.4 Reset Sources
12.4.1 Power-on Reset
A power-on reset (POR) is generated by an on-chip detection circuit. The POR is activated when the VCC rises and
reaches the POR threshold voltage (VPOT), and this will start the reset sequence.
The POR is also activated to power down the device properly when the VCC falls and drops below the VPOT level.
The VPOT level is higher for falling VCC than for rising VCC. Consult the datasheet for POR characteristics data.
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12.4.2 Brownout Detection
The on-chip brownout detection (BOD) circuit monitors the VCC level during operation by comparing it to a fixed,
programmable level that is selected by the BODLEVEL fuses. If disabled, BOD is forced on at the lowest level during chip
erase and when the PDI is enabled.
12.4.3 External Reset
The external reset circuit is connected to the external RESET pin. The external reset will trigger when the RESET pin is
driven below the RESET pin threshold voltage, VRST, for longer than the minimum pulse period, tEXT. The reset will be
held as long as the pin is kept low. The RESET pin includes an internal pull-up resistor.
12.4.4 Watchdog Reset
The watchdog timer (WDT) is a system function for monitoring correct program operation. If the WDT is not reset from
the software within a programmable timeout period, a watchdog reset will be given. The watchdog reset is active for one
to two clock cycles of the 2MHz internal oscillator. For more details see “WDT – Watchdog Timer” on page 25.
12.4.5 Software Reset
The software reset makes it possible to issue a system reset from software by writing to the software reset bit in the reset
control register.The reset will be issued within two CPU clock cycles after writing the bit. It is not possible to execute any
instruction from when a software reset is requested until it is issued.
12.4.6 Program and Debug Interface Reset
The program and debug interface reset contains a separate reset source that is used to reset the device during external
programming and debugging. This reset source is accessible only from external debuggers and programmers.
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13. WDT – Watchdog Timer
13.1 Features
Issues a device reset if the timer is not reset before its timeout period
Asynchronous operation from dedicated oscillator
1kHz output of the 32kHz ultra low power oscillator
11 selectable timeout periods, from 8ms to 8s
Two operation modes:
Normal mode
Window mode
Configuration lock to prevent unwanted changes
13.2 Overview
The watchdog timer (WDT) is a system function for monitoring correct program operation. It makes it possible to recover
from error situations such as runaway or deadlocked code. The WDT is a timer, configured to a predefined timeout
period, and is constantly running when enabled. If the WDT is not reset within the timeout period, it will issue a
microcontroller reset. The WDT is reset by executing the WDR (watchdog timer reset) instruction from the application
code.
The window mode makes it possible to define a time slot or window inside the total timeout period during which WDT
must be reset. If the WDT is reset outside this window, either too early or too late, a system reset will be issued.
Compared to the normal mode, this can also catch situations where a code error causes constant WDR execution.
The WDT will run in active mode and all sleep modes, if enabled. It is asynchronous, runs from a CPU-independent clock
source, and will continue to operate to issue a system reset even if the main clocks fail.
The configuration change protection mechanism ensures that the WDT settings cannot be changed by accident. For
increased safety, a fuse for locking the WDT settings is also available.
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14. Battery Backup System
14.1 Features
Battery Backup voltage supply from dedicated VBAT power pin for:
One Ultra Low-power 32-bit Real Time Counter (RTC)
One 32.768kHz crystal oscillator with failure detection monitor
Two Backup Registers
Typical power consumption of 500nA with Real Time Counter running
Automatic switching from main power to battery backup power at:
Brown-Out Detection (BOD) reset
Automatic switching from battery backup power to main power:
Device reset after Brown-Out Reset (BOR) is released
Device reset after Power-On Reset (POR) and BOR is released
14.2 Overview
Atmel AVR XMEGA family is already running in an ultra low leakage process with power-save current consumption below
2µA with RTC, BOD and watchdog enabled. Still, for some applications where time keeping is important, the system
would have one main battery or power source used for day to day tasks, and one backup battery power for the time
keeping functionality. The Battery Backup System includes functionality that enable automatic power switching between
main power and a battery backup power. Figure 14-1 on page 27 shows an overview of the system.
The Battery Backup Module support connection of a backup battery to the dedicated VBAT power pin. This will ensure
power to the 32-bit Real Time Counter, a 32.768kHz crystal oscillator with failure detection monitor and two backup
registers, when the main battery or power source is unavailable.
Upon main power loss the device will automatically detect this and the Battery Backup Module will switch to be powered
from the VBAT pin. After main power has been restored and both main POR and BOR are released, the Battery Backup
Module will automatically switch back to be powered from main power again.
The 32-bit real time counter (RTC) must be clocked from the 1Hz output of a 32.768kHz crystal oscillator connected
between the TOSC1 and TOSC2 pins when running from VBAT. For more details on the 32-bit RTC refer to the “RTC32 –
32-bit Real-Time Counter” on page 39“.
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Figure 14-1. Battery Backup Module and its power domain implementation.
Power
switch
Main
power
supervision
VBAT
power
supervisor
VBAT
VDD
Watchdog w/
Oscillator
XTAL1
OCD &
Programming
Interface
Oscillator &
sleep
controller
XTAL2
Failure
monitor
CPU
GPIO
TOSC1
TOSC2
&
Peripherals
Crystal
Oscillator
RTC
FLASH,
EEPROM
& Fuses
Internal
RAM
Backup
Registers
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15. Interrupts and Programmable Multilevel Interrupt Controller
15.1 Features
Short and predictable interrupt response time
Separate interrupt configuration and vector address for each interrupt
Programmable multilevel interrupt controller
Interrupt prioritizing according to level and vector address
Three selectable interrupt levels for all interrupts: low, medium and high
Selectable, round-robin priority scheme within low-level interrupts
Non-maskable interrupts for critical functions
Interrupt vectors optionally placed in the application section or the boot loader section
15.2 Overview
Interrupts signal a change of state in peripherals, and this can be used to alter program execution. Peripherals can have
one or more interrupts, and all are individually enabled and configured. When an interrupt is enabled and configured, it
will generate an interrupt request when the interrupt condition is present. The programmable multilevel interrupt
controller (PMIC) controls the handling and prioritizing of interrupt requests. When an interrupt request is acknowledged
by the PMIC, the program counter is set to point to the interrupt vector, and the interrupt handler can be executed.
All peripherals can select between three different priority levels for their interrupts: low, medium, and high. Interrupts are
prioritized according to their level and their interrupt vector address. Medium-level interrupts will interrupt low-level
interrupt handlers. High-level interrupts will interrupt both medium- and low-level interrupt handlers. Within each level, the
interrupt priority is decided from the interrupt vector address, where the lowest interrupt vector address has the highest
interrupt priority. Low-level interrupts have an optional round-robin scheduling scheme to ensure that all interrupts are
serviced within a certain amount of time.
Non-maskable interrupts (NMI) are also supported, and can be used for system critical functions.
15.3 Interrupt vectors
The interrupt vector is the sum of the peripheral’s base interrupt address and the offset address for specific interrupts in
each peripheral. The base addresses for the Atmel AVR XMEGA A3BU devices are shown in Table 15-1. Offset
addresses for each interrupt available in the peripheral are described for each peripheral in the XMEGA AU manual. For
peripherals or modules that have only one interrupt, the interrupt vector is shown in Table 15-1. The program address is
the word address.
Table 15-1. Reset and interrupt vectors.
Program address
(base address)
Source
Interrupt description
0x000
RESET
0x002
OSCF_INT_vect
PORTC_INT_base
PORTR_INT_base
DMA_INT_base
RTC32_INT_base
TWIC_INT_base
TCC0_INT_base
Crystal oscillator failure interrupt vector (NMI)
Port C interrupt base
0x004
0x008
Port R interrupt base
0x00C
DMA controller interrupt base
0x014
32-bit Real Time Counter interrupt base
Two-Wire Interface on Port C interrupt base
Timer/Counter 0 on Port C interrupt base
0x018
0x01C
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Program address
(base address)
Source
Interrupt description
0x028
0x030
0x032
0x038
0x03E
0x040
0x044
0x048
0x04E
0x056
0x05A
0x05E
0x06A
0x074
0x080
0x084
0x088
0x08E
0x09A
0x0A6
0x0AE
0x0B0
0x0B6
0x0D0
0x0D8
0x0EE
0x0FA
TCC1_INT_base
SPIC_INT_vect
Timer/Counter 1 on Port C interrupt base
SPI on Port C interrupt vector
USARTC0_INT_base
USARTC1_INT_base
AES_INT_vect
USART 0 on Port C interrupt base
USART 1 on Port C interrupt base
AES interrupt vector
NVM_INT_base
PORTB_INT_base
ACB_INT_base
Non-Volatile Memory interrupt base
Port B interrupt base
Analog Comparator on Port B interrupt base
Analog to Digital Converter on Port B interrupt base
Port E interrupt base
ADCB_INT_base
PORTE_INT_base
TWIE_INT_base
TCE0_INT_base
TCE1_INT_base
USARTE0_INT_base
PORTD_INT_base
PORTA_INT_base
ACA_INT_base
Two-Wire Interface on Port E interrupt base
Timer/Counter 0 on Port E interrupt base
Timer/Counter 1 on Port E interrupt base
USART 0 on Port E interrupt base
Port D interrupt base
Port A interrupt base
Analog Comparator on Port A interrupt base
Analog to Digital Converter on Port A interrupt base
Timer/Counter 0 on Port D interrupt base
Timer/Counter 1 on Port D interrupt base
SPI on Port D interrupt vector
ADCA_INT_base
TCD0_INT_base
TCD1_INT_base
SPID_INT_vector
USARTD0_INT_base
USARTD1_INT_base
PORTF_INT_base
TCF0_INT_base
USARTF0_INT_base
USB_INT_base
USART 0 on Port D interrupt base
USART 1 on Port D interrupt base
Port F interrupt base
Timer/Counter 0 on Port F interrupt base
USART 0 on Port F interrupt base
USB on Port D interrupt base
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16. I/O Ports
16.1 Features
47 general purpose input and output pins with individual configuration
Output driver with configurable driver and pull settings:
Totem-pole
Wired-AND
Wired-OR
Bus-keeper
Inverted I/O
Input with synchronous and/or asynchronous sensing with interrupts and events
Sense both edges
Sense rising edges
Sense falling edges
Sense low level
Optional pull-up and pull-down resistor on input and Wired-OR/AND configurations
Optional slew rate control
Asynchronous pin change sensing that can wake the device from all sleep modes
Two port interrupts with pin masking per I/O port
Efficient and safe access to port pins
Hardware read-modify-write through dedicated toggle/clear/set registers
Configuration of multiple pins in a single operation
Mapping of port registers into bit-accessible I/O memory space
Peripheral clocks output on port pin
Real-time counter clock output to port pin
Event channels can be output on port pin
Remapping of digital peripheral pin functions
Selectable USART, SPI, and timer/counter input/output pin locations
16.2 Overview
One port consists of up to eight port pins: pin 0 to 7. Each port pin can be configured as input or output with configurable
driver and pull settings. They also implement synchronous and asynchronous input sensing with interrupts and events for
selectable pin change conditions. Asynchronous pin-change sensing means that a pin change can wake the device from
all sleep modes, included the modes where no clocks are running.
All functions are individual and configurable per pin, but several pins can be configured in a single operation. The pins
have hardware read-modify-write (RMW) functionality for safe and correct change of drive value and/or pull resistor
configuration. The direction of one port pin can be changed without unintentionally changing the direction of any other
pin.
The port pin configuration also controls input and output selection of other device functions. It is possible to have both the
peripheral clock and the real-time clock output to a port pin, and available for external use. The same applies to events
from the event system that can be used to synchronize and control external functions. Other digital peripherals, such as
USART, SPI, and timer/counters, can be remapped to selectable pin locations in order to optimize pin-out versus
application needs.
The notation of the ports are PORTA, PORTB, PORTC, PORTD, PORTE, PORTF and PORTR.
16.3 Output Driver
All port pins (Pn) have programmable output configuration. The port pins also have configurable slew rate limitation to
reduce electromagnetic emission.
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16.3.1 Push-pull
Figure 16-1. I/O configuration - Totem-pole.
DIRn
OUTn
INn
Pn
16.3.2 Pull-down
Figure 16-2. I/O configuration - Totem-pole with pull-down (on input).
DIRn
OUTn
INn
Pn
16.3.3 Pull-up
Figure 16-3. I/O configuration - Totem-pole with pull-up (on input).
DIRn
OUTn
INn
Pn
16.3.4 Bus-keeper
The bus-keeper’s weak output produces the same logical level as the last output level. It acts as a pull-up if the last level
was ‘1’, and pull-down if the last level was ‘0’.
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Figure 16-4. I/O configuration - Totem-pole with bus-keeper.
DIRn
OUTn
INn
Pn
16.3.5 Others
Figure 16-5. Output configuration - Wired-OR with optional pull-down.
OUTn
Pn
INn
Figure 16-6. I/O configuration - Wired-AND with optional pull-up.
INn
Pn
OUTn
16.4 Input sensing
Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is
shown in Figure 16-7 on page 33.
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Figure 16-7. Input sensing system overview.
Asynchronous sensing
EDGE
DETECT
Interrupt
Control
IRQ
Synchronous sensing
Pxn
Synchronizer
INn
EDGE
DETECT
Synchronous
Events
D
Q
D
Q
R
R
INVERTED I/O
Asynchronous
Events
When a pin is configured with inverted I/O, the pin value is inverted before the input sensing.
16.5 Alternate Port Functions
Most port pins have alternate pin functions in addition to being a general purpose I/O pin. When an alternate function is
enabled, it might override the normal port pin function or pin value. This happens when other peripherals that require pins
are enabled or configured to use pins. If and how a peripheral will override and use pins is described in the section for
that peripheral. “Pinout and Pin Functions” on page 55 shows which modules on peripherals that enable alternate
functions on a pin, and which alternate functions that are available on a pin.
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17. TC0/1 – 16-bit Timer/Counter Type 0 and 1
17.1 Features
Seven 16-bit timer/counters
Four timer/counters of type 0
Three timer/counters of type 1
Split-mode enabling two 8-bit timer/counter from each timer/counter type 0
32-bit Timer/Counter support by cascading two timer/counters
Up to four compare or capture (CC) channels
Four CC channels for timer/counters of type 0
Two CC channels for timer/counters of type 1
Double buffered timer period setting
Double buffered capture or compare channels
Waveform generation:
Frequency generation
Single-slope pulse width modulation
Dual-slope pulse width modulation
Input capture:
Input capture with noise cancelling
Frequency capture
Pulse width capture
32-bit input capture
Timer overflow and error interrupts/events
One compare match or input capture interrupt/event per CC channel
Can be used with event system for:
Quadrature decoding
Count and direction control
Capture
Can be used with DMA and to trigger DMA transactions
High-resolution extension
Increases frequency and waveform resolution by 4x (2-bit) or 8x (3-bit)
Advanced waveform extension:
Low- and high-side output with programmable dead-time insertion (DTI)
Event controlled fault protection for safe disabling of drivers
17.2 Overview
Atmel AVR XMEGA devices have a set of seven flexible 16-bit Timer/Counters (TC). Their capabilities include accurate
program execution timing, frequency and waveform generation, and input capture with time and frequency measurement
of digital signals. Two timer/counters can be cascaded to create a 32-bit timer/counter with optional 32-bit capture.
A timer/counter consists of a base counter and a set of compare or capture (CC) channels. The base counter can be
used to count clock cycles or events. It has direction control and period setting that can be used for timing. The CC
channels can be used together with the base counter to do compare match control, frequency generation, and pulse
width waveform modulation, as well as various input capture operations. A timer/counter can be configured for either
capture or compare functions, but cannot perform both at the same time.
A timer/counter can be clocked and timed from the peripheral clock with optional prescaling or from the event system.
The event system can also be used for direction control and capture trigger or to synchronize operations.
There are two differences between timer/counter type 0 and type 1. Timer/counter 0 has four CC channels, and
timer/counter 1 has two CC channels. All information related to CC channels 3 and 4 is valid only for timer/counter 0.
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Only Timer/Counter 0 has the split mode feature that split it into two 8-bit Timer/Counters with four compare channels
each.
Some timer/counters have extensions to enable more specialized waveform and frequency generation. The advanced
waveform extension (AWeX) is intended for motor control and other power control applications. It enables low- and high-
side output with dead-time insertion, as well as fault protection for disabling and shutting down external drivers. It can
also generate a synchronized bit pattern across the port pins.
The advanced waveform extension can be enabled to provide extra and more advanced features for the Timer/Counter.
This are only available for Timer/Counter 0. See “AWeX – Advanced Waveform Extension” on page 37 for more details.
The high-resolution (hi-res) extension can be used to increase the waveform output resolution by four or eight times by
using an internal clock source running up to four times faster than the peripheral clock. See “Hi-Res – High Resolution
Extension” on page 38 for more details.
Figure 17-1. Overview of a Timer/Counter and closely related peripherals.
Timer/Counter
Base Counter
Prescaler
clkPER
Timer Period
Counter
Control Logic
Event
System
clkPER4
Compare/Capture Channel D
Compare/Capture Channel C
Compare/Capture Channel B
Compare/Capture Channel A
AWeX
DTI
Pattern
Generation
Fault
Dead-Time
Insertion
Capture
Comparator
Control
Protection
Waveform
Generation
Buffer
PORTC, PORTD and PORTE each has one Timer/Counter 0 and one Timer/Counter1. PORTF has one Timer/Counter
0. Notation of these are TCC0 (Time/Counter C0), TCC1, TCD0, TCD1, TCE0, TCE1 and TCF0, respectively.
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18. TC2 – Timer/Counter Type 2
18.1 Features
Eight eight-bit timer/counters
Four Low-byte timer/counter
Four High-byte timer/counter
Up to eight compare channels in each Timer/Counter 2
Four compare channels for the low-byte timer/counter
Four compare channels for the high-byte timer/counter
Waveform generation
Single slope pulse width modulation
Timer underflow interrupts/events
One compare match interrupt/event per compare channel for the low-byte timer/counter
Can be used with the event system for count control
Can be used to trigger DMA transactions
18.2 Overview
There are four Timer/Counter 2. These are realized when a Timer/Counter 0 is set in split mode. It is then a system of
two eight-bit timer/counters, each with four compare channels. This results in eight configurable pulse width modulation
(PWM) channels with individually controlled duty cycles, and is intended for applications that require a high number of
PWM channels.
The two eight-bit timer/counters in this system are referred to as the low-byte timer/counter and high-byte timer/counter,
respectively. The difference between them is that only the low-byte timer/counter can be used to generate compare
match interrupts, events and DMA triggers. The two eight-bit timer/counters have a shared clock source and separate
period and compare settings. They can be clocked and timed from the peripheral clock, with optional prescaling, or from
the event system. The counters are always counting down.
PORTC, PORTD, PORTE and PORTF each has one Timer/Counter 2. Notation of these are TCC2 (Time/Counter C2),
TCD2, TCE2 and TCF2, respectively.
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19. AWeX – Advanced Waveform Extension
19.1 Features
Waveform output with complementary output from each compare channel
Four dead-time insertion (DTI) units
8-bit resolution
Separate high and low side dead-time setting
Double buffered dead time
Optionally halts timer during dead-time insertion
Pattern generation unit creating synchronised bit pattern across the port pins
Double buffered pattern generation
Optional distribution of one compare channel output across the port pins
Event controlled fault protection for instant and predictable fault triggering
19.2 Overview
The advanced waveform extension (AWeX) provides extra functions to the timer/counter in waveform generation (WG)
modes. It is primarily intended for use with different types of motor control and other power control applications. It
enables low- and high side output with dead-time insertion and fault protection for disabling and shutting down external
drivers. It can also generate a synchronized bit pattern across the port pins.
Each of the waveform generator outputs from the timer/counter 0 are split into a complimentary pair of outputs when any
AWeX features are enabled. These output pairs go through a dead-time insertion (DTI) unit that generates the non-
inverted low side (LS) and inverted high side (HS) of the WG output with dead-time insertion between LS and HS
switching. The DTI output will override the normal port value according to the port override setting.
The pattern generation unit can be used to generate a synchronized bit pattern on the port it is connected to. In addition,
the WG output from compare channel A can be distributed to and override all the port pins. When the pattern generator
unit is enabled, the DTI unit is bypassed.
The fault protection unit is connected to the event system, enabling any event to trigger a fault condition that will disable
the AWeX output. The event system ensures predictable and instant fault reaction, and gives flexibility in the selection of
fault triggers.
The AWeX is available for TCC0. The notation of this is AWEXC.
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20. Hi-Res – High Resolution Extension
20.1 Features
Increases waveform generator resolution up to 8x (three bits)
Supports frequency, single-slope PWM, and dual-slope PWM generation
Supports the AWeX when this is used for the same timer/counter
20.2 Overview
The high-resolution (hi-res) extension can be used to increase the resolution of the waveform generation output
from a timer/counter by four or eight. It can be used for a timer/counter doing frequency, single-slope PWM, or
dual-slope PWM generation. It can also be used with the AWeX if this is used for the same timer/counter.
The hi-res extension uses the peripheral 4x clock (ClkPER4). The system clock prescalers must be configured so the
peripheral 4x clock frequency is four times higher than the peripheral and CPU clock frequency when the hi-res extension
is enabled.
There are four hi-res extensions that each can be enabled for each timer/counters pair on PORTC, PORTD, PORTE and
PORTF. The notation of these are HIRESC, HIRESD, HIRESE and HIRESF, respectively.
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21. RTC32 – 32-bit Real-Time Counter
21.1 Features
32-bit resolution
One 32-bit Compare register
One 32-bit Period register
Clear Timer on overflow
Optional Interrupt/ Event on overflow and compare match
Selectable clock reference
1.024kHz
1Hz
Isolated VBAT power domain with dynamic switch over from/to VCC power domain’
21.1.1 Overview
The 32-bit real-time counter (RTC) is a counter that typically runs continuously, including in low-power sleep modes, to
keep track of time. It can wake up the device from sleep modes and/or interrupt the device at regular intervals.
The reference clock is generated from a high accuracy 32.768kHz crystal, and the design is optimized for low power
consumption. The RTC typically operate in low power sleep modes, keeping track of time and waking up the device at
regular intervals.
The RTC input clock can be taken from a 1.024kHz or 1Hz prescaled output from the 32.768kHz reference clock. The
RTC will give a compare interrupt request and/or event when the counter value equals the Compare register value. The
RTC will give an overflow interrupt request and/or event when the counter value equals the Period register value.
Counter overflow will also reset the counter value to zero.
The 32-bit Real Time Counter (RTC) must be clocked from the 1Hz output of a 32.768kHz crystal oscillator connected
between the TOSC1 and TOSC2 pins when running from VBAT
.
Figure 21-1. Real Time Counter overview.
PER
CNT
=
=
Overflow
1.024kHz
TOSC1
TOSC2
32.768kHz
Crystal Osc
DIV32
DIV1024
Compare
Match
COMP
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22. USB – Universal Serial Bus Interface
22.1 Features
One USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface
Integrated on-chip USB transceiver, no external components needed
16 endpoint addresses with full endpoint flexibility for up to 31 endpoints
One input endpoint per endpoint address
One output endpoint per endpoint address
Endpoint address transfer type selectable to
Control transfers
Interrupt transfers
Bulk transfers
Isochronous transfers
Configurable data payload size per endpoint, up to 1023 bytes
Endpoint configuration and data buffers located in internal SRAM
Configurable location for endpoint configuration data
Configurable location for each endpoint's data buffer
Built-in direct memory access (DMA) to internal SRAM for:
Endpoint configurations
Reading and writing endpoint data
Ping-pong operation for higher throughput and double buffered operation
Input and output endpoint data buffers used in a single direction
CPU/DMA controller can update data buffer during transfer
Multipacket transfer for reduced interrupt load and software intervention
Data payload exceeding maximum packet size is transferred in one continuous transfer
No interrupts or software interaction on packet transaction level
Transaction complete FIFO for workflow management when using multiple endpoints
Tracks all completed transactions in a first-come, first-served work queue
Clock selection independent of system clock source and selection
Minimum 1.5MHz CPU clock required for low speed USB operation
Minimum 12MHz CPU clock required for full speed operation
Connection to event system
On chip debug possibilities during USB transactions
22.2 Overview
The USB module is a USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface.
The USB supports 16 endpoint addresses. All endpoint addresses have one input and one output endpoint, for a total of
31 configurable endpoints and one control endpoint. Each endpoint address is fully configurable and can be configured
for any of the four transfer types; control, interrupt, bulk, or isochronous. The data payload size is also selectable, and it
supports data payloads up to 1023 bytes.
No dedicated memory is allocated for or included in the USB module. Internal SRAM is used to keep the configuration for
each endpoint address and the data buffer for each endpoint. The memory locations used for endpoint configurations
and data buffers are fully configurable. The amount of memory allocated is fully dynamic, according to the number of
endpoints in use and the configuration of these. The USB module has built-in direct memory access (DMA), and will
read/write data from/to the SRAM when a USB transaction takes place.
To maximize throughput, an endpoint address can be configured for ping-pong operation. When done, the input and
output endpoints are both used in the same direction. The CPU or DMA controller can then read/write one data buffer
while the USB module writes/reads the others, and vice versa. This gives double buffered communication.
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Multipacket transfer enables a data payload exceeding the maximum packet size of an endpoint to be transferred as
multiple packets without software intervention. This reduces the CPU intervention and the interrupts needed for USB
transfers.
For low-power operation, the USB module can put the microcontroller into any sleep mode when the USB bus is idle and
a suspend condition is given. Upon bus resumes, the USB module can wake up the microcontroller from any sleep
mode.
PORTD has one USB. Notation of this is USB.
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23. TWI – Two-Wire Interface
23.1 Features
Two Identical two-wire interface peripherals
Bidirectional, two-wire communication interface
Phillips I2C compatible
System Management Bus (SMBus) compatible
Bus master and slave operation supported
Slave operation
Single bus master operation
Bus master in multi-master bus environment
Multi-master arbitration
Flexible slave address match functions
7-bit and general call address recognition in hardware
10-bit addressing supported
Address mask register for dual address match or address range masking
Optional software address recognition for unlimited number of addresses
Slave can operate in all sleep modes, including power-down
Slave address match can wake device from all sleep modes
100kHz and 400kHz bus frequency support
Slew-rate limited output drivers
Input filter for bus noise and spike suppression
Support arbitration between start/repeated start and data bit (SMBus)
Slave arbitration allows support for address resolve protocol (ARP) (SMBus)
23.2 Overview
The two-wire interface (TWI) is a bidirectional, two-wire communication interface. It is I2C and System Management Bus
(SMBus) compatible. The only external hardware needed to implement the bus is one pull-up resistor on each bus line.
A device connected to the bus must act as a master or a slave. The master initiates a data transaction by addressing a
slave on the bus and telling whether it wants to transmit or receive data. One bus can have many slaves and one or
several masters that can take control of the bus. An arbitration process handles priority if more than one master tries to
transmit data at the same time. Mechanisms for resolving bus contention are inherent in the protocol.
The TWI module supports master and slave functionality. The master and slave functionality are separated from each
other, and can be enabled and configured separately. The master module supports multi-master bus operation and
arbitration. It contains the baud rate generator. Both 100kHz and 400kHz bus frequency is supported. Quick command
and smart mode can be enabled to auto-trigger operations and reduce software complexity.
The slave module implements 7-bit address match and general address call recognition in hardware. 10-bit addressing is
also supported. A dedicated address mask register can act as a second address match register or as a register for
address range masking. The slave continues to operate in all sleep modes, including power-down mode. This enables
the slave to wake up the device from all sleep modes on TWI address match. It is possible to disable the address
matching to let this be handled in software instead.
The TWI module will detect START and STOP conditions, bus collisions, and bus errors. Arbitration lost, errors, collision,
and clock hold on the bus are also detected and indicated in separate status flags available in both master and slave
modes.
It is possible to disable the TWI drivers in the device, and enable a four-wire digital interface for connecting to an external
TWI bus driver. This can be used for applications where the device operates from a different VCC voltage than used by
the TWI bus.
PORTC and PORTE each has one TWI. Notation of these peripherals are TWIC and TWIE.
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24. SPI – Serial Peripheral Interface
24.1 Features
Two identical SPI peripherals
Full-duplex, three-wire synchronous data transfer
Master or slave operation
Lsb first or msb first data transfer
Eight programmable bit rates
Interrupt flag at the end of transmission
Write collision flag to indicate data collision
Wake up from idle sleep mode
Double speed master mode
24.2 Overview
The Serial Peripheral Interface (SPI) is a high-speed synchronous data transfer interface using three or four pins. It
allows fast communication between an Atmel AVR XMEGA device and peripheral devices or between several
microcontrollers. The SPI supports full-duplex communication.
A device connected to the bus must act as a master or slave. The master initiates and controls all data transactions.
PORTC and PORTD each has one SPI. Notation of these peripherals are SPIC and SPID.
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25. USART
25.1 Features
Six identical USART peripherals
Full-duplex operation
Asynchronous or synchronous operation
Synchronous clock rates up to 1/2 of the device clock frequency
Asynchronous clock rates up to 1/8 of the device clock frequency
Supports serial frames with 5, 6, 7, 8, or 9 data bits and one or two stop bits
Fractional baud rate generator
Can generate desired baud rate from any system clock frequency
No need for external oscillator with certain frequencies
Built-in error detection and correction schemes
Odd or even parity generation and parity check
Data overrun and framing error detection
Noise filtering includes false start bit detection and digital low-pass filter
Separate interrupts for
Transmit complete
Transmit data register empty
Receive complete
Multiprocessor communication mode
Addressing scheme to address a specific devices on a multidevice bus
Enable unaddressed devices to automatically ignore all frames
Master SPI mode
Double buffered operation
Operation up to 1/2 of the peripheral clock frequency
IRCOM module for IrDA compliant pulse modulation/demodulation
25.2 Overview
The universal synchronous and asynchronous serial receiver and transmitter (USART) is a fast and flexible serial
communication module. The USART supports full-duplex communication and asynchronous and synchronous operation.
The USART can be configured to operate in SPI master mode and used for SPI communication.
Communication is frame based, and the frame format can be customized to support a wide range of standards. The
USART is buffered in both directions, enabling continued data transmission without any delay between frames. Separate
interrupts for receive and transmit complete enable fully interrupt driven communication. Frame error and buffer overflow
are detected in hardware and indicated with separate status flags. Even or odd parity generation and parity check can
also be enabled.
The clock generator includes a fractional baud rate generator that is able to generate a wide range of USART baud rates
from any system clock frequencies. This removes the need to use an external crystal oscillator with a specific frequency
to achieve a required baud rate. It also supports external clock input in synchronous slave operation.
When the USART is set in master SPI mode, all USART-specific logic is disabled, leaving the transmit and receive
buffers, shift registers, and baud rate generator enabled. Pin control and interrupt generation are identical in both modes.
The registers are used in both modes, but their functionality differs for some control settings.
An IRCOM module can be enabled for one USART to support IrDA 1.4 physical compliant pulse modulation and
demodulation for baud rates up to 115.2Kbps.
PORTC, PORTD, and PORTE each has two USARTs, while PORTF has one USART only. Notation of these peripherals
are USARTC0, USARTC1, USARTD0, USARTD1, USARTE0 and USARTF0, respectively.
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26. IRCOM – IR Communication Module
26.1 Features
Pulse modulation/demodulation for infrared communication
IrDA compatible for baud rates up to 115.2Kbps
Selectable pulse modulation scheme
3/16 of the baud rate period
Fixed pulse period, 8-bit programmable
Pulse modulation disabled
Built-in filtering
Can be connected to and used by any USART
26.2 Overview
Atmel AVR XMEGA devices contain an infrared communication module (IRCOM) that is IrDA compatible for baud rates
up to 115.2Kbps. It can be connected to any USART to enable infrared pulse encoding/decoding for that USART.
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27. AES and DES Crypto Engine
27.1 Features
Data Encryption Standard (DES) CPU instruction
Advanced Encryption Standard (AES) crypto module
DES Instruction
Encryption and decryption
DES supported
Encryption/decryption in 16 CPU clock cycles per 8-byte block
AES crypto module
Encryption and decryption
Supports 128-bit keys
Supports XOR data load mode to the state memory
Encryption/decryption in 375 clock cycles per 16-byte block
27.2 Overview
The Advanced Encryption Standard (AES) and Data Encryption Standard (DES) are two commonly used standards for
cryptography. These are supported through an AES peripheral module and a DES CPU instruction, and the
communication interfaces and the CPU can use these for fast, encrypted communication and secure data storage.
DES is supported by an instruction in the AVR CPU. The 8-byte key and 8-byte data blocks must be loaded into the
register file, and then the DES instruction must be executed 16 times to encrypt/decrypt the data block.
The AES crypto module encrypts and decrypts 128-bit data blocks with the use of a 128-bit key. The key and data must
be loaded into the key and state memory in the module before encryption/decryption is started. It takes 375 peripheral
clock cycles before the encryption/decryption is done. The encrypted/encrypted data can then be read out, and an
optional interrupt can be generated. The AES crypto module also has DMA support with transfer triggers when
encryption/decryption is done and optional auto-start of encryption/decryption when the state memory is fully loaded.
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28. CRC – Cyclic Redundancy Check Generator
28.1 Features
Cyclic redundancy check (CRC) generation and checking for
Communication data
Program or data in flash memory
Data in SRAM and I/O memory space
Integrated with flash memory, DMA controller and CPU
Continuous CRC on data going through a DMA channel
Automatic CRC of the complete or a selectable range of the flash memory
CPU can load data to the CRC generator through the I/O interface
CRC polynomial software selectable to
CRC-16 (CRC-CCITT)
CRC-32 (IEEE 802.3)
Zero remainder detection
28.2 Overview
A cyclic redundancy check (CRC) is an error detection technique test algorithm used to find accidental errors in data, and
it is commonly used to determine the correctness of a data transmission, and data present in the data and program
memories. A CRC takes a data stream or a block of data as input and generates a 16- or 32-bit output that can be
appended to the data and used as a checksum. When the same data are later received or read, the device or application
repeats the calculation. If the new CRC result does not match the one calculated earlier, the block contains a data error.
The application will then detect this and may take a corrective action, such as requesting the data to be sent again or
simply not using the incorrect data.
Typically, an n-bit CRC applied to a data block of arbitrary length will detect any single error burst not longer than n bits
(any single alteration that spans no more than n bits of the data), and will detect the fraction 1-2-n of all longer error
bursts. The CRC module in Atmel AVR XMEGA devices supports two commonly used CRC polynomials; CRC-16 (CRC-
CCITT) and CRC-32 (IEEE 802.3).
CRC-16:
Polynomial:
Hex value:
x16+x12+x5+1
0x1021
CRC-32:
Polynomial:
Hex value:
x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1
0x04C11DB7
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29. ADC – 12-bit Analog to Digital Converter
29.1 Features
Two Analog to Digital Converters (ADCs)
12-bit resolution
Up to two million samples per second
Two inputs can be sampled simultaneously using ADC and 1x gain stage
Four inputs can be sampled within 1.5µs
Down to 2.5µs conversion time with 8-bit resolution
Down to 3.5µs conversion time with 12-bit resolution
Differential and single-ended input
Up to 16 single-ended inputs
16x4 differential inputs without gain
8x4 differential input with gain
Built-in differential gain stage
1/2x, 1x, 2x, 4x, 8x, 16x, 32x, and 64x gain options
Single, continuous and scan conversion options
Four internal inputs
Internal temperature sensor
DAC output
VCC voltage divided by 10
1.1V bandgap voltage
Four conversion channels with individual input control and result registers
Enable four parallel configurations and results
Internal and external reference options
Compare function for accurate monitoring of user defined thresholds
Optional event triggered conversion for accurate timing
Optional DMA transfer of conversion results
Optional interrupt/event on compare result
29.2 Overview
The ADC converts analog signals to digital values. The ADC has 12-bit resolution and is capable of converting up to two
million samples per second (msps). The input selection is flexible, and both single-ended and differential measurements
can be done. For differential measurements, an optional gain stage is available to increase the dynamic range. In
addition, several internal signal inputs are available. The ADC can provide both signed and unsigned results.
This is a pipelined ADC that consists of several consecutive stages. The pipelined design allows a high sample rate at a
low system clock frequency. It also means that a new input can be sampled and a new ADC conversion started while
other ADC conversions are still ongoing. This removes dependencies between sample rate and propagation delay.
The ADC has four conversion channels (0-3) with individual input selection, result registers, and conversion start control.
The ADC can then keep and use four parallel configurations and results, and this will ease use for applications with high
data throughput or for multiple modules using the ADC independently. It is possible to use DMA to move ADC results
directly to memory or peripherals when conversions are done.
Both internal and external reference voltages can be used. An integrated temperature sensor is available for use with the
ADC. The output from the DAC, VCC/10 and the bandgap voltage can also be measured by the ADC.
The ADC has a compare function for accurate monitoring of user defined thresholds with minimum software intervention
required.
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Figure 29-1. ADC overview.
ADC0
Compare
•
•
•
ADC15
Internal
<
>
VINP
signals
ADC0
CH0 Result
CH1 Result
CH2 Result
CH3 Result
•
•
•
Threshold
(Int Req)
ADC7
½x - 64x
ADC
ADC4
•
•
•
ADC7
Int. signals
Internal
signals
VINN
ADC0
•
•
•
Internal 1.00V
Internal VCC/1.6V
Internal VCC/2
AREFA
Reference
Voltage
ADC3
Int. signals
AREFB
Two inputs can be sampled simultaneously as both the ADC and the gain stage include sample and hold circuits, and the
gain stage has 1x gain setting.
Four inputs can be sampled within 1.5µs without any intervention by the application.
The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (propagation delay) from 3.5µs
for 12-bit to 2.5µs for 8-bit result.
ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding. This eases calculation when
the result is represented as a signed integer (signed 16-bit number).
PORTA and PORTB each has one ADC. Notation of these peripherals are ADCA and ADCB, respectively.
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30. DAC – 12-bit Digital to Analog Converter
30.1 Features
One Digital to Analog Converter (DAC)
12-bit resolution
Two independent, continuous-drive output channels
Up to one million samples per second conversion rate per DAC channel
Built-in calibration that removes:
Offset error
Gain error
Multiple conversion trigger sources
On new available data
Events from the event system
High drive capabilities and support for
Resistive loads
Capacitive loads
Combined resistive and capacitive loads
Internal and external reference options
DAC output available as input to analog comparator and ADC
Low-power mode, with reduced drive strength
Optional DMA transfer of data
30.2 Overview
The digital-to-analog converter (DAC) converts digital values to voltages. The DAC has two channels, each with 12-bit
resolution, and is capable of converting up to one million samples per second (msps) on each channel. The built-in
calibration system can remove offset and gain error when loaded with calibration values from software.
Figure 30-1. DAC overview.
DMA req
(Data Empty)
D
A
T
Output
Driver
12
CH0DATA
DAC0
A
Int.
To
AC/ADC
Trigger
Select
Enable
CTRLA
Enable
driver
Reference
voltage
AVCC
Internal 1.00V
AREFA
CTRLB
Internal Output
enable
AREFB
Trigger
Select
D
A
Output
Driver
12
CH1DATA
DAC1
T
A
DMA req
(Data Empty)
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A DAC conversion is automatically started when new data to be converted are available. Events from the event system
can also be used to trigger a conversion, and this enables synchronized and timed conversions between the DAC and
other peripherals, such as a timer/counter. The DMA controller can be used to transfer data to the DAC.
The DAC has high drive strength, and is capable of driving both resistive and capacitive loads, as well as loads which
combine both. A low-power mode is available, which will reduce the drive strength of the output. Internal and external
voltage references can be used. The DAC output is also internally available for use as input to the analog comparator or
ADC.
PORTB has one DAC. Notation of this peripheral is DACB.
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31. AC – Analog Comparator
31.1 Features
Four Analog Comparators (AC)
Selectable propagation delay versus current consumption
Selectable hysteresis
No
Small
Large
Analog comparator output available on pin
Flexible input selection
All pins on the port
Output from the DAC
Bandgap reference voltage
A 64-level programmable voltage scaler of the internal VCC voltage
Interrupt and event generation on:
Rising edge
Falling edge
Toggle
Window function interrupt and event generation on:
Signal above window
Signal inside window
Signal below window
Constant current source with configurable output pin selection
31.2 Overview
The analog comparator (AC) compares the voltage levels on two inputs and gives a digital output based on this
comparison. The analog comparator may be configured to generate interrupt requests and/or events upon several
different combinations of input change.
Two important properties of the analog comparator’s dynamic behavior are: hysteresis and propagation delay. Both of
these parameters may be adjusted in order to achieve the optimal operation for each application.
The input selection includes analog port pins, several internal signals, and a 64-level programmable voltage scaler. The
analog comparator output state can also be output on a pin for use by external devices.
A constant current source can be enabled and output on a selectable pin. This can be used to replace, for example,
external resistors used to charge capacitors in capacitive touch sensing applications.
The analog comparators are always grouped in pairs on each port. These are called analog comparator 0 (AC0) and
analog comparator 1 (AC1). They have identical behavior, but separate control registers. Used as pair, they can be set in
window mode to compare a signal to a voltage range instead of a voltage level.
PORTA and PORTB each has one AC pair. Notations are ACA and ACB, respectively.
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Figure 31-1. Analog comparator overview.
Pin Input
+
AC0OUT
Pin Input
-
Hysteresis
DAC
Enable
Interrupt
Interrupts
Events
Interrupt
Mode
Sensititivity
Control
&
Voltage
Scaler
ACnMUXCTRL
ACnCTRL
WINCTRL
Window
Function
Enable
Bandgap
Pin Input
Hysteresis
+
-
AC1OUT
Pin Input
The window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in
Figure 31-2.
Figure 31-2. Analog comparator window function.
+
AC0
Upper limit of window
-
Interrupts
Interrupt
Input signal
sensitivity
Events
control
+
AC1
Lower limit of window
-
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32. Programming and Debugging
32.1 Features
Programming
External programming through PDI or JTAG interfaces
Minimal protocol overhead for fast operation
Built-in error detection and handling for reliable operation
Boot loader support for programming through any communication interface
Debugging
Nonintrusive, real-time, on-chip debug system
No software or hardware resources required from device except pin connection
Program flow control
Go, Stop, Reset, Step Into, Step Over, Step Out, Run-to-Cursor
Unlimited number of user program breakpoints
Unlimited number of user data breakpoints, break on:
Data location read, write, or both read and write
Data location content equal or not equal to a value
Data location content is greater or smaller than a value
Data location content is within or outside a range
No limitation on device clock frequency
Program and Debug Interface (PDI)
Two-pin interface for external programming and debugging
Uses the Reset pin and a dedicated pin
No I/O pins required during programming or debugging
JTAG interface
Four-pin, IEEE Std. 1149.1 compliant interface for programming and debugging
Boundary scan capabilities according to IEEE Std. 1149.1 (JTAG)
32.2 Overview
The Program and Debug Interface (PDI) is an Atmel proprietary interface for external programming and on-chip
debugging of a device.
The PDI supports fast programming of nonvolatile memory (NVM) spaces; flash, EEPOM, fuses, lock bits, and the user
signature row.
Debug is supported through an on-chip debug system that offers nonintrusive, real-time debug. It does not require any
software or hardware resources except for the device pin connection. Using the Atmel tool chain, it offers complete
program flow control and support for an unlimited number of program and complex data breakpoints. Application debug
can be done from a C or other high-level language source code level, as well as from an assembler and disassembler
level.
Programming and debugging can be done through two physical interfaces. The primary one is the PDI physical layer,
which is available on all devices. This is a two-pin interface that uses the Reset pin for the clock input (PDI_CLK) and one
other dedicated pin for data input and output (PDI_DATA). A JTAG interface is also available on most devices, and this
can be used for programming and debugging through the four-pin JTAG interface. The JTAG interface is IEEE Std.
1149.1 compliant, and supports boundary scan. Any external programmer or on-chip debugger/emulator can be directly
connected to either of these interfaces. Unless otherwise stated, all references to the PDI assume access through the
PDI physical layer.
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33. Pinout and Pin Functions
The device pinout is shown in “Pinout/Block Diagram” on page 3. In addition to general purpose I/O functionality, each
pin can have several alternate functions. This will depend on which peripheral is enabled and connected to the actual pin.
Only one of the pin functions can be used at time.
33.1 Alternate Pin Function Description
The tables below show the notation for all pin functions available and describe its function.
33.1.1 Operation/Power Supply
VCC
Digital supply voltage
Analog supply voltage
Battery Backup Module supply voltage
Ground
AVCC
VBAT
GND
33.1.2 Port Interrupt functions
SYNC
Port pin with full synchronous and limited asynchronous interrupt function
ASYNC
Port pin with full synchronous and full asynchronous interrupt function
33.1.3 Analog functions
ACn
Analog Comparator input pin n
Analog Comparator n Output
ACnOUT
ADCn
DACn
AREF
Analog to Digital Converter input pin n
Digital to Analog Converter output pin n
Analog Reference input pin
33.1.4 Timer/Counter and AWEX functions
OCnxLS
OCnxHS
Output Compare Channel x Low Side for Timer/Counter n
Output Compare Channel x High Side for Timer/Counter n
33.1.5 Communication functions
SCL
Serial Clock for TWI
SDA
Serial Data for TWI
SCLIN
SCLOUT
SDAIN
SDAOUT
XCKn
Serial Clock In for TWI when external driver interface is enabled
Serial Clock Out for TWI when external driver interface is enabled
Serial Data In for TWI when external driver interface is enabled
Serial Data Out for TWI when external driver interface is enabled
Transfer Clock for USART n
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RXDn
TXDn
SS
Receiver Data for USART n
Transmitter Data for USART n
Slave Select for SPI
MOSI
MISO
SCK
D-
Master Out Slave In for SPI
Master In Slave Out for SPI
Serial Clock for SPI
Data- for USB
D+
Data+ for USB
33.1.6 Oscillators, Clock and Event
TOSCn
XTALn
Timer Oscillator pin n
Input/Output for Oscillator pin n
Peripheral Clock Output
Event Channel Output
CLKOUT
EVOUT
RTCOUT
RTC Clock Source Output
33.1.7 Debug/System functions
RESET
PDI_CLK
PDI_DATA
TCK
Reset pin
Program and Debug Interface Clock pin
Program and Debug Interface Data pin
JTAG Test Clock
TDI
JTAG Test Data In
TDO
JTAG Test Data Out
TMS
JTAG Test Mode Select
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33.2 Alternate Pin Functions
The tables below show the primary/default function for each pin on a port in the first column, the pin number in the
second column, and then all alternate pin functions in the remaining columns. The head row shows what peripheral that
enable and use the alternate pin functions.
For better flexibility, some alternate functions also have selectable pin locations for their functions, this is noted under the
first table where this apply.
Table 33-1. Port A - alternate functions.
PORT A
PIN #
INTERRUPT
ADCAPOS/
GAINPOS
ADCB
POS
ADCA
NEG
ADCA
GAINNEG
ACA
POS
ACA
NEG
ACA
OUT
REFA
GND
AVCC
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
60
61
62
63
64
1
SYNC
SYNC
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
ADC0
ADC1
ADC2
ADC3
AC0
AC1
AC2
AC3
AC4
AC5
AC6
AC0
AC1
AREF
SYNC/ASYNC
SYNC
ADC10
ADC11
ADC12
ADC13
ADC14
ADC15
AC3
AC5
AC7
2
SYNC
ADC4
ADC5
ADC6
ADC7
3
SYNC
4
SYNC
AC1OUT
AC0OUT
5
SYNC
Table 33-2. Port B - alternate functions.
PORT B
PIN #
INTERRUPT
ADCBPOS/
GAINPOS
ADCB
NEG
ADCB
GAINNEG
ACB
POS
ACB
NEG
ACB
OUT
DACB
REFB
JTAG
ADCA POS
ADC8
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
GND
VCC
6
7
SYNC
SYNC
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
ADC0
ADC1
ADC2
ADC3
AC0
AC1
AC2
AC3
AC4
AC5
AC6
AC0
AC1
AREF
ADC9
8
SYNC/ASYNC
SYNC
ADC10
ADC11
ADC12
ADC13
ADC14
ADC15
DAC0
DAC1
9
AC3
AC5
AC7
10
11
12
13
14
15
SYNC
ADC4
ADC5
ADC6
ADC7
TMS
TDI
SYNC
SYNC
AC1OUT
AC0OUT
TCK
TDO
SYNC
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Table 33-3. Port C - alternate functions.
TCC0
USARTC0
CLOCKOUT
EVENTOUT
(1)(2)
(3)
(6)
PORT C
PC0
PIN #
16
INTERRUPT
SYNC
AWEXC
OC0ALS
OC0AHS
OC0BLS
OC0BHS
OC0CLS
TCC1
USARTC1
SPIC (4)
TWIC
SDA
SCL
(5)
OC0A
OC0B
OC0C
OC0D
PC1
17
SYNC
XCK0
RXD0
TXD0
PC2
18
SYNC/ASYNC
SYNC
PC3
19
PC4
20
SYNC
OC1A
OC1B
SS
OC0CH
S
PC5
PC6
PC7
21
22
23
SYNC
SYNC
SYNC
XCK1
RXD1
TXD1
MOSI
MISO
SCK
OC0DLS
clkRTC
clkPER
OC0DH
S
EVOUT
GND
VCC
24
25
Notes:
1. Pin mapping of all TC0 can optionally be moved to high nibble of port.
2. If TC0 is configured as TC2 all eight pins can be used for PWM output.
3. Pin mapping of all USART0 can optionally be moved to high nibble of port.
4. Pins MOSI and SCK for all SPI can optionally be swapped.
5. CLKOUT can optionally be moved between port C, D and E and between pin 4 and 7.
6. EVOUT can optionally be moved between port C, D and E and between pin 4 and 7.
Table 33-4. Port D - alternate functions.
PORT D
PD0
PIN #
26
INTERRUPT
SYNC
TCD0
OC0A
OC0B
OC0C
OC0D
TCD1
USBD
USARTD0
USARTD1
SPID
CLOCKOUT
EVENTOUT
PD1
27
SYNC
XCK0
RXD0
TXD0
PD2
28
SYNC/ASYNC
SYNC
PD3
29
PD4
30
SYNC
OC1A
OC1B
SS
PD5
31
SYNC
XCK1
RXD1
TXD1
MOSI
MISO
SCK
PD6
32
SYNC
D-
PD7
33
SYNC
D+
clkPER
EVOUT
GND
VCC
34
35
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Table 33-5. Port E - alternate functions.
PORT E
PE0
PIN #
36
INTERRUPT
SYNC
TCE0
OC0A
OC0B
OC0C
OC0D
TCE1
USARTE0
TWIE
SDA
SCL
PE1
37
SYNC
XCK0
RXD0
TXD0
PE2
38
SYNC/ASYNC
SYNC
PE3
39
PE4
40
SYNC
OC1A
OC1B
PE5
41
SYNC
TOSC2
TOSC1
GND
VCC
42
43
44
45
Table 33-6. Port F - alternate functions.
PORT F
PF0
PIN #
46
INTERRUPT
SYNC
TCF0
USARTF0
OC0A
OC0B
PF1
47
SYNC
XCK0
RXD0
TXD0
SYNC/ASYN
C
PF2
48
OC0C
OC0D
PF3
49
50
51
52
53
54
55
SYNC
SYNC
PF4
VBAT
GND
VCC
PF6
SYNC
SYNC
PF7
Table 33-7. Port R - alternate functions.
PORT R
PDI
PIN #
56
INTERRUPT
PDI
XTAL
PDI_DATA
PDI_CLOCK
RESET
PRO
57
58
SYNC
SYNC
XTAL2
XTAL1
PR1
59
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34. Peripheral Module Address Map
The address maps show the base address for each peripheral and module in Atmel AVR XMEGA A3BU. For complete
register description and summary for each peripheral module, refer to the XMEGA AU Manual.
Table 34-1. Peripheral module address map.
Base Address
Name
Description
0x0000
GPIO
General purpose IO registers
0x0010
0x0014
0x0018
0x001C
0x0030
0x0040
0x0048
0x0050
0x0060
0x0068
0x0070
0x0078
0x0080
0x0090
0x00A0
0x00B0
0x00C0
0x00D0
0x00F0
0x0100
0x0180
0x01C0
0x0200
0x0240
0x0320
0x0380
0x0390
0x0420
0x0480
0x04A0
0x04D0
0x0600
0x0620
VPORT0
VPORT1
VPORT2
VPORT3
CPU
Virtual Port 0
Virtual Port 1
Virtual Port 2
Virtual Port 2
CPU
CLK
Clock Control
SLEEP
OSC
Sleep Controller
Oscillator Control
DFLLRC32M
DFLLRC2M
PR
DFLL for the 32MHz internal oscillator
DFLL for the 2MHz internal oscillator
Power Reduction
RST
Reset Controller
WDT
Watch-Dog Timer
MCU
MCU Control
PMIC
Programmable Multilevel Interrupt Controller
Port Configuration
PORTCFG
AES
AES module
CRC
CRC generator
VBAT
VBAT Battery Backup module
DMA Controller
DMA
EVSYS
NVM
Event System
Non Volatile Memory (NVM) Controller
Analog to Digital Converter on port A
Analog to Digital Converter on port B
Digital to Analog Converter on port B
Analog Comparator pair on port A
Analog Comparator pair on port B
32-bit Real Time Counter
Two-wire Interface on port C
Two-wire Interface on port E
USB Device
ADCA
ADCB
DACB
ACA
ACB
RTC32
TWIC
TWIE
USBD
PORTA
PORTB
Port A
Port B
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Base Address
Name
Description
0x0640
PORTC
Port C
0x0660
0x0680
0x06A0
0x07E0
0x0800
0x0840
0x0880
0x0890
0x08A0
0x08B0
0x08C0
0x08F8
0x0900
0x0940
0x0990
0x09A0
0x09B0
0x09C0
0x0A00
0x0A40
0x0A80
0x0A90
0x0AA0
0x0B00
0x0B90
0x0BA0
PORTD
PORTE
PORTF
PORTR
TCC0
Port D
Port E
Port F
Port R
Timer/Counter 0 on port C
Timer/Counter 1 on port C
Advanced Waveform Extension on port C
High Resolution Extension on port C
USART 0 on port C
TCC1
AWEXC
HIRESC
USARTC0
USARTC1
SPIC
USART 1 on port C
Serial Peripheral Interface on port C
Infrared Communication Module
Timer/Counter 0 on port D
Timer/Counter 1 on port D
High Resolution Extension on port D
USART 0 on port D
IRCOM
TCD0
TCD1
HIRESD
USARTD0
USARTD1
SPID
USART 1 on port D
Serial Peripheral Interface on port D
Timer/Counter 0 on port E
Timer/Counter 1 on port E
Advanced Waveform Extension on port E
High Resolution Extension on port E
USART 0 on port E
TCE0
TCE1
AWEXE
HIRESE
USARTE0
TCF0
Timer/Counter 0 on port F
High Resolution Extension on port F
USART 0 on port F
HIRESF
USARTF0
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35. Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
Arithmetic and Logic Instructions
ADD
ADC
ADIW
SUB
Rd, Rr
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd
Add without Carry
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd + Rr
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,C,N,V,S
Z,C,N,V,S,H
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
None
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
1/2
Add with Carry
Rd + Rr + C
Rd + 1:Rd + K
Rd - Rr
Add Immediate to Word
Subtract without Carry
Subtract Immediate
Subtract with Carry
Subtract Immediate with Carry
Subtract Immediate from Word
Logical AND
SUBI
SBC
Rd - K
Rd - Rr - C
Rd - K - C
Rd + 1:Rd - K
Rd Rr
SBCI
SBIW
AND
ANDI
OR
Rd + 1:Rd
Rd
Logical AND with Immediate
Logical OR
Rd
Rd K
Rd
Rd v Rr
ORI
Logical OR with Immediate
Exclusive OR
Rd
Rd v K
EOR
COM
NEG
SBR
Rd
Rd Rr
One’s Complement
Two’s Complement
Set Bit(s) in Register
Clear Bit(s) in Register
Increment
Rd
$FF - Rd
Rd
Rd
$00 - Rd
Rd,K
Rd,K
Rd
Rd
Rd v K
CBR
INC
Rd
Rd ($FFh - K)
Rd + 1
Rd
DEC
TST
Rd
Decrement
Rd
Rd - 1
Rd
Test for Zero or Minus
Clear Register
Rd
Rd Rd
CLR
Rd
Rd
Rd Rd
SER
Rd
Set Register
Rd
$FF
MUL
MULS
MULSU
FMUL
FMULS
FMULSU
DES
Rd,Rr
Rd,Rr
Rd,Rr
Rd,Rr
Rd,Rr
Rd,Rr
K
Multiply Unsigned
R1:R0
R1:R0
R1:R0
R1:R0
R1:R0
R1:R0
Rd x Rr (UU)
Rd x Rr (SS)
Rd x Rr (SU)
Rd x Rr<<1 (UU)
Rd x Rr<<1 (SS)
Rd x Rr<<1 (SU)
Z,C
Multiply Signed
Z,C
Multiply Signed with Unsigned
Fractional Multiply Unsigned
Fractional Multiply Signed
Fractional Multiply Signed with Unsigned
Data Encryption
Z,C
Z,C
Z,C
Z,C
if (H = 0) then R15:R0
else if (H = 1) then R15:R0
Encrypt(R15:R0, K)
Decrypt(R15:R0, K)
Branch instructions
RJMP
IJMP
k
Relative Jump
PC
PC + k + 1
None
None
2
2
Indirect Jump to (Z)
PC(15:0)
PC(21:16)
Z,
0
EIJMP
Extended Indirect Jump to (Z)
PC(15:0)
PC(21:16)
Z,
EIND
None
2
JMP
k
k
Jump
PC
PC
k
None
None
3
RCALL
Relative Call Subroutine
PC + k + 1
2 / 3 (1)
XMEGA A3BU [DATASHEET]
62
8362F–AVR–02/2013
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ICALL
Indirect Call to (Z)
PC(15:0)
PC(21:16)
Z,
0
None
2 / 3 (1)
EICALL
Extended Indirect Call to (Z)
PC(15:0)
PC(21:16)
Z,
EIND
None
3 (1)
CALL
RET
k
call Subroutine
PC
PC
k
None
None
I
3 / 4 (1)
4 / 5 (1)
4 / 5 (1)
1 / 2 / 3
1
Subroutine Return
STACK
STACK
PC + 2 or 3
RETI
Interrupt Return
PC
CPSE
CP
Rd,Rr
Compare, Skip if Equal
Compare
if (Rd = Rr) PC
None
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
Rd,Rr
Rd - Rr
CPC
Rd,Rr
Compare with Carry
Rd - Rr - C
1
CPI
Rd,K
Compare with Immediate
Skip if Bit in Register Cleared
Skip if Bit in Register Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
Rd - K
1
SBRC
SBRS
SBIC
SBIS
Rr, b
if (Rr(b) = 0) PC
if (Rr(b) = 1) PC
if (I/O(A,b) = 0) PC
If (I/O(A,b) =1) PC
if (SREG(s) = 1) then PC
if (SREG(s) = 0) then PC
if (Z = 1) then PC
if (Z = 0) then PC
if (C = 1) then PC
if (C = 0) then PC
if (C = 0) then PC
if (C = 1) then PC
if (N = 1) then PC
if (N = 0) then PC
if (N V= 0) then PC
if (N V= 1) then PC
if (H = 1) then PC
if (H = 0) then PC
if (T = 1) then PC
if (T = 0) then PC
if (V = 1) then PC
if (V = 0) then PC
if (I = 1) then PC
if (I = 0) then PC
PC + 2 or 3
PC + 2 or 3
PC + 2 or 3
PC + 2 or 3
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
1 / 2 / 3
1 / 2 / 3
2 / 3 / 4
2 / 3 / 4
1 / 2
Rr, b
A, b
A, b
s, k
s, k
k
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRMI
BRPL
BRGE
BRLT
BRHS
BRHC
BRTS
BRTC
BRVS
BRVC
BRIE
BRID
1 / 2
1 / 2
k
Branch if Not Equal
1 / 2
k
Branch if Carry Set
1 / 2
k
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
1 / 2
k
1 / 2
k
1 / 2
k
Branch if Minus
1 / 2
k
Branch if Plus
1 / 2
k
Branch if Greater or Equal, Signed
Branch if Less Than, Signed
Branch if Half Carry Flag Set
Branch if Half Carry Flag Cleared
Branch if T Flag Set
1 / 2
k
1 / 2
k
1 / 2
k
1 / 2
k
1 / 2
k
Branch if T Flag Cleared
Branch if Overflow Flag is Set
Branch if Overflow Flag is Cleared
Branch if Interrupt Enabled
Branch if Interrupt Disabled
1 / 2
k
1 / 2
k
1 / 2
k
1 / 2
k
1 / 2
Data transfer instructions
MOV
MOVW
LDI
Rd, Rr
Rd, Rr
Rd, K
Copy Register
Rd
Rd+1:Rd
Rd
Rr
None
None
None
1
1
1
Copy Register Pair
Load Immediate
Rr+1:Rr
K
XMEGA A3BU [DATASHEET]
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8362F–AVR–02/2013
Mnemonics
Operands
Rd, k
Description
Operation
Flags
None
None
None
#Clocks
2 (1)(2)
LDS
LD
Load Direct from data space
Load Indirect
Rd
Rd
(k)
Rd, X
(X)
1 (1)(2)
LD
Rd, X+
Load Indirect and Post-Increment
Rd
X
(X)
X + 1
1 (1)(2)
LD
Rd, -X
Load Indirect and Pre-Decrement
X X - 1,
Rd (X)
X - 1
(X)
None
2 (1)(2)
LD
LD
Rd, Y
Load Indirect
Rd (Y)
(Y)
None
None
1 (1)(2)
1 (1)(2)
Rd, Y+
Load Indirect and Post-Increment
Rd
Y
(Y)
Y + 1
LD
Rd, -Y
Load Indirect and Pre-Decrement
Y
Rd
Y - 1
(Y)
None
2 (1)(2)
LDD
LD
Rd, Y+q
Rd, Z
Load Indirect with Displacement
Load Indirect
Rd
Rd
(Y + q)
(Z)
None
None
None
2 (1)(2)
1 (1)(2)
1 (1)(2)
LD
Rd, Z+
Load Indirect and Post-Increment
Rd
Z
(Z),
Z+1
LD
Rd, -Z
Load Indirect and Pre-Decrement
Z
Rd
Z - 1,
(Z)
None
2 (1)(2)
LDD
STS
ST
Rd, Z+q
k, Rr
Load Indirect with Displacement
Store Direct to Data Space
Store Indirect
Rd
(k)
(X)
(Z + q)
Rd
None
None
None
None
2 (1)(2)
2 (1)
X, Rr
Rr
1 (1)
ST
X+, Rr
Store Indirect and Post-Increment
(X)
X
Rr,
X + 1
1 (1)
ST
-X, Rr
Store Indirect and Pre-Decrement
X
(X)
X - 1,
Rr
None
2 (1)
ST
ST
Y, Rr
Store Indirect
(Y)
Rr
None
None
1 (1)
1 (1)
Y+, Rr
Store Indirect and Post-Increment
(Y)
Y
Rr,
Y + 1
ST
-Y, Rr
Store Indirect and Pre-Decrement
Y
(Y)
Y - 1,
Rr
None
2 (1)
STD
ST
Y+q, Rr
Z, Rr
Store Indirect with Displacement
Store Indirect
(Y + q)
(Z)
Rr
Rr
None
None
None
2 (1)
1 (1)
1 (1)
ST
Z+, Rr
Store Indirect and Post-Increment
(Z)
Z
Rr
Z + 1
ST
-Z, Rr
Store Indirect and Pre-Decrement
Store Indirect with Displacement
Load Program Memory
Z
(Z + q)
R0
Z - 1
Rr
None
None
None
None
None
2 (1)
2 (1)
3
STD
LPM
LPM
LPM
Z+q,Rr
(Z)
Rd, Z
Load Program Memory
Rd
(Z)
3
Rd, Z+
Load Program Memory and Post-Increment
Rd
Z
(Z),
Z + 1
3
ELPM
ELPM
ELPM
Extended Load Program Memory
Extended Load Program Memory
R0
Rd
(RAMPZ:Z)
(RAMPZ:Z)
None
None
None
3
3
3
Rd, Z
Rd, Z+
Extended Load Program Memory and Post-
Increment
Rd
Z
(RAMPZ:Z),
Z + 1
SPM
SPM
Store Program Memory
(RAMPZ:Z)
R1:R0
None
None
-
-
Z+
Store Program Memory and Post-Increment
by 2
(RAMPZ:Z)
Z
R1:R0,
Z + 2
XMEGA A3BU [DATASHEET]
64
8362F–AVR–02/2013
Mnemonics
IN
Operands
Rd, A
A, Rr
Rr
Description
Operation
Flags
None
None
None
None
None
#Clocks
In From I/O Location
Out To I/O Location
Push Register on Stack
Pop Register from Stack
Exchange RAM location
Rd
I/O(A)
STACK
Rd
I/O(A)
Rr
1
1
OUT
PUSH
POP
Rr
1 (1)
2 (1)
2
Rd
STACK
XCH
Z, Rd
Temp
Rd
(Z)
Rd,
(Z),
Temp
LAS
LAC
LAT
Z, Rd
Z, Rd
Z, Rd
Load and Set RAM location
Load and Clear RAM location
Load and Toggle RAM location
Temp
Rd
(Z)
Rd,
(Z),
Temp v (Z)
None
None
None
2
2
2
Temp
Rd
(Z)
Rd,
(Z),
($FFh – Rd) • (Z)
Temp
Rd
(Z)
Rd,
(Z),
Temp (Z)
Bit and bit-test instructions
LSL
Rd
Rd
Rd
Rd
Logical Shift Left
Rd(n+1)
Rd(0)
C
Rd(n),
0,
Rd(7)
Z,C,N,V,H
Z,C,N,V
1
1
1
1
LSR
ROL
ROR
Logical Shift Right
Rd(n)
Rd(7)
C
Rd(n+1),
0,
Rd(0)
Rotate Left Through Carry
Rotate Right Through Carry
Rd(0)
Rd(n+1)
C
C,
Rd(n),
Rd(7)
Z,C,N,V,H
Z,C,N,V
Rd(7)
Rd(n)
C
C,
Rd(n+1),
Rd(0)
ASR
SWAP
BSET
BCLR
SBI
Rd
Arithmetic Shift Right
Swap Nibbles
Rd(n)
Rd(n+1), n=0..6
Z,C,N,V
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Rd
Rd(3..0)
Rd(7..4)
None
s
Flag Set
SREG(s)
1
SREG(s)
s
Flag Clear
SREG(s)
0
SREG(s)
A, b
A, b
Rr, b
Rd, b
Set Bit in I/O Register
Clear Bit in I/O Register
Bit Store from Register to T
Bit load from T to Register
Set Carry
I/O(A, b)
1
None
CBI
I/O(A, b)
0
None
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
T
Rr(b)
T
1
T
Rd(b)
None
C
C
N
N
Z
Z
I
C
C
N
N
Z
Z
I
Clear Carry
0
Set Negative Flag
Clear Negative Flag
Set Zero Flag
1
0
1
Clear Zero Flag
0
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
1
CLI
I
0
I
SES
CLS
S
S
1
S
S
0
XMEGA A3BU [DATASHEET]
65
8362F–AVR–02/2013
Mnemonics
SEV
Operands
Description
Operation
Flags
#Clocks
Set Two’s Complement Overflow
Clear Two’s Complement Overflow
Set T in SREG
V
V
T
1
0
1
0
1
0
V
V
T
T
H
H
1
1
1
1
1
1
CLV
SET
CLT
Clear T in SREG
T
SEH
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
H
H
CLH
MCU control instructions
BREAK
NOP
Break
(See specific descr. for BREAK)
None
None
None
None
1
1
1
1
No Operation
Sleep
SLEEP
WDR
(see specific descr. for Sleep)
(see specific descr. for WDR)
Watchdog Reset
Notes:
1. Cycle times for Data memory accesses assume internal memory accesses, and are not valid for accesses via the external RAM interface.
2. One extra cycle must be added when accessing Internal SRAM.
XMEGA A3BU [DATASHEET]
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36. Packaging information
36.1 64A
PIN 1
e
B
PIN 1 IDENTIFIER
E1
E
D1
D
C
0°~7°
A2
A
A1
L
COMMON DIMENSIONS
(Unit of measure = mm)
MIN
–
MAX
1.20
NOM
–
NOTE
SYMBOL
A
A1
A2
D
0.05
0.95
15.75
13.90
15.75
13.90
0.30
0.09
0.45
–
0.15
1.00
16.00
14.00
16.00
14.00
–
1.05
16.25
D1
E
14.10 Note 2
16.25
Notes:
E1
B
14.10 Note 2
0.45
1.This package conforms to JEDEC reference MS-026, Variation AEB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
C
–
0.20
3. Lead coplanarity is 0.10mm maximum.
L
–
0.75
e
0.80 TYP
2010-10-20
DRAWING NO. REV.
64A
TITLE
2325 Orchard Parkway
San Jose, CA 95131
64A, 64-lead, 14 x 14mm Body Size, 1.0mm Body Thickness,
0.8mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
C
XMEGA A3BU [DATASHEET]
67
8362F–AVR–02/2013
36.2 64M2
D
Marked Pin# 1 ID
E
SEATING PLANE
C
A1
A3
TOP VIEW
A
K
0.08
C
L
Pin #1 Corner
SIDE VIEW
D2
1
2
3
Pin #1
Triangle
Option A
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
0.80
–
MAX
1.00
0.05
NOM
NOTE
SYMBOL
E2
Option B
Option C
Pin #1
A
0.90
Chamfer
(C 0.30)
A1
A3
0.02
0.20 REF
b
0.18
8.90
7.50
8.90
0.25
9.00
7.65
9.00
0.30
9.10
7.80
9.10
D
D2
E
Pin #1
Notch
(0.20 R)
K
e
b
BOTTOM VIEW
E2
e
7.50
7.65
0.50 BSC
0.40
7.80
L
0.35
0.20
0.45
0.40
0.27
K
1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD.
2. Dimension and tolerance conform to ASMEY14.5M-1994.
Notes:
2011-10-28
TITLE
DRAWING NO. REV.
64M2
2325 Orchard Parkway
San Jose, CA 95131
64M2, 64-pad, 9 x 9 x 1.0mm Bod y, Lead Pitch 0.50mm ,
Quad Flat No Lead
E
R
7.65mm Exposed Pad,
Package (QFN)
XMEGA A3BU [DATASHEET]
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8362F–AVR–02/2013
37. Electrical Characteristics
All typical values are measured at T = 25C unless other temperature condition is given. All minimum and maximum
values are valid across operating temperature and voltage unless other conditions are given.
Note: For devices that are not available yet, preliminary values in this datasheet are based on simulations, and/or
characterization of similar AVR XMEGA microcontrollers. After the device is characterized the final values will be
available, hence existing values can change. Missing minimum and maximum values will be available after the
device is characterized.
37.1 Absolute Maximum Ratings
Stresses beyond those listed in Table 37-1 on page 69 under may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or other conditions beyond those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Table 37-1. Absolute maximum ratings.
Symbol
VCC
IVCC
IGND
VPIN
IPIN
Parameter
Condition
Min.
Typ.
Max.
4
Units
Power supply voltage
Current into a VCC pin
Current out of a Gnd pin
Pin voltage with respect to Gnd and VCC
I/O pin sink/source current
Storage temperature
-0.3
V
200
mA
200
-0.5
-25
-65
VCC+0.5
25
V
mA
TA
150
°C
Tj
Junction temperature
150
37.2 General Operating Ratings
The device must operate within the ratings listed in Table 37-2 in order for all other electrical characteristics and typical
characteristics of the device to be valid.
Table 37-2. General operating conditions.
Symbol
VCC
Parameter
Condition
Min.
1.60
1.60
-40
Typ.
Max.
3.6
Units
Power supply voltage
Analog supply voltage
Temperature range
Junction temperature
V
AVCC
TA
3.6
85
°C
Tj
-40
105
XMEGA A3BU [DATASHEET]
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8362F–AVR–02/2013
Table 37-3. Operating voltage and frequency.
Symbol
Parameter
Condition
VCC = 1.6V
VCC = 1.8V
VCC = 2.7V
VCC = 3.6V
Min.
Typ.
Max.
12
Units
0
0
0
0
12
ClkCPU
CPU clock frequency
MHz
32
32
The maximum CPU clock frequency depends on VCC. As shown in Figure 37-1 on page 70 the Frequency vs. VCC curve
is linear between 1.8V < VCC < 2.7V.
Figure 37-1. Maximum frequency vs. VCC
.
MHz
32
Safe Operating Area
12
V
1.6
1.8
2.7
3.6
XMEGA A3BU [DATASHEET]
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8362F–AVR–02/2013
37.3 Current consumption
Table 37-4. Current consumption for Active mode and sleep modes.
Symbol Parameter
Condition
Min.
Typ.
120
270
350
697
658
1.1
Max.
Units
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
32kHz, Ext. Clk
µA
1MHz, Ext. Clk
Active Power
consumption (1)
700
1.4
15
2MHz, Ext. Clk
32MHz, Ext. Clk
32kHz, Ext. Clk
VCC = 3.0V
mA
10.6
4.3
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
4.8
78
1MHz, Ext. Clk
2MHz, Ext. Clk
µA
Idle Power
150
150
290
4.7
consumption (1)
350
600
7.0
1.0
5.0
ICC
VCC = 3.0V
VCC = 3.0V
32MHz, Ext. Clk
T = 25°C
mA
0.1
T = 85°C
1.8
Power-down power
consumption
WDT and Sampled BOD enabled,
T = 25°C
1.3
3.1
3.0
7.0
VCC = 3.0V
WDT and Sampled BOD enabled,
T = 85°C
µA
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
VCC = 3.0V
0.6
0.7
0.8
1.0
2
2
3
3
RTC from 1.024kHz low power
32.768kHz TOSC, T = 25°C
Power-save power
consumption (2)
RTC from low power 32.768kHz
TOSC, T = 25°C
Current through RESET pin
subtracted
Reset power consumption
VCC = 3.0V
250
Notes:
1. All Power Reduction Registers set.
2. Maximum limits are based on characterization, and not tested in production.
XMEGA A3BU [DATASHEET]
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Table 37-5. Current consumption for modules and peripherals.
Symbol Parameter
Condition (1)
Min.
Typ.
1.0
27
Max.
Units
ULP oscillator
32.768kHz int. oscillator
85
2MHz int. oscillator
32MHz int. oscillator
DFLL enabled with 32.768kHz int. osc. as reference
DFLL enabled with 32.768kHz int. osc. as reference
115
270
460
µA
20x multiplication factor,
PLL
220
32MHz int. osc. DIV4 as reference
Watchdog timer
1.0
138
1.2
100
95
Continuous mode
BOD
Sampled mode, includes ULP oscillator
Internal 1.0V reference
Temperature sensor
ICC
3.0
2.6
2.1
1.6
1.9
CURRLIMIT = LOW
CURRLIMIT = MEDIUM
CURRLIMIT = HIGH
Normal mode
250ksps
ADC
VREF = Ext ref
mA
250ksps
DAC
AC
VREF = Ext ref
No load
Low Power mode
1.1
High Speed Mode
Low Power Mode
330
130
115
16
DMA
615KBps between I/O registers and SRAM
µA
Timer/Counter
USART
Rx and Tx enabled, 9600 BAUD
2.5
4
Flash memory and EEPROM programming
mA
Note:
1. All parameters measured as the difference in current consumption between module enabled and disabled. All data at VCC = 3.0V, ClkSYS = 1MHz external clock
without prescaling, T = 25°C unless other conditions are given.
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37.4 Wake-up time from sleep modes
Table 37-6. Device wake-up time from sleep modes with various system clock sources.
Symbol Parameter
Condition
External 2MHz clock
Min.
Typ. (1)
2.0
Max.
Units
Wake-up time from idle,
standby, and extended standby
mode
32.768kHz internal oscillator
2MHz internal oscillator
32MHz internal oscillator
External 2MHz clock
120
2.0
0.2
twakeup
µs
4.5
32.768kHz internal oscillator
2MHz internal oscillator
32MHz internal oscillator
320
9.0
Wake-up time from Power-save
and Power-down mode
5.0
Note:
1. The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 37-2. All peripherals and modules start
execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts.
Figure 37-2. Wake-up time definition.
Wakeup time
Wakeup request
Clock output
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37.5 I/O Pin Characteristics
The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output
voltage limits reflect or exceed this specification.
Table 37-7. I/O pin characteristics.
Symbol Parameter
Condition
Min.
Typ.
Max.
Units
(1)
IOH
/
I/O pin source/sink current
-20
20
mA
(2)
IOL
VCC = 2.7 - 3.6V
2
0.7*VCC
0.7*VCC
-0.3
-0.3
-0.3
2.4
VCC+0.3
VCC+0.3
VCC+0.3
0.3*VCC
0.3*VCC
0.3*VCC
VIH
High level input voltage
VCC = 2.0 - 2.7V
VCC = 1.6 - 2.0V
VCC = 2.7- 3.6V
VCC = 2.0 - 2.7V
VCC = 1.6 - 2.0V
VCC = 3.0 - 3.6V
VIL
Low level input voltage
IOH = -2mA
IOH = -1mA
IOH = -2mA
IOH = -8mA
IOH = -6mA
IOH = -2mA
IOL = 2mA
IOL = 1mA
IOL = 2mA
IOL = 15mA
IOL = 10mA
IOL = 5mA
0.94*VCC
0.96*VCC
0.92*VCC
2.9
2.0
VCC = 2.3 - 2.7V
1.7
VOH
High level output voltage
V
VCC = 3.3V
2.6
VCC = 3.0V
2.1
2.6
VCC = 1.8V
1.4
1.6
VCC = 3.0 - 3.6V
0.05*VCC
0.03*VCC
0.06*VCC
0.4
0.4
0.4
VCC = 2.3 - 2.7V
0.7
VOL
Low level output voltage
VCC = 3.3V
VCC = 3.0V
VCC = 1.8V
T = 25°C
0.76
0.64
0.46
0.1
0.3
0.3
IIN
RP
Input leakage current
<0.001
25
µA
I/O pin Pull/Bus-keeper resistor
Reset pin pull-up resistor
k
RRST
25
4
tr
Rise time
No load
ns
slew rate limitation
7
Notes:
1. The sum of all IOH for PORTA and PORTB must not exceed 100mA.
The sum of all IOH for PORTC, PORTD, PORTE must for each port not exceed 200mA.
The sum of all IOH for pins PF[0-4] on PORTF must not exceed 200mA.
The sum of all IOL for pins PF[6-7] on PORTF, PORTR and PDI must not exceed 100mA.
2. The sum of all IOL for PORTA and PORTB must not exceed 100mA.
The sum of all IOL for PORTC, PORTD, PORTE must for each port not exceed 200mA.
The sum of all IOL for pins PF[0-4] on PORTF must not exceed 200mA.
The sum of all IOL for pins PF[6-7] on PORTF, PORTR and PDI must not exceed 100mA.
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37.6 ADC characteristics
Table 37-8. Power supply, reference and input range.
Symbol
AVCC
VREF
Rin
Parameter
Condition
Min.
VCC- 0.3
1
Typ.
Max.
Units
Analog supply voltage
Reference voltage
Input resistance
VCC+ 0.3
AVCC- 0.6
V
Switched
4.0
4.4
>10
7
k
pF
Cin
Input capacitance
Reference input resistance
Switched
RAREF
CAREF
VIN
(leakage only)
M
pF
Reference input capacitance Static load
Input range
-0.1
-VREF
-V
AVCC+0.1
VREF
Conversion range
Conversion range
Fixed offset voltage
Differential mode, Vinp - Vinn
V
VIN
Single ended unsigned mode, Vinp
VREF-V
ΔV
190
LSB
Table 37-9. Clock and timing.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
Maximum is 1/4 of Peripheral clock
frequency
100
2000
ClkADC
ADC Clock frequency
kHz
Measuring internal signals
Current limitation (CURRLIMIT) off
CURRLIMIT = LOW
100
100
100
100
100
0.25
125
2000
1500
1000
500
5
fclkADC
Sample rate
ksps
CURRLIMIT = MEDIUM
CURRLIMIT = HIGH
Sampling Time
1/2 ClkADC cycle
µs
(RES+2)/2+(GAIN !=0)
RES (Resolution) = 8 or 12
ClkADC
cycles
Conversion time (latency)
Start-up time
5
8
ADC clock cycles
12
7
24
7
ClkADC
cycles
After changing reference or input mode
After ADC flush
ADC settling time
1
1
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Table 37-10. Accuracy characteristics.
Symbol
Parameter
Condition (2)
Min.
Typ.
12
Max.
12
Units
RES
Resolution
Programmable to 8 or 12 bit
8
Bits
VCC-1.0V < VREF< VCC-0.6V
±1.2
±1.5
±1.0
±1.5
<±0.8
-1
±2
500ksps
All VREF
VCC-1.0V < VREF< VCC-0.6V
All VREF
±3
INL (1)
Integral non-linearity
±2
lsb
2000ksps
±3
DNL (1)
Differential non-linearity
Offset Error
guaranteed monotonic
<±1
mV
Temperature drift
<0.01
<0.6
-1
mV/K
mV/V
Operating voltage drift
External reference
AVCC/1.6
AVCC/2.0
Bandgap
10
Differential
mode
mV
8
Gain Error
±5
Temperature drift
<0.02
<0.5
mV/K
mV/V
Operating voltage drift
Differential mode, shorted input
2msps, VCC = 3.6V, ClkPER = 16MHz
mV
rms
Noise
0.4
Notes:
1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.
2. Unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external VREF is used.
Table 37-11. Gain stage characteristics.
Symbol
Rin
Parameter
Condition
Switched in normal mode
Switched in normal mode
Gain stage output
Min.
Typ.
4.0
Max.
Units
k
pF
Input resistance
Input capacitance
Signal range
Cin
4.4
0
VCC- 0.6
V
ClkADC
cycles
Propagation delay
Sample rate
ADC conversion rate
Same as ADC
500ksps
1
100
1000
±4
kHz
lsb
All gain
settings
INL (1)
Integral Non-Linearity
±1.5
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Symbol
Parameter
Condition
1x gain, normal mode
Min.
Typ.
-0.8
-2.5
-3.5
-2
Max.
Units
Gain Error
8x gain, normal mode
64x gain, normal mode
1x gain, normal mode
8x gain, normal mode
64x gain, normal mode
1x gain, normal mode
8x gain, normal mode
64x gain, normal mode
%
Offset Error,
input referred
-5
mV
-4
0.5
1.5
11
VCC = 3.6V
Ext. VREF
mV
rms
Noise
Note:
1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.
37.7 DAC Characteristics
Table 37-12. Power supply, reference and output range.
Symbol
AVCC
Parameter
Condition
Min.
VCC- 0.3
1.0
Typ.
Max.
VCC+ 0.3
VCC- 0.6
50
Units
Analog supply voltage
V
VREF
Reference voltage
Rchannel
DC output impedance
V
Linear output voltage range
Reference input resistance
Reference input capacitance Static load
Minimum Resistance load
0.15
AVCC-0.15
RAREF
CAREF
>10
7
M
pF
k
pF
nF
1
100
Maximum capacitance load
1000 serial resistance
1
AVCC/1000
10
Operating within accuracy specification
Safe operation
Output sink/source
mA
Table 37-13. Clock and timing.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
Fclk
Conversion rate
Fout=Fclk/4, Cload=100pF, maximum step size
0
1000
ksps
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Table 37-14. Accuracy characteristics.
Symbol
Parameter
Condition
Min.
Typ.
Max.
12
3
Units
RES
Input Resolution
Bits
VCC = 1.6V
VCC = 3.6V
VCC = 1.6V
VCC = 3.6V
VCC = 1.6V
VCC = 3.6V
VCC = 1.6V
VCC = 3.6V
VCC = 1.6V
VCC = 3.6V
VCC = 1.6V
VCC = 3.6V
2.0
1.5
2.0
1.5
5.0
5.0
1.5
0.6
1.0
0.6
4.5
4.5
<4
VREF= Ext 1.0V
VREF=AVCC
2.5
4
INL (1)
Integral non-linearity
4
VREF=INT1V
VREF=Ext 1.0V
VREF=AVCC
3
lsb
1.5
3.5
1.5
DNL (1)
Differential non-linearity
VREF=INT1V
Gain error
After calibration
Gain calibration step size
Gain calibration drift
Offset error
4
VREF= Ext 1.0V
After calibration
<0.2
<1
mV/K
lsb
Offset calibration step size
1
Note:
1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% output voltage range.
37.8 Analog Comparator Characteristics
Table 37-15. Analog Comparator characteristics.
Symbol
Voff
Parameter
Condition
Min.
Typ.
< 10
<1
Max.
Units
mV
nA
Input offset voltage
Input leakage current
Input voltage range
AC startup time
Ilk
-0.1
AVCC
V
100
0
µs
Vhys1
Hysteresis, None
mode = High Speed (HS)
mode = Low Power (LP)
mode = HS
13
30
30
60
Vhys2
Hysteresis, Small
Hysteresis, Large
mV
Vhys3
mode = LP
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Symbol
Parameter
Condition
VCC = 3.0V, T= 85°C
mode = HS
VCC = 3.0V, T= 85°C
mode = LP
Min.
Typ.
30
Max.
Units
mode = HS
mode = LP
90
30
tdelay
Propagation delay
ns
130
130
500
Single mode
Double mode
2
4
8
Current source calibration
range
µs
16
0.5
64-Level Voltage Scaler
Integral non-linearity (INL)
0.3
lsb
37.9 Bandgap and Internal 1.0V Reference Characteristics
Table 37-16. Bandgap and Internal 1.0V reference characteristics.
Symbol Parameter
Condition
Min.
Typ.
Max.
Units
As reference for ADC or DAC
As input voltage to ADC and AC
1 ClkPER + 2.5µs
Startup time
µs
1.5
1.1
1
Bandgap voltage
V
INT1V
Internal 1.00V reference
T= 85°C, after calibration
0.99
1.01
Variation over voltage and temperature
Relative to T= 85°C, VCC = 3.0V
1.0
%
37.10 Brownout Detection Characteristics
Table 37-17. Brownout detection characteristics.
Symbol Parameter
BOD level 0 falling VCC
BOD level 1 falling VCC
BOD level 2 falling VCC
Condition
Min.
Typ.
1.62
1.8
Max.
Units
1.60
1.72
2.0
BOD level 3 falling VCC
VBOT
2.2
V
BOD level 4 falling VCC
2.4
BOD level 5 falling VCC
BOD level 6 falling VCC
BOD level 7 falling VCC
2.6
2.8
3.0
Continuous mode
Sampled mode
0.4
tBOD
Detection time
Hysteresis
µs
1000
1.6
VHYST
%
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37.11 External Reset Characteristics
Table 37-18. External reset characteristics.
Symbol Parameter
Condition
Min.
Typ.
Max.
Units
tEXT
Minimum reset pulse width
95
1000
ns
VCC = 2.7 - 3.6V
0.60*VCC
0.70*VCC
0.40*VCC
0.30*VCC
Reset threshold voltage (VIH)
VCC = 1.6 - 2.7V
VCC = 2.7 - 3.6V
VCC = 1.6 - 2.7V
VRST
V
Reset threshold voltage (VIL)
37.12 Power-on Reset Characteristics
Table 37-19. Power-on reset characteristics.
Symbol Parameter
Condition
Min.
Typ.
1.0
Max.
Units
VCC falls faster than 1V/ms
VCC falls at 1V/ms or slower
0.4
0.8
(1)
VPOT-
POR threshold voltage falling VCC
POR threshold voltage rising VCC
1.0
V
VPOT+
1.3
1.59
Note:
1. VPOT- values are only valid when BOD is disabled. When BOD is enabled VPOT- = VPOT+.
37.13 VBAT and Battery Backup Characteristics
Table 37-20. VBAT and battery backup characteristics.
Symbol Parameter
Vbat supply voltage range
Condition
Min
Typ
Max
Units
V
Vbbbod
3.6
0.1
Vcc Power-down slope range
BOD threshold voltage
Monotonic falling
V/ms
1.8
V
s
Vbbbod
BBBOD threshold voltage
BBBOD detection speed
1.7
1
2.1
2
Powering from VBAT pin RTC from Low
Power 32kHz TOSC and XOSC Faillure
Monitor enabled
Current consumption
VBAT pin leackage
0.6
µA
nA
Powering Battery Backup module from Vcc
50
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37.14 Flash and EEPROM Memory Characteristics
Table 37-21. Endurance and data retention.
Symbol Parameter
Condition
Min.
10K
10K
100
25
Typ.
Max.
Units
25°C
85°C
25°C
55°C
25°C
85°C
25°C
55°C
Write/Erase cycles
Cycle
Flash
Data retention
Year
Cycle
Year
80K
30K
100
25
Write/Erase cycles
Data retention
EEPROM
Table 37-22. Programming time.
Symbol Parameter
Condition
Min.
Typ. (1)
Max.
Units
Chip Erase
256KB Flash, EEPROM (2) and SRAM Erase
Page Erase
105
4
Flash
Page Write
4
Atomic Page Erase and Write
Page Erase
8
ms
4
EEPROM
Page Write
4
Atomic Page Erase and Write
8
Notes:
1. Programming is timed from the 2MHz internal oscillator.
2. EEPROM is not erased if the EESAVE fuse is programmed.
37.15 Clock and Oscillator Characteristics
37.15.1 Calibrated 32.768kHz Internal Oscillator characteristics
Table 37-23. 32.768kHz internal oscillator characteristics.
Symbol Parameter
Condition
Min.
Typ.
Max.
Units
Frequency
32.768
kHz
Factory calibration accuracy
User calibration accuracy
T = 85C, VCC = 3.0V
-0.5
-0.5
0.5
0.5
%
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37.15.2 Calibrated 2MHz RC Internal Oscillator characteristics
Table 37-24. 2MHz internal oscillator characteristics.
Symbol Parameter
Frequency range
Condition
Min.
Typ.
Max.
Units
DFLL can tune to this frequency over
voltage and temperature
1.8
2.2
MHz
Factory calibrated frequency
Factory calibration accuracy
User calibration accuracy
DFLL calibration stepsize
2.0
T = 85C, VCC= 3.0V
-1.5
-0.2
1.5
0.2
%
0.22
37.15.3 Calibrated and tunable 32MHz internal oscillator characteristics
Table 37-25. 32MHz internal oscillator characteristics.
Symbol Parameter
Frequency range
Condition
Min.
Typ.
Max.
Units
DFLL can tune to this frequency over
voltage and temperature
30
55
MHz
Factory calibrated frequency
Factory calibration accuracy
User calibration accuracy
DFLL calibration step size
32
T = 85C, VCC= 3.0V
-1.5
-0.2
1.5
0.2
%
0.23
37.15.4 32kHz Internal ULP Oscillator characteristics
Table 37-26. 32kHz internal ULP oscillator characteristics.
Symbol Parameter
Output frequency
Accuracy
Condition
Min.
Typ.
Max.
Units
kHz
%
32
-30
30
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37.15.5 Internal Phase Locked Loop (PLL) characteristics
Table 37-27. Internal PLL characteristics.
Symbol Parameter
Condition
Min.
0.4
20
Typ.
Max.
64
Units
fIN
Input frequency
Output frequency must be within fOUT
VCC= 1.6 - 1.8V
48
MHz
fOUT
Output frequency (1)
VCC= 2.7 - 3.6V
20
128
Start-up time
Re-lock time
25
25
µs
Note:
1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency.
37.15.6 External clock characteristics
Figure 37-3. External clock drive waveform.
tCH
tCH
tCR
tCF
VIH1
VIL1
tCL
tCK
Table 37-28. External clock used as system clock without prescaling.
Symbol Parameter
Clock frequency(1)
Condition
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
Min.
0
Typ.
Max.
12
Units
1/tCK
MHz
0
32
83.3
31.5
30.0
12.5
30.0
12.5
tCK
Clock period
tCH
Clock high time
tCL
Clock low time
ns
10
3
tCR
Rise time (for maximum frequency)
10
3
tCF
Fall time (for maximum frequency)
tCK
Change in period from one clock cycle to the next
10
%
Note:
1. The maximum frequency vs. supply voltage is linear between 1.8V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
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Table 37-29. External clock with prescaler (1)for system clock.
Symbol Parameter
Condition
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
Min.
0
Typ.
Max.
90
Units
1/tCK
Clock Frequency (2)
Clock Period
MHz
0
142
11
tCK
ns
ns
ns
ns
7
4.5
2.4
4.5
2.4
tCH
Clock High Time
tCL
Clock Low Time
1.5
1.0
1.5
1.0
10
tCR
Rise Time (for maximum frequency)
tCF
Fall Time (for maximum frequency)
ns
%
tCK
Change in period from one clock cycle to the next
Notes:
1. System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded.
2. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
37.15.7 External 16MHz crystal oscillator and XOSC characteristics
Table 37-30. External 16MHz crystal oscillator and XOSC characteristics.
Symbol Parameter
Condition
Min.
Typ.
<10
<1
Max.
Units
FRQRANGE=0
XOSCPWR=0
XOSCPWR=1
XOSCPWR=0
XOSCPWR=1
Cycle to cycle jitter
FRQRANGE=1, 2, or 3
<1
ns
FRQRANGE=0
<6
Long term jitter
Frequency error
FRQRANGE=1, 2, or 3
<0.5
<0.5
<0.1
<0.05
<0.005
<0.005
40
FRQRANGE=0
FRQRANGE=1
FRQRANGE=2 or 3
XOSCPWR=0
XOSCPWR=1
XOSCPWR=0
XOSCPWR=1
%
FRQRANGE=0
FRQRANGE=1
FRQRANGE=2 or 3
42
Duty cycle
45
48
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Symbol Parameter
Condition
Min.
Typ.
Max.
Units
0.4MHz resonator,
CL=100pF
2.4k
XOSCPWR=0,
FRQRANGE=0
1MHz crystal, CL=20pF
2MHz crystal, CL=20pF
2MHz crystal
8.7k
2.1k
4.2k
250
195
360
285
155
365
200
105
435
235
125
495
270
145
305
XOSCPWR=0,
FRQRANGE=1,
CL=20pF
8MHz crystal
9MHz crystal
8MHz crystal
XOSCPWR=0,
FRQRANGE=2,
CL=20pF
9MHz crystal
12MHz crystal
9MHz crystal
XOSCPWR=0,
FRQRANGE=3,
CL=20pF
12MHz crystal
16MHz crystal
9MHz crystal
RQ
Negative impedance (1)
XOSCPWR=1,
FRQRANGE=0,
CL=20pF
12MHz crystal
16MHz crystal
9MHz crystal
XOSCPWR=1,
FRQRANGE=1,
CL=20pF
12MHz crystal
16MHz crystal
12MHz crystal
XOSCPWR=1,
FRQRANGE=2,
CL=20pF
16MHz crystal
12MHz crystal
16MHz crystal
160
380
205
XOSCPWR=1,
FRQRANGE=3,
CL=20pF
ESR
SF = safety factor
min(RQ)/SF
k
Parasitic capacitance
XTAL1 pin
CXTAL1
5.2
Parasitic capacitance
XTAL2 pin
pF
CXTAL2
CLOAD
6.8
Parasitic capacitance load
2.95
Note:
1. Numbers for negative impedance are not tested in production but guaranteed from design and characterization.
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37.15.8 External 32.768kHz crystal oscillator and TOSC characteristics
Table 37-31. External 32.768kHz crystal oscillator and TOSC characteristics.
Symbol Parameter
Condition
Min.
Typ.
Max.
60
Units
Crystal load capacitance 6.5pF
Crystal load capacitance 9.0pF
Recommended crystal equivalent
ESR/R1
k
series resistance (ESR)
35
CTOSC1
CTOSC2
CL
Parasitic capacitance TOSC1 pin
Parasitic capacitance TOSC2 pin
Parasitic capacitance load
3.0
2.9
2.0
pF
capacitance load matched to
crystal specification
Recommended safety factor
3.0
Note:
1. See Figure 37-4 for definition.
Figure 37-4. TOSC input capacitance.
CL1
CL2
Device internal
External
TOSC1
TOSC2
32.768kHz crystal
The parasitic capacitance between the TOSC pins is CL1 + CL2 in series as seen from the crystal when oscillating without
external capacitors.
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37.16 SPI Characteristics
Figure 37-5. SPI timing requirements in master mode.
SS
tMOS
tSCKR
tSCKF
SCK
(CPOL = 0)
tSCKW
SCK
(CPOL = 1)
tSCKW
tMIS
tMIH
tSCK
MISO
(Data input)
MSB
LSB
tMOH
tMOH
MOSI
(Data output)
MSB
LSB
Figure 37-6. SPI timing requirements in slave mode.
SS
tSSS
tSCKR
tSCKF
tSSH
SCK
(CPOL = 0)
tSSCKW
SCK
(CPOL = 1)
tSSCKW
tSIS
tSIH
tSSCK
MOSI
(Data input)
MSB
LSB
tSOSSS
tSOS
tSOSSH
MISO
(Data output)
MSB
LSB
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Table 37-32. SPI timing characteristics and requirements.
Symbol Parameter Condition
Min.
Typ.
Max.
Units
(See Table 22-3 in
XMEGA AU Manual)
tSCK
SCK Period
Master
tSCKW
tSCKR
tSCKF
tMIS
SCK high/low width
SCK Rise time
Master
Master
Master
Master
Master
Master
Master
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
0.5*SCK
2.7
SCK Fall time
2.7
MISO setup to SCK
MISO hold after SCK
MOSI setup SCK
MOSI hold after SCK
Slave SCK Period
SCK high/low width
SCK Rise time
10
tMIH
10
tMOS
tMOH
tSSCK
tSSCKW
tSSCKR
tSSCKF
tSIS
0.5*SCK
1.0
4*t ClkPER
2*t ClkPER
ns
1600
1600
SCK Fall time
MOSI setup to SCK
MOSI hold after SCK
SS setup to SCK
3
t ClkPER
21
tSIH
tSSS
tSSH
SS hold after SCK
MISO setup SCK
MISO hold after SCK
MISO setup after SS low
MISO hold after SS high
20
tSOS
8.0
13
tSOH
tSOSS
tSOSH
11
8.0
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37.17 Two-Wire Interface Characteristics
Table 37-33 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel AVR XMEGA
Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 37-
7.
Figure 37-7. Two-Wire Interface bus timing.
tof
tHIGH
tLOW
tr
SCL
SDA
tHD;DAT
tSU;STA
tSU;STO
tSU;DAT
tHD;STA
tBUF
Table 37-33. Two-wire interface characteristics.
Symbol Parameter
Condition
Min.
0.7VCC
0.5
Typ.
Max.
Units
VIH
VIL
Input high voltage
VCC+0.5
0.3×VCC
Input low voltage
V
(1)
Vhys
Hysteresis of Schmitt Trigger inputs
Output low voltage
0.05VCC
0
VOL
3mA, sink current
0.4
300
250
50
(1)(2)
(1)(2)
tr
tof
Rise time for both SDA and SCL
Output fall time from VIHmin to VILmax
Spikes suppressed by input filter
Input current for each I/O pin
Capacitance for each I/O pin
SCL clock frequency
20+0.1Cb
20+0.1Cb
0
10pF < Cb < 400pF (2)
0.1VCC < VI < 0.9VCC
ns
tSP
II
-10
10
µA
pF
CI
10
fSCL
fPER (3)>max(10fSCL, 250kHz)
0
400
kHz
fSCL 100kHz
100ns
Cb
--------------
VCC – 0.4V
---------------------------
3mA
RP
Value of pull-up resistor
300ns
fSCL > 100kHz
--------------
Cb
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Symbol Parameter
Condition
fSCL 100kHz
Min.
4.0
0.6
4.7
1.3
4.0
0.6
4.7
0.6
0
Typ.
Max.
Units
tHD;STA
Hold Time (repeated) START condition
fSCL > 100kHz
fSCL 100kHz
fSCL > 100kHz
fSCL 100kHz
fSCL > 100kHz
fSCL 100kHz
fSCL > 100kHz
fSCL 100kHz
fSCL > 100kHz
fSCL 100kHz
fSCL > 100kHz
fSCL 100kHz
fSCL > 100kHz
fSCL 100kHz
fSCL > 100kHz
tLOW
Low Period of SCL Clock
High Period of SCL Clock
tHIGH
Set-up time for a repeated START
condition
tSU;STA
tHD;DAT
tSU;DAT
tSU;STO
tBUF
µs
3.45
0.9
Data hold time
0
250
100
4.0
0.6
4.7
1.3
Data setup time
Setup time for STOP condition
Bus free time between a STOP and
START condition
Notes:
1. Required only for fSCL > 100kHz.
2. Cb = Capacitance of one bus line in pF.
3.
fPER = Peripheral clock frequency.
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38. Typical Characteristics
38.1 Current consumption
38.1.1 Active mode supply current
Figure 38-1. Active supply current vs. frequency.
fSYS = 0 - 1MHz external clock, T = 25°C.
800
700
600
500
400
300
200
100
3.3V
3.0V
2.7V
2.2V
1.8V
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Frequency [MHz]
Figure 38-2. Active supply current vs. frequency.
fSYS = 1 - 32MHz external clock, T = 25°C.
14
12
10
8
3.3V
3.0V
2.7V
6
2.2V
4
1.8V
2
0
0
4
8
12
16
20
24
28
32
Frequency [MHz]
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Figure 38-3. Active mode supply current vs. VCC
.
fSYS = 32.768kHz internal oscillator.
450
400
350
300
250
200
150
100
-40°C
25°C
85°C
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
V
CC [V]
Figure 38-4. Active mode supply current vs. VCC
.
fSYS = 1MHz external clock.
1000
900
800
700
600
500
400
300
200
-40°C
25°C
85°C
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
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Figure 38-5. Active mode supply current vs. VCC
.
fSYS = 2MHz internal oscillator.
1800
1600
1400
1200
1000
800
-40°C
25°C
85°C
600
400
200
1.6
1.8
2.0
2.2
2.4
2.6
VCC [V]
2.8
3.0
3.2
3.4
3.6
Figure 38-6. Active mode supply current vs. VCC
.
fSYS = 32MHz internal oscillator prescaled to 8MHz.
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
-40°C
25°C
85°C
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
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Figure 38-7. Active mode supply current vs. VCC
.
fSYS = 32MHz internal oscillator.
16
15
14
13
12
11
10
9
-40°C
25°C
85°C
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
VCC [V]
38.1.2 Idle mode supply current
Figure 38-8. Idle mode supply current vs. frequency.
fSYS = 0 - 1MHz external clock, T = 25°C.
180
160
140
120
100
80
3.3V
3.0V
2.7V
2.2V
1.8V
60
40
20
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Frequency [MHz]
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Figure 38-9. Idle mode supply current vs. frequency.
fSYS = 1 - 32MHz external clock, T = 25°C.
6
5
4
3
2
3.3V
3.0V
2.7V
2.2V
1
0
1.8V
0
4
8
12
16
Frequency [MHz]
20
24
28
32
Figure 38-10.Idle mode supply current vs. VCC
.
fSYS = 32.768kHz internal oscillator.
35
34
33
32
31
30
29
28
85°C
-40°C
25°C
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
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Figure 38-11.Idle mode supply current vs. VCC
.
fSYS = 1MHz external clock.
200
180
160
140
120
100
80
85°C
25°C
-40°C
60
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
Figure 38-12.Idle mode supply current vs. VCC
.
fSYS = 2MHz internal oscillator.
500
450
400
350
300
250
200
-40°C
25°C
85°C
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
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Figure 38-13.Idle mode supply current vs. VCC
.
fSYS = 32MHz internal oscillator prescaled to 8MHz.
2.3
-40°C
25°C
85°C
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
Figure 38-14.Idle mode current vs. VCC
.
fSYS = 32MHz internal oscillator.
6.7
6.4
6.1
5.8
5.5
5.2
4.9
4.6
4.3
4.0
-40°C
25°C
85°C
2.7
2.8
2.9
3.0
3.1
3.2
[V]
3.3
3.4
3.5
3.6
V
CC
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38.1.3 Power-down mode supply current
Figure 38-15.Power-down mode supply current vs. VCC
.
All functions disabled.
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
85°C
25°C
-40°C
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
Figure 38-16.Power-down mode supply current vs. VCC
.
Watchdog and sampled BOD enabled.
3.5
3.2
2.9
2.6
2.3
2.0
1.7
1.4
1.1
85°C
25°C
-40°C
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
V
CC [V]
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38.1.4 Power-save mode supply current
Figure 38-17.Power-save mode supply current vs. VCC
.
Real Time Counter enabled and running from 1.024kHz output of 32.768kHz TOSC.
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
Normal mode
Low-power mode
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
38.1.5 Standby mode supply current
Figure 38-18.Standby supply current vs. VCC
.
Standby, fSYS = 1MHz.
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
85°C
25°C
-40°C
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
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Figure 38-19.Standby supply current vs. VCC
.
25°C, running from different crystal oscillators.
500
16MHz
12MHz
450
400
350
300
250
200
150
8MHz
2MHz
0.454MHz
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
38.2 I/O Pin Characteristics
38.2.1 Pull-up
Figure 38-20.I/O pin pull-up resistor current vs. input voltage.
VCC = 1.8V.
80
70
60
50
40
30
20
10
0
-40°C
25°C
85°C
0
0.2
0.4
0.6
0.8
1.0
VPIN[V]
1.2
1.4
1.6
1.8
XMEGA A3BU [DATASHEET]
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Figure 38-21.I/O pin pull-up resistor current vs. input voltage.
VCC = 3.0V.
130
117
104
91
78
65
52
39
26
13
0
-40°C
25°C
85°C
0
0.3
0.6
0.9
1.2
1.5
1.8
PIN[V]
2.1
2.4
2.7
3.0
V
Figure 38-22.I/O pin pull-up resistor current vs. input voltage.
VCC = 3.3V.
140
126
112
98
84
70
56
42
28
14
0
-40°C
25°C
85°C
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
3.3
VPIN[V]
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38.2.2 Output Voltage vs. Sink/Source Current
Figure 38-23.I/O pin output voltage vs. source current.
VCC = 1.8V.
1.9
1.7
1.5
1.3
1.1
0.9
-40°C
25°C 85°C
-7
0.7
0.5
-9
-8
-6
-5
-4
-3
-2
-1
0
IPIN [mA]
Figure 38-24.I/O pin output voltage vs. source current.
VCC = 3.0V.
3.0
2.5
2.0
1.5
1.0
-40°C
25°C 85°C
-25
0.5
-30
-20
-15
-10
-5
0
IPIN [mA]
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Figure 38-25.I/O pin output voltage vs. source current.
VCC = 3.3V.
3.5
3.0
2.5
2.0
-40°C
1.5
25°C
1.0
85°C
0.5
-30
-25
-20
-15
-10
-5
0
I
PIN [mA]
Figure 38-26.I/O pin output voltage vs. source current.
4.0
3.6V
3.3V
3.5
3.0
2.5
2.0
1.5
1.0
2.7V
2.2V
1.8V
-20
-18
-16
-14
-12
-10
-8
-6
-4
-2
0
IPIN [mA]
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Figure 38-27.I/O pin output voltage vs. sink current.
VCC = 1.8V.
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
85°C 25°C
-40°C
0
2
4
6
8
10
12
14
16
18
20
I
PIN [mA]
Figure 38-28.I/O pin output voltage vs. sink current.
VCC = 3.0V.
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
25°C
85°C
-40°C
0
3
6
9
12
15
18
21
24
27
30
IPIN [mA]
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Figure 38-29.I/O pin output voltage vs. sink current.
VCC = 3.3V.
1.0
0.8
0.6
0.4
0.2
0
85°C
25°C
-40°C
0
5
10
15
20
25
30
35
IPIN [mA]
Figure 38-30.I/O pin output voltage vs. sink current.
1.5
1.8V
1.2
0.9
0.6
0.3
0
2.2V
2.7V
3.3V
3.6V
0
5
10
15
20
25
IPIN [mA]
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38.2.3 Thresholds and Hysteresis
Figure 38-31.I/O pin input threshold voltage vs. VCC.
T = 25°C.
1.85
1.70
1.55
1.40
1.25
1.10
0.95
0.80
0.65
0.50
VIH
VIL
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
Figure 38-32.I/O pin input threshold voltage vs. VCC
.
VIH I/O pin read as “1”.
1.8
1.6
1.4
1.2
1.0
0.8
-40°C
25°C
85°C
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
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Figure 38-33.I/O pin input threshold voltage vs. VCC
.
VIL I/O pin read as “0”.
1.7
1.5
1.3
1.1
0.9
0.7
0.5
-40°C
25°C
85°C
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
Figure 38-34.I/O pin input hysteresis vs. VCC
.
350
300
250
200
150
100
-40°C
25°C
85°C
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
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38.3 ADC Characteristics
Figure 38-35.INL error vs. external VREF
.
T = 25C, VCC = 3.6V, external reference.
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
Differential mode
Single-ended unsigned mode
Single-ended signed mode
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
V
REF [V]
Figure 38-36.INL error vs. sample rate.
T = 25C, VCC = 3.6V, VREF = 3.0V external.
1.4
Differential mode
1.3
1.2
1.1
1.0
0.9
0.8
0.7
Single-ended unsigned mode
Single-ended signed mode
500
650
800
950
1100
1250
1400
1550
1700
1850
2000
ADC sample rate [ksps]
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Figure 38-37.INL error vs. input code.
2.0
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
0
512
1024
1536
2048
2560
3072
3584
4096
ADC input code
Figure 38-38.DNL error vs. external VREF
.
T = 25C, VCC = 3.6V, external reference.
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
Differential mode
Single-endedsigned mode
Single-ended unsigned mode
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
VREF [V]
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Figure 38-39.DNL error vs. sample rate.
T = 25C, VCC = 3.6V, VREF = 3.0V external.
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
Differential mode
Single-ended signed mode
Single-ended unsigned mode
0.50
0.65
0.80
0.95
1.10
1.25
1.40
1.55
1.70
1.85
2.00
Sampling speed [MS/s]
Figure 38-40.DNL error vs. input code.
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
0
512
1024
1536
2048
2560
3072
3584
4096
ADC Input Code
XMEGA A3BU [DATASHEET]
110
8362F–AVR–02/2013
Figure 38-41.Gain error vs. VREF
.
T = 25C, VCC = 3.6V, ADC sampling speed = 500ksps.
4
2
0
Single-ended signed mode
Single-ended unsigned mode
-2
-4
Differential mode
-6
-8
-10
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
VREF [V]
Figure 38-42.Gain error vs. VCC
.
T = 25C, VREF = external 1.0V, ADC sampling speed = 500ksps.
3.0
2.5
2.0
1.5
1.0
0.5
0
Single-ended signed mode
Single-ended unsigned mode
-0.5
-1.0
-1.5
-2.0
Differential mode
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA A3BU [DATASHEET]
111
8362F–AVR–02/2013
Figure 38-43.Offset error vs. VREF
.
T = 25C, VCC = 3.6V, ADC sampling speed = 500ksps.
-1.1
-1.2
-1.3
-1.4
-1.5
-1.6
Differential mode
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
VREF [V]
Figure 38-44.Gain error vs. temperature.
VCC = 3.0V, VREF = external 2.0V.
1
0
1V mode
-1
-2
1.5V mode
2V mode
-3
-4
-5
-6
2.5V mode
3V mode
-7
-8
-9
-10
-11
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
Temperature [°C]
XMEGA A3BU [DATASHEET]
112
8362F–AVR–02/2013
Figure 38-45.Offset error vs. VCC
.
T = 25C, VREF = external 1.0V, ADC sampling speed = 500ksps.
-0.5
-0.6
-0.7
-0.8
-0.9
-1.0
-1.1
-1.2
Differential mode
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
Figure 38-46.Noise vs. VREF
.
T = 25C, VCC = 3.6V, ADC sampling speed = 500ksps.
1.30
1.15
1.00
0.85
0.70
0.55
0.40
Single-ended signed mode
Single-ended unsigned mode
Differential mode
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
VREF [V]
XMEGA A3BU [DATASHEET]
113
8362F–AVR–02/2013
Figure 38-47.Noise vs. VCC
.
T = 25C, VREF = external 1.0V, ADC sampling speed = 500ksps.
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
Single-ended signed mode
Single-ended unsigned mode
Differential mode
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
38.4 DAC Characteristics
Figure 38-48.DAC INL error vs. VREF
.
VCC = 3.6V.
3.1
2.9
2.7
2.5
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
-40°C
25°C
85°C
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
V
REF [V]
XMEGA A3BU [DATASHEET]
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8362F–AVR–02/2013
Figure 38-49.DNL error vs. VREF
.
T = 25C, VCC = 3.6V.
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
-40°C
25°C
85°C
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
V
REF [V]
Figure 38-50.DAC noise vs. temperature.
VCC = 3.0V, VREF = 2.4V .
0.183
0.181
0.179
0.177
0.175
0.173
0.171
0.169
0.167
0.165
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
Temperature [ºC]
XMEGA A3BU [DATASHEET]
115
8362F–AVR–02/2013
38.5 Analog Comparator Characteristics
Figure 38-51.Analog comparator hysteresis vs. VCC
.
High-speed, small hysteresis.
17
16
15
14
13
12
11
10
9
85°C
-40°C
25°C
8
7
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
Figure 38-52.Analog comparator hysteresis vs. VCC
.
Low power, small hysteresis.
35
34
33
32
31
30
29
28
27
26
25
85°C
25°C
-40°C
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA A3BU [DATASHEET]
116
8362F–AVR–02/2013
Figure 38-53.Analog comparator hysteresis vs. VCC
.
High-speed mode, large hysteresis.
40
38
36
34
32
30
28
26
24
22
20
85°C
25°C
-40°C
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
Figure 38-54.Analog comparator hysteresis vs. VCC
.
Low power, large hysteresis.
75
70
65
60
55
50
85°C
25°C
-40°C
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA A3BU [DATASHEET]
117
8362F–AVR–02/2013
Figure 38-55.Analog comparator current source vs. calibration value.
Temperature = 25°C.
8
7
6
5
4
3
2
3.3V
3.0V
2.7V
2.2V
1.8V
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
CALIB[3..0]
Figure 38-56.Analog comparator current source vs. calibration value.
VCC = 3.0V.
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
-40°C
25°C
85°C
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
CALIB[3..0]
XMEGA A3BU [DATASHEET]
118
8362F–AVR–02/2013
Figure 38-57.Voltage scaler INL vs. SCALEFAC.
T = 25C, VCC = 3.0V.
0.100
0.075
0.050
0.025
0
25°C
-0.025
-0.050
-0.075
-0.100
0
10
20
30
40
50
60
70
SCALEFAC
38.6 Internal 1.0V reference Characteristics
Figure 38-58.ADC/DAC Internal 1.0V reference vs. temperature.
1.002
1.000
0.998
0.996
0.994
0.992
0.990
3.3V
3.0V
2.7V
1.8V
-45 -35 -25 -15
-5
5
15
25
35
45
55
65
75
85
Temperature [°C]
XMEGA A3BU [DATASHEET]
119
8362F–AVR–02/2013
38.7 BOD Characteristics
Figure 38-59.BOD thresholds vs. temperature.
BOD level = 1.6V.
1.632
1.630
1.628
1.626
1.624
1.622
1.620
Rising VCC
Falling VCC
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
Temperature [°C]
Figure 38-60.BOD thresholds vs. temperature.
BOD level = 3.0V.
3.08
3.07
3.06
3.05
3.04
3.03
3.02
3.01
Rising VCC
Falling VCC
-45 -35 -25 -15
-5
5
15
25
35
45
55
65
75
85
Temperature [°C]
XMEGA A3BU [DATASHEET]
120
8362F–AVR–02/2013
38.8 External Reset Characteristics
Figure 38-61. Minimum Reset pin pulse width vs. VCC
.
147
142
137
132
127
122
117
112
107
102
97
85°C
-40°C
25°C
92
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
Figure 38-62. Reset pin pull-up resistor current vs. reset pin voltage.
VCC = 1.8V.
80
70
60
50
40
30
20
10
0
-40°C
25°C
85°C
0
0.2
0.4
0.6
0.8
1.0
VPIN[V]
1.2
1.4
1.6
1.8
XMEGA A3BU [DATASHEET]
121
8362F–AVR–02/2013
Figure 38-63. Reset pin pull-up resistor current vs. reset pin voltage.
VCC = 3.0V.
130
117
104
91
78
65
52
39
26
13
0
-40°C
25°C
85°C
0
0.3
0.6
0.9
1.2
1.5
1.8
PIN[V]
2.1
2.4
2.7
3.0
V
Figure 38-64. Reset pin pull-up resistor current vs. reset pin voltage.
VCC = 3.3V.
140
126
112
98
84
70
56
42
28
14
0
-40°C
25°C
85°C
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
3.3
VPIN[V]
XMEGA A3BU [DATASHEET]
122
8362F–AVR–02/2013
Figure 38-65. Reset pin input threshold voltage vs. VCC.
VIH - Reset pin read as “1”.
2.1
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
-40°C
85°C
25°C
1.6
1.8
2.0
2.2
2.4
2.6
CC [V]
2.8
3.0
3.2
3.4
3.6
V
Figure 38-66. Reset pin input threshold voltage vs. VCC.
VIL - Reset pin read as “0”.
1.65
1.50
1.35
1.20
1.05
0.90
0.75
0.60
0.45
-40°C
25°C
85°C
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA A3BU [DATASHEET]
123
8362F–AVR–02/2013
38.9 Power-on Reset Characteristics
Figure 38-67. Power-on reset current consumption vs. VCC
.
BOD level = 3.0V, enabled in continuous mode.
700
600
500
400
300
200
100
0
-40°C
25°C
85°C
0
0.5
1.0
1.5
2.0
2.5
3.0
VCC [V]
38.10 Oscillator Characteristics
38.10.1 Ultra Low-Power internal oscillator
Figure 38-68. Ultra Low-Power internal oscillator frequency vs. temperature.
32.9
32.8
32.7
32.6
32.5
32.4
32.3
32.2
3.3V
3.0V
2.7V
2.2V
1.8V
-45 -35 -25 -15
-5
5
15
25
35
45
55
65
75
85
Temperature [°C]
XMEGA A3BU [DATASHEET]
124
8362F–AVR–02/2013
38.10.2 32.768kHz Internal Oscillator
Figure 38-69. 32.768kHz internal oscillator frequency vs. temperature.
32.85
32.80
32.75
32.70
32.65
32.60
32.55
32.50
32.45
32.40
32.35
3.3V
3.0V
2.7V
2.2V
1.8V
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
Temperature [°C]
Figure 38-70. 32.768kHz internal oscillator frequency vs. calibration value.
VCC = 3.0V, T = 25°C.
50
45
40
35
30
25
20
0
50
100
150
200
250
300
RC32KCAL[7..0]
XMEGA A3BU [DATASHEET]
125
8362F–AVR–02/2013
38.10.3 2MHz Internal Oscillator
Figure 38-71. 2MHz internal oscillator frequency vs. temperature.
DFLL disabled.
2.18
2.16
2.14
2.12
2.10
2.08
2.06
2.04
2.02
2.00
1.98
3.3V
3.0V
2.7V
2.2V
1.8V
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
Temperature [°C]
Figure 38-72. 2MHz internal oscillator frequency vs. temperature.
DFLL enabled, from the 32.768kHz internal oscillator .
2.008
2.005
2.002
1.999
1.996
1.993
1.990
1.987
1.984
1.981
1.978
1.975
3.0V
3.3V
2.7V
2.2V
1.8V
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
Temperature [°C]
XMEGA A3BU [DATASHEET]
126
8362F–AVR–02/2013
Figure 38-73. 2MHz internal oscillator CALA calibration step size.
VCC = 3V.
0.37
0.35
0.32
0.30
0.27
0.25
0.22
0.20
0.17
25°C
-40°C
85°C
0
10
20
30
40
50
60
70
80
90 100 110 120 130
CALA
38.10.4 32MHz Internal Oscillator
Figure 38-74. 32MHz internal oscillator frequency vs. temperature.
DFLL disabled.
36.5
36.0
35.5
35.0
34.5
34.0
33.5
33.0
32.5
32.0
31.5
3.3V
3.0V
2.7V
1.8V
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
Temperature [°C]
XMEGA A3BU [DATASHEET]
127
8362F–AVR–02/2013
Figure 38-75. 32MHz internal oscillator frequency vs. temperature.
DFLL enabled, from the 32.768kHz internal oscillator.
32.10
32.05
32.00
31.95
31.90
31.85
31.80
31.75
31.70
31.65
31.60
3.0V
3.3V
2.7V
2.2V
1.8V
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
Temperature [°C]
Figure 38-76. 32MHz internal oscillator CALA calibration step size.
VCC = 3.0V.
0.39
0.34
0.29
0.24
0.19
0.14
25°C
85°C
-40°C
0
10
20
30
40
50
60
70
80
90
100 110 120 130
CALA
XMEGA A3BU [DATASHEET]
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8362F–AVR–02/2013
Figure 38-77. 32MHz internal oscillator frequency vs. CALB calibration value.
VCC = 3.0V.
80
75
70
65
60
55
50
45
40
35
30
25
-40°C
25°C
85°C
0
10
20
30
40
50
60
70
CALB
38.10.5 32MHz internal oscillator calibrated to 48MHz
Figure 38-78. 48MHz internal oscillator frequency vs. temperature.
DFLL disabled.
55
54
53
52
51
50
49
48
47
3.3V
3.0V
2.7V
2.2V
1.8V
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
Temperature [°C]
XMEGA A3BU [DATASHEET]
129
8362F–AVR–02/2013
Figure 38-79. 48MHz internal oscillator frequency vs. temperature.
DFLL enabled, from the 32.768kHz internal oscillator.
48.15
48.05
47.95
47.85
47.75
47.65
47.55
47.45
3.3V
3.0V
2.7V
2.2V
1.8V
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
Temperature [°C]
Figure 38-80. 48MHz internal oscillator CALA calibration step size.
VCC = 3.0V.
0.40%
0.35%
0.30%
0.25%
0.20%
0.15%
25°C
85°C
-40°C
0
16
32
48
64
80
96
112
128
CALA
XMEGA A3BU [DATASHEET]
130
8362F–AVR–02/2013
38.11 Two-Wire Interface characteristics
Figure 38-81.SDA hold time vs. temperature.
500
450
400
350
300
250
200
150
100
50
3
2
1
0
-45 -35 -25 -15
-5
5
15
25
35
45
55
65
75
85
Temperature [°C]
Figure 38-82. SDA hold time vs. supply voltage.
500
450
400
350
300
250
200
150
100
50
3
2
1
0
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
VCC [V]
XMEGA A3BU [DATASHEET]
131
8362F–AVR–02/2013
38.12 PDI characteristics
Figure 38-83. Maximum PDI frequency vs. VCC
.
36
31
26
21
16
11
-40°C
25°C
85°C
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
VCC [V]
XMEGA A3BU [DATASHEET]
132
8362F–AVR–02/2013
39. Errata
39.1 ATxmega256A3BU
39.1.1 Rev. G
AWeX fault protection restore is not done correct in Pattern Generation Mode
1. AWeX fault protection restore is not done correctly in Pattern Generation Mode
When a fault is detected the OUTOVEN register is cleared, and when fault condition is cleared, OUTOVEN is
restored according to the corresponding enabled DTI channels. For Common Waveform Channel Mode (CWCM),
this has no effect as the OUTOVEN is correct after restoring from fault. For Pattern Generation Mode (PGM),
OUTOVEN should instead have been restored according to the DTILSBUF register.
Problem fix/Workaround
For CWCM no workaround is required.
For PGM in latched mode, disable the DTI channels before returning from the fault condition. Then, set correct
OUTOVEN value and enable the DTI channels, before the direction (DIR) register is written to enable the correct
outputs again.
For PGM in cycle-by-cycle mode there is no workaround.
39.1.2 Rev. E-F
Not sampled
39.1.3 rev. D
ADC unsigned mode non-functional
ADC increased noise when using internal 1.0V reference at low temperature
DAC offset calibration range too small when using AVCC as reference
Register ANAINIT in MCUR will always read as zero
CPU clock frequency limited to 24MHz
CPU clock frequency limited to 20MHz if using both application section and boot section
High active current consumption at low frequency
USB Transfer Complete interrupt generated for each IN packet in Multipacket Mode
Disabling the USART transmitter does not automatically set the TxD pin direction to input
AWeX PWM output after fault restarted with wrong values
TWI inactive bus timeout from BUSY bus state
TOSC32 as RTC32 clock output Non-functional
Pending asynchronous RTC32 interrupts will not wake up device
Pending full asynchronous pin change interrupts will not wake the device
1. ADC Unsigned mode non-functional
The ADC Unsigned mode is non-functional.
Problem fix/Workaround
XMEGA A3BU [DATASHEET]
133
8362F–AVR–02/2013
None, use the ADC in signed mode also for single ended conversions.
2. ADC increased noise when using internal 1.0V reference at low temperature
When operating at -40C and using internal 1.0V reference the RMS noise will be up 4LSB.
Problem fix/Workaround
Use averaging tof multiple samples to remove noise.
3. DAC offset calibration range too small when using AVCC as reference
If using AVCC as reference, the DAC offset calibration will not totally remove the offset error. Offset could be up to
100LSB after calibration.
Problem fix/Workaround
Offset adjustment must be partly handled in software.
4. Register ANAINIT in MCUR will always read as zero
The ANAINIT register in the MCUR module will always be read as zero even if written to a different value. The
actual content of the register is correct.
Problem fix/Workaround
Do not use software that reads these registers to get the Analog Initialization configuration.
5. CPU clock frequency limited to 24MHz
The CPU clock must never exceed 24MHz for any supply level.
Problem fix/Workaround
None.
6. CPU clock frequency limited to 20MHz if using both application section and boot section
The CPU clock frequency must never exceed 20MHz when jumping between flash application section and boot
section or executing code from one section and reading (LPM) from the other. If exceeding this frequency the first
instruction/read will be read as NOP/0x00.
These conditions occur when:
• Executing code in one section and jumping (JMP, CALL, RET, branch) to other section.
• Interrupt table is located in different flash section than the code is executed from.
• Using LPM reading the other flash section than the code is executed from.
• Reading signature rows
• Running CRC and the address crosses the boundary between the two sections.
Problem fix/Workaround
For all conditions except CRC crossing the boundary between the sections, enable the Flash Power Reduction
mode and add a NOP after every LPM instruction. For CRC there is no workaround.
7. High active current consumption at low frequency
The current consumption in Active mode is higher than specified for all frequencies below 12MHz. The extra cur-
rent consumption increases with supply level and lower frequency (see Figure 39-1 on page 135).
XMEGA A3BU [DATASHEET]
134
8362F–AVR–02/2013
Problem fix/Workaround
None, avoid running at low frequenices and use higher frequnecies in compination with sleep modes where
possible.
Figure 39-1. Current consumption increase vs. VCC voltage and CPU clock frequency
3500
3000
3.6V
2500
3.3V
2000
3.0V
2.7V
1500
2.2V
1000
1.8V
500
0
0
2
4
6
8
10
12
14
Frequency (MHz)
8. USB Transfer Complete interrupt generated for each IN packet in Multipacket Mode
When multipacket is used, a Transfer Complete interrupt will be generated for each IN packet transferred on USB
line instead of just at the end of the multipacket transfer.
Problem fix/Workaround
Ignore interrupt until multipacket is complete.
9. Disabling the USART transmitter does not automatically set the TxD pin direction to input
If the USART transmitter is idle with no frames to transmit, setting TXEN to zero will not automatically set the TxD
pin direction to input.
Problem fix/Workaround
The TxD pin direction can be set to input using the Port DIR register. Using Port DIR register to set direction to
input only will be immediate and ongoing transmissions will be truncated.
10. AWeX PWM output after fault restarted with wrong values
When recovering from fault state, the PWM output will drive wrong values to the port for up to 2x CLKPER + 1
CLKPER4 cycles.
Problem fix/Workaround
If the glitch can not be tolerated or not filtered out by external components the following sequence can be used in
Latched Mode for restaring without glitch:
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1. Disable DTI outputs (Write DTICCxEN to 0).
2. Clear fault flag.
3. Wait for Overflow.
4. Re-enable DTI (Write DTICCxEN to 1).
5. Set pin direction to Output.
This will remove the glitch, but the following period will be shorter.
In Cycle-by-cycle mode the same procedure can be followed as long as the Pattern Generation Mode is not
enabled.
For Pattern Generation Mode, there is no workaround.
11. TWI inactive bus timeout from BUSY bus state
If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a START is detected, the
transaction will be dropped.
Problem fix/Workaround
None.
12. TOSC32 as RTC32 clock output Non-functional
Selecting TOSC32 as clock output is Non-functional.
Problem fix/Workaround
If 32kHz clock output is required, the internal 32.768kHz oscillator can be selected as source for RTC32 and out-
put to pin.
13. Pending asynchronous RTC32-interrupts will not wake up device
Asynchronous Interrupts from the Real-Time-Counter that is pending when the sleep instruction is executed, will
be ignored until the device is woken from another source or the source triggers again.
Problem fix/Workaround
In software, read the RTC32 CNT value before executing the SLEEP instruction and check that it will not to gener-
ate overflow or compare match interrupt during the last CPU instruction before the SLEEP instruction is executed.
In addition check that no previous RTC interrupts are pending.
14. Pending full asynchronous pin change interrupts will not wake the device
Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the sleep instruction is
executed, will be ignored until the device is woken from another source or the source triggers again. This applies
when entering all sleep modes where the System Clock is stopped.
Problem fix/Workaround
Use limited asynchronous pin-change interrupts instead.
39.1.4 rev A-C
Not sampled.
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40. Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. The referring revisions in this
section are referring to the document revision.
40.1 8362F – 02/2013
1.
2.
3.
4.
5.
6.
Updated the whole contents with an updated template (Atmel new logo, table tags and paragraph tags).
Updated Figure 2-1 on page 3. Pin 15 and Pin 25 are VCC and not VDD.
Updated Figure 16-7 on page 33, “Input sensing system overview.”
Updated Figure 31-1 on page 53, “Analog comparator overview.”
Removed TWID from Table 33-4 on page 58, “Port D - alternate functions.”
Updated Table 37-30 on page 84. Added ESR parameter in “External 16MHz crystal oscillator and XOSC characteristics.”
40.2 8362E – 12/11
1.
2.
3.
4.
5.
6.
7.
Updated “Electrical Characteristics” on page 69.
Updated “Typical Characteristics” on page 91.
Added “Errata” on page 133.
Updated “Packaging information” on page 67.
Editing and figure updates
Tape and reel added in “Ordering Information” on page 2
Pin numbers for GND and VCC in Table 33-4 on page 62 have been corrected
40.3 8362D - 03/11
1.
2.
3.
Preliminary removed from the front page.
Updated the datasheet according to the Atmel new brand style guide.
Editing update.
40.4 8362C - 02/11
1.
2.
2.
3.
Updated “Electrical Characteristics” on page 69.
Added “Typical Characteristics” on page 91
Added “Errata” on page 133.
Editing update.
40.5 8362B - 11/09
1.
Updated “Ordering Information” on page 2.
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40.6 8362A - 10/09
1.
Initial version.
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Table Of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Pinout/Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1
Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4. Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.1
Recommended reading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5. Capacitive touch sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
6. AVR CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
ALU - Arithmetic Logic Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Program Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Stack and Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
7. Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Flash Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Fuses and Lock bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
I/O Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Data Memory and Bus Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.10 Device ID and Revision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.11 JTAG Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.12 I/O Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.13 Flash and EEPROM Page Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8. DMAC – Direct Memory Access Controller . . . . . . . . . . . . . . . . . . . 15
8.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8.2
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
9. Event System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
9.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
9.2
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
10. System Clock and Clock options . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
10.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
10.3 Clock Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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11. Power Management and Sleep Modes . . . . . . . . . . . . . . . . . . . . . . 21
11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
11.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
11.3 Sleep Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
12. System Control and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
12.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
12.3 Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
12.4 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
13. WDT – Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
13.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
14. Battery Backup System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
14.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
15. Interrupts and Programmable Multilevel Interrupt Controller . . . . . . 28
15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
15.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
15.3 Interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
16. I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
16.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
16.3 Output Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
16.4 Input sensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
16.5 Alternate Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
17. TC0/1 – 16-bit Timer/Counter Type 0 and 1 . . . . . . . . . . . . . . . . . . 34
17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
17.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
18. TC2 – Timer/Counter Type 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
18.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
19. AWeX – Advanced Waveform Extension . . . . . . . . . . . . . . . . . . . . . 37
19.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
19.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
20. Hi-Res – High Resolution Extension . . . . . . . . . . . . . . . . . . . . . . . . 38
20.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
20.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
21. RTC32 – 32-bit Real-Time Counter . . . . . . . . . . . . . . . . . . . . . . . . . 39
21.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
22. USB – Universal Serial Bus Interface . . . . . . . . . . . . . . . . . . . . . . . 40
22.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
22.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
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23. TWI – Two-Wire Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
23.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
23.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
24. SPI – Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
24.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
24.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
25. USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
25.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
25.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
26. IRCOM – IR Communication Module . . . . . . . . . . . . . . . . . . . . . . . . 45
26.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
26.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
27. AES and DES Crypto Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
27.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
27.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
28. CRC – Cyclic Redundancy Check Generator . . . . . . . . . . . . . . . . . 47
28.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
28.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
29. ADC – 12-bit Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . 48
29.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
29.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
30. DAC – 12-bit Digital to Analog Converter . . . . . . . . . . . . . . . . . . . . 50
30.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
30.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
31. AC – Analog Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
31.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
31.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
32. Programming and Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
32.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
32.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
33. Pinout and Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
33.1 Alternate Pin Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
33.2 Alternate Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
34. Peripheral Module Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
35. Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
36. Packaging information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
36.1 64A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
36.2 64M2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
37. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
37.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
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37.2 General Operating Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
37.3 Current consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
37.4 Wake-up time from sleep modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
37.5 I/O Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
37.6 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
37.7 DAC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
37.8 Analog Comparator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
37.9 Bandgap and Internal 1.0V Reference Characteristics. . . . . . . . . . . . . . . . . . 79
37.10 Brownout Detection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
37.11 External Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
37.12 Power-on Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
37.13 VBAT and Battery Backup Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
37.14 Flash and EEPROM Memory Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 81
37.15 Clock and Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
37.16 SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
37.17 Two-Wire Interface Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
38. Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
38.1 Current consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
38.2 I/O Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
38.3 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
38.4 DAC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
38.5 Analog Comparator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
38.6 Internal 1.0V reference Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
38.7 BOD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
38.8 External Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
38.9 Power-on Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
38.10 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
38.11 Two-Wire Interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
38.12 PDI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
39. Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
39.1 ATxmega256A3BU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
40. Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
40.1 8362F – 02/2013. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
40.2 8362E – 12/11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
40.3 8362D - 03/11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
40.4 8362C - 02/11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
40.5 8362B - 11/09 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
40.6 8362A - 10/09 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table Of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
XMEGA A3BU [DATASHEET]
iv
8362F–AVR–02/2013
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