ATA6829_09 [ATMEL]
Dual Triple DMOS Output Driver with Serial Input Control; 带串行输入控制三双DMOS输出驱动器
| 型号： | ATA6829_09 |
| 厂家： | 
ATMEL |
| 描述： | Dual Triple DMOS Output Driver with Serial Input Control |
| 文件： | 总16页 (文件大小：619K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Supply Voltage up to 40V
• RDSon Typically 0.5Ω at 25°C, Maximum 1.1Ω at 150°C
• Up to 1.5A Output Current
• Three High-side and Three Low-side Drivers Usable as Single Outputs or Half Bridges
• Capable to Switch all Kinds of Loads such as DC Motors, Bulbs, Resistors, Capacitors
and Inductors
• PWM Capability for Each Output Controlled by External PWM Signal
• No Shoot-through Current
Dual Triple
DMOS Output
Driver with
Serial Input
Control
• Very Low Quiescent Current IS < 5 µA in Standby Mode over Total Temperature Range
• Outputs Short-circuit Protected
• Selective Overtemperature Protection for Each Switch and Overtemperature
Prewarning
• Undervoltage Protection
• Various Diagnostic Functions such as Shorted Output, Open Load, Overtemperature
and Power-supply Fail Detection
• Serial Data Interface, Daisy Chain Capable, up to 2 MHz Clock Frequency
• SO16 Power Package
1. Description
The ATA6829 is a fully protected driver interface designed in 0.8-µm BCDMOS tech-
nology. It is used to control up to six different loads by a microcontroller in automotive
and industrial applications.
ATA6829
Each of the three high-side and three low-side drivers is capable to drive currents up
to 1.5A. Each driver is freely configurable and can be controlled separately from a
standard serial data interface. Therefore, all kinds of loads such as bulbs, resistors,
capacitors and inductors can be combined. The IC design especially supports the
applications of H-bridges to drive DC motors. The capability to control each output
with an external PWM signal opens additional applications.
Protection is guaranteed regarding short-circuit conditions, overtemperature and
undervoltage. Various diagnostic functions and a very low quiescent current in
stand-by mode opens a wide range of applications. Automotive qualification (protec-
tion against conducted interferences, EMC protection and 2-kV ESD protection) gives
added value and enhanced quality for exacting requirements of automotive
applications.
4531G–BCD–07/09
Figure 1-1. Block Diagram
OUT3H
OUT2H
OUT1H
4
14
13
Charge
pump
Fault
detect
Fault
Fault
detect
detect
12
6
VS
DI
O
H
S
3
L
S
3
H
S
2
L
S
2
H
L
S
1
S
R
R
O
C
S
P
H
3
P
L
3
P
H
2
P
L
2
P
H
1
P
L
1
7
L
S
S
CLK
D
1
I
UV -
protection
Control
logic
Input register
Output register
Serial interface
11
5
Power-on
VCC
CS
reset
n. n. n. n. n. n.
P
S
F
I
N
H
O
V
L
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
T
P
u. u. u. u. u. u.
S
1
10
DO
16
GND
GND
GND
8
PWM
Thermal
protection
Fault
detect
Fault
detect
Fault
detect
9
1
15
3
2
OUT3L
OUT2L
OUT1L
2
ATA6829
4531G–BCD–07/09
ATA6829
2. Pin Configuration
Figure 2-1. Pinning PSO16
GND
OUT1L
OUT3L
OUT3H
CS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
OUT2L
OUT2H
OUT1H
VS
DI
VCC
CLK
DO
PWM
GND
Table 2-1.
Pin Description
Pin
Symbol
Function
1
GND
Ground; reference potential; internal connection to pin 9 and pin 16; connection to heat slug
Low-side driver output 1; power MOS open drain with internal reverse diode; short-circuit protection;
overtemperature protection; diagnosis for short and open load; PWM ability
2
3
4
OUT1L
OUT3L
OUT3H
Low-side driver output 3; see pin 2
High-side driver output 3; power MOS open source with internal reverse diode; short-circuit protection;
overtemperature protection; diagnosis for short and open load; PWM ability
Chip select input; 5-V CMOS logic level input with internal pull up;
low = serial communication is enabled, high = disabled
5
6
7
CS
DI
Serial data input; 5-V CMOS logic level input with internal pull down; receives serial data from the control
device; DI expects a 16-bit control word with LSB being transferred first
Serial clock input; 5-V CMOS logic level input with internal pull down; controls serial data input interface
and internal shift register (fmax = 2 MHz)
CLK
PWM input; 5-V CMOS logic level input with internal pull down; receives PWM signal to control outputs
which are selected for PWM mode by the serial data interface, high = outputs on, low = outputs off
8
9
PWM
GND
Ground; see pin 1
Serial data output; 5-V CMOS logic-level tri-state output for output (status) register data; sends 16-bit
status information to the microcontroller (LSB is transferred first); output will remain tri-stated unless
device is selected by CS = low, therefore, several ICs can operate on one data-output line only.
10
DO
11
12
13
14
15
16
VCC
VS
Logic supply voltage (5V)
Power supply for high-side output stages OUT1H, OUT2H, OUT3H, internal supply
High-side driver output 1; see pin 4
High-side driver output 2; see pin 4
Low-side driver output 2; see pin 2
OUT1H
OUT2H
OUT2L
GND
Ground; see pin 1
3
4531G–BCD–07/09
3. Functional Description
3.1
Serial Interface
Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized
to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be trans-
ferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS
is high, pin DO is in tri-state condition. This output is enabled on the falling edge of CS. Output
data will change their state with the rising edge of CLK and stay stable until the next rising edge
of CLK appears. LSB (bit 0, TP) is transferred first.
Figure 3-1. Data Transfer
CS
SRR
LS1
HS1
LS2
HS2
LS3
PL1
DI
HS3
PH1
PL2
PH2
PL3
PH3
OLD OCS
SI
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
DO
TP
S1L
S1H
S2L
S2H
S3L
S3H
n. u.
n. u.
n. u.
n. u.
n. u.
n. u.
OVL
INH PSF
Table 3-1.
Input Data Protocol
Bit
Input Register Function
Status register reset (high = reset; the bits PSF and OVL in the output
data register are set to low)
0
SRR
1
2
LS1
HS1
LS2
HS2
LS3
HS3
PL1
PH1
PL2
PH2
PL3
PH3
OLD
OCS
Controls output LS1 (high = switch output LS1 on)
Controls output HS1 (high = switch output HS1 on)
3
See LS1
4
See HS1
5
See LS1
6
See HS1
7
Output LS1 additionally controlled by PWM Input
8
Output HS1 additionally controlled by PWM Input
9
See PL1
10
11
12
13
14
See PH1
See PL1
See PH1
Open load detection (low = on)
Overcurrent shutdown (high = overcurrent shutdown is active)
Software inhibit; low = standby, high = normal operation
(data transfer is not affected by standby function because the digital part
is still powered)
15
SI
4
ATA6829
4531G–BCD–07/09
ATA6829
Table 3-2.
Output Data Protocol
Output (Status)
Bit
Register
Function
Temperature prewarning: high = warning
0
TP
Normal operation: high = output is on, low = output is off
Open-load detection: high = open load, low = no open load
(correct load condition is detected if the corresponding output is switched
off); not affected by SRR
1
2
Status LS1
Status HS1
Normal operation: high = output is on, low = output is off
Open-load detection: high = open load, low = no open load
(correct load condition is detected if the corresponding output is switched
off); not affected by SRR
3
4
Status LS2
Status HS2
Status LS3
Status HS3
n. u.
Description see LS1
Description see HS1
Description see LS1
Description see HS1
Not used
5
6
7
8
n. u.
Not used
9
n. u.
Not used
10
11
12
n. u.
Not used
n. u.
Not used
n. u.
Not used
Over-load detected: set high, when at least one output is switched off by
a short-circuit condition or an overtemperature event. Bits 1 to 6 can be
used to detect the affected switch.
13
OVL
(open-load detection bit OLD = high)
Inhibit: this bit is controlled by software (bit SI in input register)
High = standby, low = normal operation
14
15
INH
PSF
Power-supply fail: undervoltage at pin VS detected
After power-on reset, the input register has the following status:
Bit 15 Bit 14
Bit 13
OLD
Bit 12
PH3
Bit 11
PL3
Bit 10
PH2
Bit 9
PL2
Bit 8
PH1
Bit 7
PL1
Bit 6
HS3
Bit 5
LS3
Bit 4
HS2
Bit 3
LS2
Bit 2
HS1
Bit 1
LS1
Bit 0
SRR
SI
OCS
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
The following patterns are used to enable internal test modes of the IC. It is not recommended to use these patterns during
normal operation.
Bit 15 Bit 14
Bit 13
(OCS)
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(HS3)
(LS3)
(HS2)
(LS2)
(HS1) (LS1)
(SRR)
H
H
H
H
H
H
H
H
H
H
L
L
H
L
L
L
H
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
5
4531G–BCD–07/09
3.2
3.3
Power-supply Fail
In case of undervoltage at pin VS, the Power-Supply Fail bit (PSF) in the output register is set
and all outputs are disabled. To detect an undervoltage, its duration has to last longer than the
undervoltage detection delay time tdUV. The outputs are enabled immediately when supply volt-
age recovers normal operation value. The PSF bit stays high until it is reset by the SRR bit in the
input register.
Open-load Detection
If the open-load detection bit (OLD) is set to low, a pull-up current for each high-side switch and
a pull-down current for each low-side switch is turned on (open-load detection current IOUT1-3). If
the current through the external load does not reach the open-load detection current, the corre-
sponding bit of the output in the output register is set to high.
Switching on an output stage with OLD bit set to low disables the open-load function for this
output.
3.4
Overtemperature Protection
If the junction temperature of one ore more output stages exceeds the thermal prewarning
threshold, TjPW set, the temperature prewarning bit (TP) in the output register is set. When the
temperature falls below the thermal prewarning threshold, TjPW reset, the bit TP is reset. The TP
bit can be read without transferring a complete 16-bit data word. The status of TP is available at
pin DO with the falling edge of CS. After the microcontroller has read this information, CS is set
high and the data transfer is interrupted without affecting the status of input and output registers.
If the junction temperature of an output stage exceeds the thermal shutdown threshold,
T
j switch off, the affected output is disabled and the corresponding bit in the output register is set to
low. Additional the overload detection bit (OVL) in the output register is set. The output can be
enabled again when the temperature falls below the thermal shutdown threshold, Tjswitch on and
the SRR bit in the input register is set to high. Hysteresis of thermal prewarning and shutdown
threshold avoids oscillations.
3.5
Short-circuit Protection
The output currents are limited by a current regulator. Overcurrent detection is activated by writ-
ing a high to the OCS bit in the input register. When the current in an output stage exceeds the
overcurrent limitation and shut-down threshold, it is switched off after a delay time (tdSd). The
over-load detection bit (OVL) is set and the corresponding status bit in the output register is set
to low. For OCS = low the overcurrent shutdown is inactive and the OVL bit is not set by an over-
current. By writing a high to the SRR bit in the input register the OVL bit is reset and the disabled
outputs are enabled.
3.6
Inhibit
The SI bit in the input register has to be set to zero to inhibit the ATA6829.
All output stages are then turned off but the serial interface stays active. The current consump-
tion is reduced to less than 5 µA at pin VS and less than 100 µA at pin VCC. The output stages
can be activated again by bit SI = 1.
6
ATA6829
4531G–BCD–07/09
ATA6829
4. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
All values refer to GND pins.
Parameters
Pin
Symbol
Value
Unit
Supply voltage
12
VVS
–0.3 to +40
V
Supply voltage
t < 0.5s; IS > –2A
12
VVS
–1
V
Logic supply voltage
Logic input voltage
Logic output voltage
Input current
11
5 to 8
10
VVCC
VCS, VDI, VCLK, VPWM
VDO
–0.3 to +7
–0.3 to VVCC + 0.3
–0.3 to VVCC + 0.3
–10 to +10
V
V
V
5 to 8
10
ICS, IDI, ICLK, IPWM
IDO
IOut3H, IOut2H, IOut1H
IOut3L, IOut2L, IOut1L
IOut3H, IOut2H, IOut1H
IOut3L, IOut2L, IOut1L
mA
mA
Output current
–10 to +10
2 to 4
13 to 15
Output current
Output voltage
Internally limited, see output specification
–0.3 to +40
2 to 4
13 to 15
V
A
2 to 4
13 to 15
towards pin 12
Reverse conducting current
(tpulse = 150 µs)
IOut3H, IOut2H, IOut1H
IOut3L, IOut2L, IOut1L
17
Junction temperature range
Storage temperature range
TJ
–40 to +150
–55 to +150
°C
°C
TSTG
5. Thermal Resistance
Parameters
Test Conditions
Measured to heat slug
GND pins 1, 9 and 16
Symbol
RthJP
Value
5
Unit
K/W
K/W
Junction pin
Junction ambient
RthJA
30
6. Operating Range
Parameters
Symbol
Value
VUV(1) to 40
4.75 to 5.25
–0.3 to VVCC
2
Unit
V
Supply voltage
VVS
Logic supply voltage
Logic input voltage
VVCC
V
VCS,VDI, VCLK, VPWM
V
Serial interface clock frequency
PWM input frequency
Junction temperature range
fCLK
fPWM
Tj
MHz
kHz
°C
1
–40 to +150
Note:
1. Threshold for undervoltage detection.
7
4531G–BCD–07/09
7. Noise and Surge Immunity
Parameters
Test Conditions
ISO 7637-1
Value
Level 4(1)
Level 5
2 kV
Conducted interferences
Interference suppression
ESD (Human Body Model)
ESD (Machine Model)
VDE 0879 Part 2
ESD S 5.1
JEDEC A115A
200 V
Note:
1. Test pulse 5: Vsmax = 40V.
8. Electrical Characteristics
7.5V < VS < 40V; 4.75V < VCC < 5.25V; INH = High; -40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins.
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
1
Current Consumption
1.1
Quiescent current VS
VVS < 20V, SI = low
12
11
IVS
1
5
µA
µA
A
A
4.75V < VVCC < 5.25V,
SI = low
1.2
1.3
1.4
Quiescent current VCC
IVCC
60
100
VVS < 20V normal
operating, all outputs
off, input register bit 13
(OLD) = high
Supply current VS
Supply current VCC
12
11
IVS
4
6
mA
µA
A
A
4.75V < VVCC < 5.25V,
normal operating
IVCC
350
650
1.5
1.6
2
Discharge current VS
Discharge current VS
VVS = 32.5V, INH = low
VVS = 40V, INH = low
12
12
IVS
IVS
0.5
2.5
5.5
10
mA
mA
A
A
Undervoltage Detection, Power-on Reset
Power-on reset
threshold
2.1
2.2
2.3
2.4
2.5
11
VVCC
tdPor
VUv
3.2
30
3.9
95
4.4
190
7.0
V
µs
V
A
A
A
A
A
Power-on reset delay
After switching on VCC
time
Undervoltage-detection
VCC = 5V
12
12
5.6
threshold
Undervoltage-detection
VCC = 5V
ΔVUv
tdUV
0.6
V
hysteresis
Undervoltage-detection
delay time
10
40
µs
3
Thermal Prewarning and Shutdown
3.1
Thermal prewarning set
TjPW set
120
105
145
130
170
155
°C
°C
B
B
Thermal prewarning
reset
3.2
TjPW reset
Thermal prewarning
hysteresis
3.3
3.4
ΔTjPW
15
K
B
B
Thermal shutdown off
Tj switch off
150
175
200
°C
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of
final level. Device not in standby for t > 1 ms.
2. Delay time between rising/falling edge of input signal at pin PWM and switch on/off output stages to 90% of final level.
3. Difference between switch-on and switch-off delay time of input signal at pin PWM to output stages in PWM mode.
8
ATA6829
4531G–BCD–07/09
ATA6829
8. Electrical Characteristics (Continued)
7.5V < VS < 40V; 4.75V < VCC < 5.25V; INH = High; -40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins.
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
3.5
Thermal shutdown on
Tj switch on
135
160
185
°C
B
Thermal shutdown
hysteresis
3.6
ΔTj switch off
15
K
B
Ratio thermal shutdown
off/thermal prewarning
set
Tj switch off/
TjPW set
3.7
3.8
1.05
1.05
1.2
B
Ratio thermal shutdown
on/thermal prewarning
reset
Tj switch on/
TjPW reset
1.2
B
4
Output Specification (OUT1-OUT3)
4, 13,
14
4.1
4.2
4.3
IOut 1-3 H = –1.3A
On resistance
RDSOn1-3H
1.1
1.1
Ω
Ω
A
A
A
IOut 1-3 L = 1.3A
2, 3, 15 RDSOn1-3L
High-side output
leakage current
VOut 1-3 H = 0V
output stages off
4, 13,
IOut1-3H
14
,
–5
µA
Low-side output
leakage current
VOut 1-3 L = VVS,
output stages off
4.4
4.5
4.6
4.7
2, 3, 15
IOut1-3L
VOut1-3 – VVS
VOut1-3L
5
µA
V
A
A
A
A
High-side switch
reverse diode forward IOut = 1.5A
voltage
4, 13,
14
1.5
Low-side switch reverse
diode forward voltage
IOut 1-3 L = –1.5A
2, 3, 15
–1.5
–2.5
V
High-side overcurrent
limitation and shutdown
threshold
4, 13,
14
IOut1-3H
–2
2
–1.5
2.5
A
Low-side overcurrent
limitation and shutdown
threshold
4.8
2, 3, 15
IOut1-3L
1.5
A
A
Overcurrent shutdown
delay time
4.9
tdSd
IOut1-3H
IOut1-3L
tdon
10
–2.5
0.2
40
–0.2
2.5
20
µs
mA
mA
µs
A
A
A
A
A
A
High-side open load
detection current
Input register bit 13
(OLD) = low, output off
4, 13,
14
4.10
4.11
4.12
4.13
4.14
Low-side open load
detection current
Input register bit 13
(OLD) = low, output off
2, 3, 15
High-side output switch VVS = 13V
on delay(1),(2)
Load = 30Ω
R
Low-side output switch VVS = 13V
on delay(1),(2)
RLoad = 30Ω
tdon
20
µs
High-side output switch VVS =13V
off delay(1),(2)
RLoad = 30Ω
tdoff
20
µs
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of
final level. Device not in standby for t > 1 ms.
2. Delay time between rising/falling edge of input signal at pin PWM and switch on/off output stages to 90% of final level.
3. Difference between switch-on and switch-off delay time of input signal at pin PWM to output stages in PWM mode.
9
4531G–BCD–07/09
8. Electrical Characteristics (Continued)
7.5V < VS < 40V; 4.75V < VCC < 5.25V; INH = High; -40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins.
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Low-side output switch VVS =13V
4.15
tdoff
3
µs
A
off delay(1),(2)
RLoad = 30Ω
Dead time between
4.16 corresponding high-
and low-side switches
VVS =13V
RLoad = 30Ω
tdon – tdoff
1
µs
A
ΔtdPWM
4.17
VVS = 13V
RLoad = 30Ω
ΔtdPWM =
tdon – tdoff
20
7
µs
µs
A
A
low-side switch(3)
ΔtdPWM
4.18
VVS = 13V
RLoad = 30Ω
ΔtdPWM =
tdon – tdoff
3
high-side switch(3)
5
Logic Inputs DI, CLK, CS, PWM
Input voltage low-level
threshold
0.3 ×
VVCC
5.1
5-8
5-8
VIL
VIH
ΔVI
IPD
IPU
V
V
A
A
A
A
A
Input voltage high-level
threshold
0.7 ×
VVCC
5.2
5.3
5.4
5.5
Hysteresis of input
voltage
5-8
50
10
700
65
mV
µA
µA
Pull-down current
Pins DI, CLK, PWM
VDI, VCLK, VPWM = VCC
VCS = 0V
6, 7, 8
5
Pull-up current
Pin CS
–65
–10
6
Serial Interface – Logic Output DO
6.1
Output-voltage low level IDOL = 2 mA
10
10
VDOL
VDOH
0.4
10
V
V
A
A
Output-voltage high
IDOL = –2 mA
level
VVCC
0.7 V
–
6.2
Leakage current
(tri-state)
VCS = VCC
0V < VDO < VVCC
6.3
7
10
IDO
–10
µA
A
Inhibit Input – Timing
Delay time from
standby to normal
operation
7.1
tdINH
100
µs
A
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of
final level. Device not in standby for t > 1 ms.
2. Delay time between rising/falling edge of input signal at pin PWM and switch on/off output stages to 90% of final level.
3. Difference between switch-on and switch-off delay time of input signal at pin PWM to output stages in PWM mode.
10
ATA6829
4531G–BCD–07/09
ATA6829
9. Serial Interface – Timing
No. Parameters
Test Conditions
Pin
Timing Chart No.(1)
Symbol
Min.
Typ.
Max.
Unit
Type*
DO enable after CS
falling edge
8.1
8.2
CDO = 100 pF
10
1
tENDO
200
ns
D
DO disable after CS
rising edge
CDO = 100 pF
10
2
tDISDO
200
ns
D
8.3 DO fall time
8.4 DO rise time
8.5 DO valid time
8.6 CS setup time
8.7 CS setup time
8.8 CS high time
8.9 CLK high time
8.10 CLK low time
8.11 CLK period time
8.12 CLK setup time
8.13 CLK setup time
8.14 DI setup time
8.15 DI hold time
CDO = 100 pF
CDO = 100 pF
CDO = 100 pF
10
10
10
5
-
-
tDOf
tDOr
100
100
200
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
D
D
D
D
D
D
D
D
D
D
D
D
D
10
4
tDOVal
tCSSethl
tCSSetlh
tCSh
225
225
500
225
225
500
225
225
40
5
8
5
9
7
5
tCLKh
7
6
tCLKl
7
-
tCLKp
7
7
tCLKSethl
tCLKSetlh
tDIset
7
3
6
11
12
6
tDIHold
40
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note: 1. See Figure 9-1 on page 12
11
4531G–BCD–07/09
Figure 9-1. Serial Interface Timing with Chart Number
1
2
CS
DO
9
CS
4
7
CLK
5
3
6
8
DI
11
CLK
10
12
DO
Inputs DI, CLK, CS: High level = 0.7 x VCC, low level = 0.3 x VCC
Output DO: High level = 0.8 x VCC, low level = 0.2 x VCC
12
ATA6829
4531G–BCD–07/09
ATA6829
10. Application Circuit
VCC
U5021M
M
M
Watchdog
OUT3H
OUT2H
OUT1H
13
4
14
Charge
pump
VS
Fault
detect
Fault
detect
Fault
detect
VBatt
12
6
VS
DI
0 to 40 V
+
O
P
H
3
P
L
3
P
H
2
P
L
2
P
H
1
P
L
1
H
S
3
L
S
3
H
S
2
L
S
2
H
L
S
1
S
R
R
O
C
S
7
L
S
S
I
D
1
CLK
UV -
Control
logic
protection
Input register
Serial interface
VCC
11
Output register
Power-on
reset
5
VCC
CS
5 V
n. n. n. n. n. n.
P
S
F
I
O
V
L
H
L
S
3
H
S
2
L
S
2
H
L
T
P
+
u. u. u. u. u. u.
S
3
S
S
N
H
1
1
10
DO
16
GND
GND
GND
8
Thermal
protection
PWM
Fault
detect
Fault
detect
Fault
9
detect
1
15
3
2
OUT3L
OUT2L
OUT1L
VCC
10.1 Application Notes
It is strongly recommended to connect the blocking capacitors at VCC and VS as close as possi-
ble to the power supply and GND pins.
Recommended value for capacitors at VS:
Electrolytic capacitor C > 22 µF in parallel with a ceramic capacitor C = 100 nF. Value for elec-
trolytic capacitor depends on external loads, conducted interferences and reverse conducting
current IOut1,2,3 (see “Absolute Maximum Ratings” on page 7).
Recommended value for capacitors at VCC
:
Electrolytic capacitor C > 10 µF in parallel with a ceramic capacitor C = 100 nF.
To reduce thermal resistance it is recommended to place cooling areas on the PCB as close as
possible to the GND pins. Negative spikes at the output pins (e.g. negative spikes caused by an
inductive load switched off with a high side driver) may activate the overtemperature protection
function of the ATA6829. In this condition, the affected output will be switched off. If this behavior
is not acceptable or compatible with the specific application functionally, it is necessary, that for
switching on required outputs again, the SRR bit (Status Register Reset) is set, to ensure a reset
of the overtemperature function.
13
4531G–BCD–07/09
11. Ordering Information
Extended Type Number
Package
Remarks
ATA6829-T3QY
PSO16
Power package with heat slug, taped and reeled, lead-free
12. Package Information
heat slug exposed
8
1
0.4 A B
Package: PSO16
with heat slug
Dimensions in mm
16
9
6.86
technical drawings
according to DIN
specifications
9.9±0.1
A
0.41
3.99 max.
B
1.27 nom.
4.27±0.4
6±0.2
7 x 1.27 = 8.89 nom.
Drawing-No.: 6.541-5050.01-4
Issue: 2; 18.08.05
14
ATA6829
4531G–BCD–07/09
ATA6829
13. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
Revision No.
History
4531G-BCD-07/09
• Complete datasheet: T6819 deleted
• Complete datasheet: T6829 changed in ATA6829
• Ordering Information on page 14 changed
• Package drawing on page 15 changed
4531F-BCD-09/05
15
4531G–BCD–07/09
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