ATA6831-PIPW [ATMEL]
Triple Half-bridge Driver with SP and PWM; 与SP和PWM三重半桥驱动器
| 型号： | ATA6831-PIPW |
| 厂家： | 
ATMEL |
| 描述： | Triple Half-bridge Driver with SP and PWM |
| 文件： | 总17页 (文件大小：294K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Supply Voltage up to 40V
• RDSon Typically 0.8Ω at 25°C, Maximum 1.5Ω at 150°C
• Up to 1.0A Output Current
• Three Half-bridge Outputs Formed by Three High-side and Three Low-side Drivers
• Capable of Switching Loads such as DC Motors, Bulbs, Resistors, Capacitors, and
Inductors
• PWM Capability up to 25 kHz for Each High-side Output Controlled by External PWM
Signal
Triple
• No Shoot-through Current
• Very Low Quiescent Current IS < 5 µA in Standby Mode over Total Temperature Range
• Outputs Short-circuit Protected
• Selective Overtemperature Protection for Each Switch and Overtemperature
Prewarning
Half-bridge
Driver with SPI
and PWM
• Undervoltage Protection
• Various Diagnostic Functions such as Shorted Output, Open Load, Overtemperature
and Power-supply Fail Detection
• Serial Data Interface, Daisy Chain Capable, up to 2 MHz Clock Frequency
• QFN18 Package
ATA6831
1. Description
The ATA6831 provides fully protected driver interfaces designed in SOI technology.
They are used to allow a microcontroller to control up to 3 different loads in automo-
tive and industrial applications.
Each of the 3 high-side and 3 low-side drivers is capable of driving currents up to
1.0A. Due to the enhanced PWM signal (up to 25 kHz) it is possible to generate a
smooth control of, for example, a DC motor without any noise. The drivers are inter-
nally connected to form 3 half-bridges and can be controlled separately from a
standard serial data interface, enabling all kinds of loads, such as bulbs, resistors,
capacitors and inductors, to be combined. The IC design especially supports the
application of H-bridges to drive DC motors.
Protection is guaranteed with respect to short-circuit conditions, overtemperature and
undervoltage. Various diagnostic functions and a very low quiescent current in
standby mode enable a wide range of applications. Automotive qualification (protec-
tion against conducted interferences, EMC protection and 2-kV ESD protection) gives
added value and enhanced quality for exacting requirements of automotive
applications.
4908D–AUTO–09/06
Figure 1-1. Block Diagram
O
S
C
O
L
D
P
H
3
P
L
3
P
H
2
P
L
2
P
H
1
P
L
1
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
S
R
R
S
I
10
11
VS1
VS2
Input register
Ouput register
Serial interface
Charge
pump
P
S
F
I
N
H
O
V
L
n. n. n. n. n. n.
u. u. u. u. u. u.
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
T
P
DI
4
CLK
5
3
CS
DO
UV
protection
Fault
detector
Fault
detector
Fault
detector
9
7
6
VCC
Control
logic
PWM
Power on
reset
8
14
17
18
GND
GND
GND
GND
Fault
detector
Fault
detector
Fault
detector
Thermal
protection
1/2
12/13
15/16
OUT3
OUT2
OUT1
2
ATA6831
4908D–AUTO–09/06
ATA6831
2. Pin Configuration
Figure 2-1. Pinning QFN18
18 17 16 15 14 13
OUT3S
OUT3F
CS
1
2
3
4
5
6
12 OUT2F
11 VS2
10 VS1
DI
9
8
7
VCC
GND
DO
CLK
PWM
Table 2-1.
Pin Description
Pin
Symbol
Function
Sense pin, used only for final testing
1
OUT3S
Half-bridge output 3; formed by internally connecting power MOS high-side switch 3 and low-side switch 3
with internal reverse diodes; short circuit protection; overtemperature protection; diagnosis for short and
open load
2
OUT3F
Chip select input; 5V CMOS logic level input with internal pull-up;
low = serial communication is enabled, high = disabled
3
4
CS
DI
Serial data input; 5V CMOS logic level input with internal pull-down; receives serial data from the control
device; DI expects a 16-bit control word with LSB transferred first
Serial clock input; 5V CMOS logic level input with internal pull-down;
controls serial data input interface and internal shift register (fmax = 2 MHz)
5
6
CLK
PWM
PWM input; 5V CMOS logic level input with internal pull-down
Serial data output; 5V CMOS logic-level tri-state output for output (status) register data; sends 16-bit status
information to the microcontroller (LSB transferred first); output will remain tri-stated unless device is
selected by CS = low; this allows several ICs to operate on only one data-output line
7
DO
8
9
GND
VCC
VS1
VS2
Ground
Logic supply voltage (5V)
10
11
Power supply for output stages OUT1 and OUT2; internal supply
Power supply for output stages OUT2 and OUT3; internal supply
Half-bridge output 2; formed by internally connected power MOS high-side switch 2 and low-side switch 2
with internal reverse diodes; short circuit protection; overtemperature protection; diagnosis for short and
open load
12
OUT2F
13
14
OUT2S
PGND2
Sense pin, used only for final testing
Power ground OUT2
Half-bridge output 1; formed by internally connected power MOS high-side switch 1 and low-side switch 1
with internal reverse diodes; short circuit protection; overtemperature protection; diagnosis for short and
open load
15
OUT1F
16
17
18
OUT1S
PGND1
PGND3
Sense pin, used only for final testing
Power ground OUT1
Power ground OUT3
3
4908D–AUTO–09/06
3. Functional Description
3.1
Serial Interface
Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized
to CLK and is accepted on the falling edge of the CLK signal. The LSB (bit 0, SRR) has to be
transferred first. Execution of new input data is enabled on the rising edge of the CS signal.
When CS is high, pin DO is in tri-state condition. This output is enabled on the falling edge of
CS. Output data will change their state with the rising edge of CLK and stay stable until the next
rising edge of CLK appears. LSB (bit 0, TP) is transferred first.
Figure 3-1. Data Transfer
CS
DI
CLK
DO
SRR
0
LS1
HS1
LS2
HS2
LS3
HS3
nPL!
PH1
PL2
PH2
10
PL3
11
PH3
12
OCS
14
SI
OLD
13
1
2
3
4
5
6
7
8
9
15
TP
S1L
S1H
S2L
S2H
S3L
S3H
n. u.
n. u.
n. u.
n. u.
n. u.
n. u.
OVl
INH
PSF
Table 3-1.
Bit
Input Data Protocol
Input Register
Function
Status register reset (high = reset; the bits PSF and OVL in the output
data register are set to low)
0
SRR
1
2
LS1
HS1
LS2
HS2
LS3
HS3
PL1
PH1
PL2
PH2
PL3
PH3
OLD
OCS
Controls output LS1 (high = switch output LS1 on)
Controls output HS1 (high = switch output HS1 on)
3
See LS1
4
See HS1
5
See LS1
6
See HS1
7
Output LS1 additionally controlled by PWM Input
8
Output HS1 additionally controlled by PWM Input
9
See PL1
10
11
12
13
14
See PH1
See PL1
See PH1
Open load detection (low = on)
Overcurrent shutdown (high = overcurrent shutdown is active)
Software inhibit; low = standby, high = normal operation
(data transfer is not affected by the standby function because the digital
part is still powered)
15
SI
4
ATA6831
4908D–AUTO–09/06
ATA6831
Table 3-2.
Output Data Protocol
Output (Status)
Bit
Register
Function
Temperature prewarning: high = warning
0
TP
Normal operation: high = output is on, low = output is off
Open-load detection: high = open load, low = no open load
(correct load condition is detected if the corresponding output is
switched off); not affected by SRR
1
2
Status LS1
Status HS1
Normal operation: high = output is on, low = output is off
Open-load detection: high = open load, low = no open load
(correct load condition is detected if the corresponding output is
switched off); not affected by SRR
3
4
Status LS2
Status HS2
Status LS3
Status HS3
n. u.
Description see LS1
Description see HS1
Description see LS1
Description see HS1
Not used
5
6
7
8
n. u.
Not used
9
n. u.
Not used
10
11
12
n. u.
Not used
n. u.
Not used
n. u.
Not used
Over-load detected: set high, when at least one output is switched off
by a short-circuit condition or an overtemperature event. Bits 1 to 6 can
be used to detect the affected switch
13
OVL
Inhibit: this bit is controlled by software (bit SI in input register)
High = standby, low = normal operation
14
15
INH
PSF
Power-supply fail: undervoltage at pin VS detected
5
4908D–AUTO–09/06
After power-on reset, the input register has the following status:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
Bit 8
PH1
Bit 7
PL1
Bit 6
HS3
Bit 5
LS3
Bit 4
HS2
Bit 3 Bit 2 Bit 1 Bit 0
SI
OCS
OLD
PH3
PL3
PH2
PL2
LS2
HS1
LS1
SRR
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
The following patterns are used to enable internal test modes of the IC. Do not use these pat-
terns during normal operation.
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
(OCS)
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2 Bit 1
Bit 0
(HS3) (LS3) (HS2) (LS2) (HS1) (LS1) (SRR)
H
H
H
H
H
H
H
H
H
H
L
L
H
L
L
L
H
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
3.2
Power-supply Fail
If undervoltage is detected at pin VS, the power-supply fail bit (PSF) in the output register is set
and all outputs are disabled. To detect an undervoltage, its duration has to last longer than the
undervoltage detection delay time tdUV. The outputs are enabled immediately when the supply
voltage returns to the normal operational value. The PSF bit stays high until it is reset by the
SRR bit in the input register.
3.3
Open-load Detection
If the open-load detection bit (OLD) is set to low, a pull-up current for each high-side switch and
a pull-down current for each low-side switch is turned on (open-load detection current IOUT1-3). If
the current through the external load does not reach the open-load detection current, the corre-
sponding bit of the output in the output register is set to high.
Switching on an output stage with the OLD bit set to low disables the open-load function for this
output.
6
ATA6831
4908D–AUTO–09/06
ATA6831
3.4
Overtemperature Protection
If the junction temperature of one or more output stages exceeds the thermal prewarning thresh-
old, TjPW set, the temperature prewarning bit (TP) in the output register is set. When the
temperature falls below the thermal prewarning threshold, TjPW reset, the bit TP is reset. The TP
bit can be read without transferring a complete 16-bit data word. The status of TP is available at
pin DO with the falling edge of CS. After the microcontroller has read this information, CS is set
high and the data transfer is interrupted without affecting the status of input and output registers.
If the junction temperature of an output stage exceeds the thermal shutdown threshold, Tjswitch off
,
the affected output is disabled and the corresponding bit in the output register is set to low. Addi-
tionally, the overload detection bit (OVL) in the output register is set. The output can be enabled
again when the temperature falls below the thermal shutdown threshold, Tjswitch on, and the SRR
bit in the input register is set to high. The hysteresis of thermal prewarning and shutdown thresh-
old avoids oscillations.
3.5
Short-circuit Protection
The output currents are limited by a current regulator. Overcurrent detection is activated by writ-
ing a high to the overcurrent shutdown bit (OCS) bit in the input register. When the current in an
output stage exceeds the overcurrent limitation and shut-down threshold, it is switched off, fol-
lowing a delay time (tdSd). The over-load detection bit (OVL) is set and the corresponding status
bit in the output register is set to low. For OCS = low, the overcurrent shutdown is inactive and
the OVL bit is not set by an overcurrent. By writing a high to the SRR bit in the input register the
OVL bit is reset and the disabled outputs are enabled.
3.6
3.7
Inhibit
The SI bit in the input register has to be set to zero to inhibit the ATA6831.
In this state, all output stages are then turned off but the serial interface remains active. The cur-
rent consumption is reduced to less than 5 µA at pin VS and less than 100 µA at pin VCC. The
output stages can be reactivated by setting bit SI to “1”.
PWM Mode
The common input for all six outputs is pin PWM (Figure 3-2). The selection of the outputs,
which are controlled by PWM, is done by input data register PLx or PHx. In addition to the PWM
input register, the corresponding input registers HSx and LSs have to be set.
Switching the high side outputs is possible up to 25 kHz, low side switches up to 8 kHz.
Figure 3-2. Output Control by PWM
Bit LSx/HSx
Pin OUTx
Bit PLx/PHx
Pin PWM
7
4908D–AUTO–09/06
4. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Pin
Symbol
Value
Unit
Supply voltage
10, 11
VVS
–0.3 to +40
V
Supply voltage
t < 0.5s; IS > –2A
10, 11
9
VVS
–1
V
V
Logic supply voltage
Logic input voltage
Logic output voltage
Input current
VVCC
–0.3 to +7
VCS, VDI, VCLK
VPWM
,
3, 4, 5, 6
7
–0.3 to VVCC + 0.3
–0.3 to VVCC + 0.3
–10 to +10
V
VDO
V
ICS, IDI, ICLK
IPWM
,
3, 4, 5, 6
7
mA
mA
Output current
IDO
–10 to +10
Internally limited, see output
specification
Output current
2, 12, 15
2, 12, 15
2, 12, 15
IOut1, IOut2, IOut3
IOut1, IOut2, IOut3
IOut1, IOut2, IOut3
Output voltage
–0.3 to +40
V
A
Reverse conducting current
(tpulse = 150 µs)
17
Junction temperature range
Storage temperature range
TJ
–40 to +150
–55 to +150
°C
°C
TSTG
5. Thermal Resistance
Parameters
Test Conditions
Symbol
Value
Unit
Thermal resistance from junction to
case
RthJC
15
k/W
Thermal resistance from junction to
ambient
Depends on the PC board
RthJA
40
K/W
6. Operating Range
Parameters
Symbol
VVS
Value
VUV(1) to 40
Unit
Supply voltage
V
V
Logic supply voltage
Logic input voltage
VVCC
4.75 to 5.25
VCS, VDI, VCLK, VPWM
–0.3 to VVCC
2
V
Serial interface clock frequency
PWM input frequency
Junction temperature range
fCLK
fPWM
Tj
MHz
kHz
°C
max. 25
–40 to +150
Note:
1. Threshold for undervoltage description
8
ATA6831
4908D–AUTO–09/06
ATA6831
7. Noise and Surge Immunity
Parameters
Test Conditions
ISO 7637-1
Value
Level 4(1)
Level 5
2 kV
Conducted interferences
Interference suppression
ESD (Human Body Model)
CDM (Charge Device Model)
VDE 0879 Part 2
ESD S 5.1
ESD STM5.3.1
500V
Note:
1. Test pulse 5: Vsmax = 40V
8. Electrical Characteristics
7.5V < VS < 40V; 4.75V < VCC < 5.25V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins.
No. Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
Type*
Pin
1
Current Consumption
1.1
Quiescent current VS
VVS < 20V, SI = low
10, 11
9
IVS
1
5
µA
µA
A
A
4.75V < VVCC < 5.25V,
SI = low
1.2
1.3
1.4
Quiescent current VCC
IVCC
60
100
VVS < 20V normal
operating, all outputs
off, input register bit 13
(OLD) = high
Supply current VS
Supply current VCC
10, 11
9
IVS
4
6
mA
µA
A
A
4.75V < VVCC < 5.25V,
normal operating
IVCC
350
650
1.5
1.6
2
Discharge current VS
Discharge current VS
VVS = 32.5V, INH = low 10, 11
IVS
IVS
0.5
2.5
5.5
10
mA
mA
A
A
VVS = 40V, INH = low
10, 11
9
Undervoltage Detection, Power-on Reset
Power-on reset
threshold
2.1
2.2
2.3
2.4
2.5
VVCC
tdPor
VUv
3.2
30
3.9
95
4.4
190
7.0
V
A
A
A
A
A
Power-on reset delay
After switching on VCC
time
µs
V
Undervoltage-detection
threshold
V
CC = 5V
10, 11
10, 11
5.6
Undervoltage-detection
hysteresis
VCC = 5V
∆VUv
tdUV
0.6
V
Undervoltage-detection
delay time
10
40
µs
3
Thermal Prewarning and Shutdown
3.1
Thermal prewarning set
TjPW set
120
105
145
130
170
155
°C
°C
B
B
Thermal prewarning
reset
3.2
3.3
TjPW reset
Thermal prewarning
hysteresis
∆TjPW
15
K
B
3.4
3.5
Thermal shutdown off
Thermal shutdown on
Tj switch off
Tj switch on
150
135
175
160
200
185
°C
°C
B
B
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes: 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of
final level. Device not in standby for t > 1 ms.
2. Delay time between rising/falling edge of input signal at pin PWM and switch on/off output stages to 90% of final level.
3. Difference between switch-on and switch-off delay time of input signal at pin PWM to output stages in PWM mode.
9
4908D–AUTO–09/06
8. Electrical Characteristics (Continued)
7.5V < VS < 40V; 4.75V < VCC < 5.25V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins.
No. Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
Type*
Pin
Thermal shutdown
hysteresis
3.6
∆Tj switch off
15
K
B
Ratio thermal shutdown
off/thermal prewarning
set
Tj switch off/
TjPW set
3.7
1.05
1.05
1.2
1.2
B
B
Ratio thermal shutdown
on/thermal prewarning
reset
Tj switch on/
TjPW reset
3.8
4
Output Specification (OUT1 to OUT3)
2, 12,
15
4.1
IOut 1-3 = –0.9 A
On resistance
RDSon1-3H
RDSon1-3L
IOut1-3H
1.5
1.5
Ω
A
A
A
A
2, 12,
15
4.2
4.3
4.4
IOut 1-3 = –0.9 A
Ω
High-side output
leakage current
VOut 1-3 H = 0V
2, 12,
15
,
–15
µA
µA
output stages off
Out 1-3 L = VVS,
output stages off
Low-side output
leakage current
V
2, 12,
15
IOut1-3L
300
2
High-side switch
reverse diode forward IOut = 1.5A
voltage
2, 12,
15
4.5
4.6
4.7
VOut1-3 – VVS
V
V
A
A
A
A
Low-side switch reverse
diode forward voltage
2, 12,
15
IOut 1-3 L = –1.5A
VOut1-3L
2
High-side overcurrent
limitation and shutdown 7.5V < VVS < 20V
threshold
2, 12,
15
IOut1-3
1.0
1.3
–1.3
1.3
1.7
–1.0
2.0
Low-side overcurrent
limitation and shutdown 7.5V < VVS < 20V
threshold
2, 12,
15
4.8
4.9
IOut1-3
IOut1-3
IOut1-3
–1.7
1.0
A
A
A
A
A
A
High-side overcurrent
limitation and shutdown 20V < VVS < 40V
threshold
2, 12,
15
Low-side overcurrent
2, 12,
15
4.10 limitation and shutdown 20V < VVS < 40V
threshold
–2.0
–1.3
–1.0
Overcurrent shutdown
delay time
4.11
tdSd
10
40
–0.2
2.5
3
µs
mA
mA
A
A
A
High-side open load
detection current
Input register bit 13
(OLD) = low, output off
2, 12,
15
4.12
4.13
4.14
IOut1-3H
IOut1-3L
–2.5
0.2
Low-side open load
detection current
Input register bit 13
(OLD) = low, output off
2, 12,
15
Open load detection
current ratio
IOLoutLX
IOLoutHX
/
1.2
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes: 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of
final level. Device not in standby for t > 1 ms.
2. Delay time between rising/falling edge of input signal at pin PWM and switch on/off output stages to 90% of final level.
3. Difference between switch-on and switch-off delay time of input signal at pin PWM to output stages in PWM mode.
10
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ATA6831
8. Electrical Characteristics (Continued)
7.5V < VS < 40V; 4.75V < VCC < 5.25V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins.
No. Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
Type*
Pin
High-side output switch VVS = 13V
4.15
4.16
4.17
4.18
tdon
20
µs
A
on delay(1),(2)
RLoad = 30Ω
Low-side output switch VVS = 13V
on delay(1),(2)
Load = 30Ω
High-side output switch VVS =13V
off delay(1),(2)
RLoad = 30Ω
tdon
tdoff
tdoff
20
20
3
µs
µs
µs
A
A
A
R
Low-side output switch VVS =13V
off delay(1),(2)
RLoad = 30Ω
Dead time between
corresponding
high-side and low-side RLoad = 30Ω
V
VS =13V
4.19
4.20
t
don – tdoff
1
3
µs
A
switches
∆tdPWM
VVS = 13V
RLoad = 30Ω
∆tdPWM
tdon – tdoff
=
20
7
µs
µs
A
A
low-side switch(3)
∆tdPWM
high-side switch(3)
VVS = 13V
RLoad = 30Ω
∆tdPWM =
tdon – tdoff
4.21
5
Logic Inputs DI, CLK, CS, PWM
Input voltage low-level
threshold
3, 4, 5,
6
0.3 ×
VVCC
5.1
VIL
VIH
∆VI
IPD
IPU
V
V
A
A
A
A
A
Input voltage high-level
threshold
3, 4, 5,
6
0.7 ×
VVCC
5.2
5.3
5.4
5.5
Hysteresis of input
voltage
3, 4, 5,
6
50
10
700
65
mV
µA
µA
Pull-down current
pins DI, CLK, PWM
VDI, VCLK, VPWM = VCC
VCS = 0V
4, 5, 6
3
Pull-up current
pin CS
–65
–10
6
Serial Interface – Logic Output DO
Output-voltage low level IDOL = 2 mA
Output-voltage high
6.1
7
7
VDOL
VDOH
0.4
10
V
V
A
A
VVCC
0.7V
–
6.2
IDOL = –2 mA
level
Leakage current
(tri-state)
VCS = VCC
0V < VDO < VVCC
6.3
7
IDO
–10
µA
A
7
Inhibit Input – Timing
Delay time from
standby to normal
operation
7.1
tdINH
100
µs
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes: 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of
final level. Device not in standby for t > 1 ms.
2. Delay time between rising/falling edge of input signal at pin PWM and switch on/off output stages to 90% of final level.
3. Difference between switch-on and switch-off delay time of input signal at pin PWM to output stages in PWM mode.
11
4908D–AUTO–09/06
9. Serial Interface Timing
No. Parameters
Test Conditions
Pin
Timing Chart No.(1)
Symbol
Min.
Typ.
Max.
Unit
Type*
8
Serial Interface Timing
DO enable after CS
falling edge
8.1
CDO = 100 pF
CDO = 100 pF
7
7
1
2
tENDO
tDISDO
200
200
ns
ns
D
D
DO disable after CS
rising edge
8.2
8.3 DO fall time
8.4 DO rise time
8.5 DO valid time
8.6 CS setup time
8.7 CS setup time
8.8 CS high time
8.9 CLK high time
8.10 CLK low time
8.11 CLK period time
8.12 CLK setup time
8.13 CLK setup time
8.14 DI setup time
8.15 DI hold time
CDO = 100 pF
CDO = 100 pF
CDO = 100 pF
7
7
7
3
3
3
5
5
5
5
5
4
4
-
-
tDOf
tDOr
100
100
200
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
D
D
D
D
D
D
D
D
D
D
D
D
D
10
4
tDOVal
tCSSethl
tCSSetlh
tCSh
225
225
500
225
225
500
225
225
40
8
9
5
tCLKh
6
tCLKl
-
tCLKp
7
tCLKSethl
tCLKSetlh
tDIset
3
11
12
tDIHold
40
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
12
ATA6831
4908D–AUTO–09/06
ATA6831
Figure 9-1. Serial Interface Timing with Chart Number
1
2
CS
DO
9
CS
4
7
CLK
5
3
6
8
DI
11
CLK
10
12
DO
Inputs DI, CLK, CS: High level = 0.7 × VCC, low level = 0.3 × VCC
Output DO: High level = 0.8 × VCC, low level = 0.2 × VCC
13
4908D–AUTO–09/06
10. Application Circuit
Figure 10-1. Application Circuit
V
CC
U5021M
Watchdog
V
S
O
S
C
O
L
D
P
H
3
P
L
3
P
H
2
P
L
2
P
H
1
P
L
1
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
S
R
R
S
I
BYV28
10
11
V
VS1
VS2
Batt
13V
Input register
Ouput register
Serial interface
+
Charge
pump
P
S
F
I
N
H
O
V
L
n. n. n. n. n. n.
u. u. u. u. u. u.
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
T
P
DI
4
CLK
5
CS
Micro-
3
controller
V
CC
UV
protection
Fault
detector
Fault
detector
Fault
detector
V
CC
9
8
DO
7
VCC
GND
5V
Control
logic
Power on
reset
+
PWM
6
14
17
18
Fault
detector
Fault
detector
Fault
detector
GND
GND
Thermal
protection
V
CC
GND
2
12
15
OUT3
OUT2
OUT1
M
M
10.1 Application Notes
• Connect the blocking capacitors at VCC and VS as close as possible to the power supply and
GND pins.
• Recommended value for capacitors at VS:
– Electrolytic capacitor C > 22 µF in parallel with a ceramic capacitor C = 100 nF. The
value for the electrolytic capacitor depends on external loads, conducted
interferences, and the reverse conducting current IOut1,2,3
.
• Recommended value for capacitors at VCC
:
– Electrolytic capacitor C > 10 µF in parallel with a ceramic capacitor C = 100 nF.
• To reduce thermal resistance, place cooling areas on the PCB as close as possible to the
GND pins and to the die pad.
14
ATA6831
4908D–AUTO–09/06
ATA6831
11. Ordering Information
Extended Type Number
Package
Remarks
ATA6831-PIQW
QFN18, 4 mm × 4 mm
QFN18, 4 mm × 4 mm
QFN18, 4 mm × 4 mm
Taped and reeled, Pb-free
Taped and reeled, Pb-free
Tubes, Pb-free
ATA6831-PIPW
ATA6831-PISW
12. Package Information
Package: VQFN_4 x 4_18L
Exposed pad 2.5 x 3.125
Dimensions in mm
Bottom
2.5
Not indicated tolerances ±0.05
Z
12
7
0.5 nom.
18
Top
18
13
1
1
Pin 1 identification
6
6
4
0.2
2.6±0.15
0.9±0.1
Z 10:1
technical drawings
according to DIN
specifications
Drawing-No.: 6.543-5133.01-4
0.23±0.07
Issue: preliminary copy; 06.10.06
15
4908D–AUTO–09/06
13. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
Revision No.
History
• Features on page 1 changed
• Figure 1-1 “Block Diagram” on page 2 changed
• Section 2 “Pin Configuration” on pages 2 to 3 changed
• Section 4 “Absolute Maximum Ratings” on page 8 changed
• Section 8 “Electrical Characteristics” on pages 9 to 11 changed
• Section 9 “Serial Interface Timing” on page 12 changed
• Figure 10-1 “Application Circuit” on page 14 changed
• Section 11 “Ordering Information” on page 15 changed
• Section 12 “Package Information” on page 15 changed
4908D-AUTO-09/06
• Title on page 1 changed
• Features on page 1 changed
• Figure 1-1 “Block Diagram” on page 1 changed
• Figure 2-1 “Pinning” on page 3 changed
• Table 2-1 “Pin Description” on page 3 changed
• Table 3-2 “Output Data Protocol” on page 5 changed
• Section 3.7 “PWM Mode” on page 7 added
4908C-AUTO-08/06
• Section 4 “Absolute Maximum Ratings” on page 8 changed
• Section 8 “Electrical Characteristics” on pages 9 to 12 changed
• Figure 10-1 “Application Circuit” on page 14 changed
• Section 10.1 “Application Notes” on page 14 changed
• Section 11 “Ordering Information” on page 15 changed
• Section 12 “Package Information” on page 15 changed
16
ATA6831
4908D–AUTO–09/06
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