ATA6827-PIQW [ATMEL]
High Temperature Triple Half-bridge Driver with Serial Input Control; 带串行输入控制高温三重半桥驱动器
| 型号： | ATA6827-PIQW |
| 厂家： | 
ATMEL |
| 描述： | High Temperature Triple Half-bridge Driver with Serial Input Control |
| 文件： | 总15页 (文件大小：338K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Supply Voltage up to 40V
• RDSon Typically 0.8Ω at 25°C, Maximum 1.8Ω at 200°C
• Up to 1.0A Output Current
• Three Half-bridge Outputs Formed by Three High-side and Three Low-side Drivers
• Capable to Switch all Kinds of Loads Such as DC Motors, Bulbs, Resistors, Capacitors
and Inductors
• No Shoot-through Current
• Outputs Short-circuit Protected
High
• Overtemperature Protection for Each Switch and Overtemperature Prewarning
• Undervoltage Protection
Temperature
Triple
Half-bridge
Driver with
Serial Input
Control
• Various Diagnostic Functions Such as Shorted Output, Open-load, Overtemperature
and Power-supply Fail Detection
• Serial Data Interface, Daisy Chain Capable, up to 2 MHz Clock Frequency
• QFN18 Package
1. Description
The ATA6827 is a fully protected driver IC specially designed for high temperature
applications. In mechatronic solutions, for example turbo charger or exhaust gas recir-
culation systems, many flaps have to be controlled by DC motor driver ICs which are
located very close to the hot engine or actuator where ambient temperatures up to
150°C are usual. Due to the advantages of SOI technology junction temperatures up
to 200°C are allowed. This enables new cost effective board design possibilities to
achieve complex mechatronic solutions.
ATA6827
The ATA6827 is a fully protected Triple Half-Bridge to control up to 3 different loads by
a microcontroller in automotive and industrial applications. Each of the 3 high-side and
3 low-side drivers is capable to drive currents up to 1.0A. The drivers are internally
connected to form 3 half-bridges and can be controlled separately from a standard
serial data interface. Therefore, all kinds of loads such as bulbs, resistors, capacitors
and inductors can be combined. The IC design especially supports the application of
H-bridges to drive DC motors.
Preliminary
Protection is guaranteed regarding short-circuit conditions, overtemperature and und-
ervoltage. Various diagnostic functions and a very low quiescent current in standby
mode opens a wide range of applications. Automotive qualification gives added value
and enhanced quality for exacting requirements of automotive applications.
4912D–AUTO–06/07
Figure 1-1. Block Diagram
O
S
C
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
S
R
R
n. n.
u. u.
n. n. n. n. n. n.
u. u. u. u. u. u.
10
11
VS
VS
Input register
Ouput register
Serial interface
Charge
pump
P
S
F
O
P
L
S
C
D
n. n. n. n. n. n.
u. u. u. u. u. u.
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
T
P
DI
4
5
CLK
CS
INH
DO
3
8
UV
protection
Fault
detector
Fault
detector
Fault
detector
9
VCC
Control
logic
Power on
reset
7
14
17
18
6
GND
GND
GND
GND
Fault
detector
Fault
detector
Fault
detector
Thermal
protection
1
13
12
16
15
2
OUT1S
OUT1F
OUT3S
OUT3F
OUT2S
OUT2F
2
ATA6827
4912D–AUTO–06/07
ATA6827
2. Pin Configuration
Figure 2-1. Pinning QFN18
18 17 16 15 14 13
OUT3S
OUT3F
CS
1
2
3
4
5
6
12 OUT2F
11 VS
10 VS
DI
9
8
7
VCC
INH
DO
CLK
GND
Table 2-1.
Pin Description
Pin
1
Symbol
OUT3S
OUT3F
Function
Used only for final testing, to be connected to OUT3F
Half-bridge output 3
2
Chip select input; 5-V CMOS logic level input with internal pull up;
low = serial communication is enabled, high = disabled
3
4
CS
DI
Serial data input; 5-V CMOS logic level input with internal pull down; receives serial data from the control
device; DI expects a 16-bit control word with LSB being transferred first
Serial clock input; 5-V CMOS logic level input with internal pull down;
controls serial data input interface and internal shift register (fmax = 2 MHz)
5
6
CLK
GND
Ground; reference potential
Serial data output; 5-V CMOS logic level tri-state output for output (status) register data; sends 16-bit
status information to the microcontroller (LSB is transferred first); output will remain tri-stated unless
device is selected by CS = low, therefore, several ICs can operate on one data output line only.
7
DO
8
INH
VCC
Inhibit input; 5-V logic input with internal pull down; low = standby, high = normal operation
Logic supply voltage (5 V)
9
10
11
12
13
14
15
16
VS
Power supply for output stages OUT1, OUT2 and OUT3, internal supply
Power supply for output stages OUT1, OUT2 and OUT3, internal supply
Half-bridge output 2
VS
OUT2F
OUT2S
PGND2
OUT1F
OUT1S
Used only for final testing, to be connected to OUT2F
Power Ground OUT2
Half-bridge output 1
Used only for final testing, to be connected to OUT13F
PGND1
PGND3
17
18
Power Ground OUT1 and OUT3
Power Ground OUT1 and OUT3
PGND1
PGND3
3
4912D–AUTO–06/07
3. Functional Description
3.1
Serial Interface
Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized
to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be trans-
ferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS
is high, pin DO is in tri-state condition. This output is enabled on the falling edge of CS. Output
data will change their state with the rising edge of CLK and stay stable until the next rising edge
of CLK appears. LSB (bit 0, TP) is transferred first.
Figure 3-1. Data Transfer
CS
DI
CLK
DO
SRR
0
LS1
HS1
LS2
HS2
LS3
HS3
n. u.
n. u.
n. u.
n. u.
10
n. u.
11
n. u.
12
n. u.
14
n. u.
15
OCS
13
1
2
3
4
5
6
7
8
9
TP
S1L
S1H
S2L
S2H
S3L
S3H
n. u.
n. u.
n. u.
n. u.
n. u.
n. u.
SCD
OPL
PSF
Table 3-1.
Bit
Input Data Protocol
Input Register
Function
Status register reset (high = reset; the bits PSF, OPL and SCD in the
output data register are set to low)
0
SRR
1
2
LS1
HS1
LS2
HS2
LS3
HS3
n. u.
n. u.
n. u.
n. u.
n. u.
n. u.
OCS
n. u.
n. u.
Controls output LS1 (high = switch output LS1 on)
Controls output HS1 (high = switch output HS1 on)
3
See LS1
4
See HS1
5
See LS1
6
See HS1
7
Not used
8
Not used
9
Not used
10
11
12
13
14
15
Not used
Not used
Not used
Overcurrent shutdown (high = overcurrent shutdown is active)
Not used
Not used
4
ATA6827
4912D–AUTO–06/07
ATA6827
Table 3-2.
Output Data Protocol
Output (Status)
Bit
0
Register
Function
Temperature prewarning: high = warning
TP
1
Status LS1
Status HS1
Status LS2
Status HS2
Status LS3
Status HS3
n. u.
High = output is on, low = output is off; not affected by SRR
2
High = output is on, low = output is off; not affected by SRR
3
Description see LS1
Description see HS1
Description see LS1
Description see HS1
Not used
4
5
6
7
8
n. u.
Not used
9
n. u.
Not used
10
11
12
n. u.
Not used
n. u.
Not used
n. u.
Not used
Short circuit detected: set high when at least one high-side or low-side
switch is switched off by a short-circuit condition. Bits 1 to 6 can be used
to detect the shorted switch.
13
SCD
Open load detected: set high, when at least one active high-side or
low-side switch sinks/sources a current below the open load threshold
current.
14
15
OPL
PSF
Power-supply fail: undervoltage at pin VS detected
After power-on reset, the input register has the following status:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
(OCS)
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2 Bit 1
Bit 0
(HS3) (LS3) (HS2) (LS2) (HS1) (LS1) (SRR)
x
x
H
x
x
x
x
x
x
L
L
L
L
L
L
L
The following patterns are used to enable internal test modes of the IC. It is not recommended to use these patterns during
normal operation.
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
(OCS)
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2 Bit 1
Bit 0
(HS3) (LS3) (HS2) (LS2) (HS1) (LS1) (SRR)
H
H
H
H
H
H
H
H
H
H
L
L
H
L
L
L
H
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
5
4912D–AUTO–06/07
3.2
Power-supply Fail
In case of undervoltage at pin VS, the Power-Supply Fail bit (PSF) in the output register is set
and all outputs are disabled. To detect an undervoltage, its duration has to be longer than the
undervoltage detection delay time tdUV. The outputs are enabled immediately when supply volt-
age recovers to a normal operating value. The PSF bit stays high until it is reset by the SRR
(Status Register Reset) bit in the input register.
3.3
3.4
Open-load Detection
If the current through a high-side or low-side switch in the ON-state stays below the open-load
detection threshold, the open-load detection bit (OPL) in the output register is set.
The OPL bit stays high until it is reset by the SRR bit in the input register. To detect an open
load, its duration has to be longer than the open-load detection delay time tdSd
.
Overtemperature Protection
If the junction temperature of one or more output stages exceeds the thermal prewarning thresh-
old, TjPW set, the temperature prewarning bit (TP) in the output register is set. When the
temperature falls below the thermal prewarning threshold, TjPW reset, the bit TP is reset. The TP
bit can be read without transferring a complete 16-bit data word. The status of TP is available at
pin DO with the falling edge of CS. After the microcontroller has read this information, CS is set
high and the data transfer is interrupted without affecting the status of input and output registers.
If the junction temperature of one or more output stages exceeds the thermal shutdown thresh-
old, Tj switch off, all outputs are disabled and the corresponding bits in the output register are set to
low. The outputs can be enabled again when the temperature falls below the thermal shutdown
threshold, Tjswitch on and the SRR bit in the input register is set to high. Hysteresis of thermal pre-
warning and shutdown threshold avoids oscillations.
3.5
Short-circuit Protection
The output currents are limited by a current regulator. Overcurrent detection is activated by writ-
ing a high to the OCS (Overcurrent Shutdown) bit in the input register. When the current in an
output stage exceeds the overcurrent limitation and shutdown threshold, it is switched off after a
delay time (tdSd). The short-circuit detection bit (SCD) is set and the corresponding status bit in
the output register is set to low. For OCS = low the overcurrent shutdown is inactive. The SCD
bit is also set if the current exceeds the overcurrent limitation and shutdown threshold, but the
outputs are not affected. By writing a high to the SRR bit in the input register the SCD bit is reset
and the disabled outputs are enabled.
3.6
Inhibit
Applying 0V to pin 8 (INH) inhibits the ATA6827.
All output switches are then turned off and switched to tri-state. The data in the output register is
deleted. The output switches can be activated again by switching pin 8 (INH) to 5V which ini-
tiates an internal power-on reset.
6
ATA6827
4912D–AUTO–06/07
ATA6827
4. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
All values refer to GND pins.
Parameters
Pin
Symbol
Value
Unit
Supply voltage
10, 11
VVS
–0.3 to +40
V
Supply voltage
t < 0.5s; IS > –2A
10, 11
VVS
–1
V
Logic supply voltage
Logic input voltage
Logic output voltage
Input current
9
VVCC
VCS,VDI, VCLK, VINH
VDO
–0.3 to +7
–0.3 to VVCC + 0.3
–0.3 to VVCC + 0.3
–10 to +10
V
V
3, 4, 5, 8
7
V
3, 4, 5, 8
7
ICS, IDI, ICLK, IINH
IDO
IOut3, IOut2, IOut1
IOut3, IOut2, IOut1
mA
mA
Output current
–10 to +10
Output current
2, 12, 15
2, 12, 15
Internally limited, see output specification
–0.3 to +40
Output voltage
V
A
Reverse conducting current
(tpulse = 150 µs)
2, 12, 15
IOut3, IOut2, IOut1
17
Junction temperature range
Storage temperature range
Ambient temperature range
Tj
TSTG
Ta
–40 to +200
–55 to +200
–40 to +150
°C
°C
°C
5. Thermal Resistance
Parameters
Test Conditions
Symbol
Rthjc
Value
maximum 15
40
Unit
K/W
K/W
Junction case
Junction ambient
(1)
RthJA
Notes: 1. Depends on PCB board design
6. Operating Range
Parameters
Symbol
Value
Unit
V
Supply voltage
VVS
VUV(2) to 40
4.75 to 5.25
–0.3 to VVCC
2
Logic supply voltage
Logic input voltage
VVCC
V
VCS,VDI, VCLK, VINH
V
Serial interface clock frequency
Junction temperature range
fCLK
Tj
MHz
°C
–40 to +200
Note:
Threshold for undervoltage detection
7
4912D–AUTO–06/07
7. Noise and Surge Immunity
Parameters
Test Conditions
ISO 7637-1
Value
Level 4(1)
Level 5
2 kV
Conducted interferences
Interference suppression
ESD (Human Body Model)
CDM (Charged Device Model)
VDE 0879 Part 2
ESD S 5.1
ESD STM 5.3.1-1999 all pins
500V
Note:
Test pulse 5: Vsmax = 40V
8. Electrical Characteristics
7.5V < VVS < 40V; 4.75V < VVCC < 5.25 V; INH = High; –40°C ≤ Tj ≤ 200°C; Ta ≤ 150°C; unless otherwise specified, all values refer to
GND pins.
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
1
Current Consumption
1.1
Quiescent current VS
VVS < 20V, INH = low
10, 11
9
IVS
1
60
40
µA
µA
A
A
4.75 V < VVCC < 5.25V,
INH = low
1.2
1.3
1.4
1.5
Quiescent current VCC
IVCC
15
VVS < 20V normal
operating, all outputs off
Supply current VS
10, 11
9
IVS
IVCC
IVS
4
6
mA
µA
A
A
A
A
4.75V < VVCC < 5.25V,
normal operating
Supply current VCC
Discharge current VS
Discharge current VS
350
500
5.5
10
VVS = 32.5V,
INH = low
10, 11
10, 11
0.5
2.0
mA
mA
VVS = 40V,
INH = low
1.6
2
IVS
Undervoltage Detection, Power-on Reset
Power-on reset
threshold
2.1
9
VVCC
tdPor
VUv
3.1
30
3.9
95
4.5
190
7.1
V
µs
V
A
A
A
A
A
Power-on reset
After switching on VCC
delay time
2.2
2.3
2.4
2.5
Undervoltage-detection
VCC = 5V
10, 11
10, 11
5.5
threshold
Undervoltage-detection
VCC = 5V
∆VUv
tdUV
0.6
V
hysteresis
Undervoltage-detection
delay time
10
40
µs
3
Thermal Prewarning and Shutdown
3.1
Thermal prewarning set
TjPW set
170
155
195
180
220
205
°C
°C
B
B
Thermal prewarning
reset
3.2
3.3
TjPW reset
Thermal prewarning
hysteresis
∆TjPW
15
°C
B
3.4
3.5
Thermal shutdown off
Thermal shutdown on
Tj switch off
Tj switch on
200
185
225
210
250
235
°C
°C
B
B
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Delay time between rising edge of the input signal at pin CS after data transmission and switch on output stages to 90% of
final level. Device not in standby for t > 1 ms
8
ATA6827
4912D–AUTO–06/07
ATA6827
8. Electrical Characteristics (Continued)
7.5V < VVS < 40V; 4.75V < VVCC < 5.25 V; INH = High; –40°C ≤ Tj ≤ 200°C; Ta ≤ 150°C; unless otherwise specified, all values refer to
GND pins.
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Thermal shutdown
hysteresis
3.6
∆Tj switch off
15
°C
B
Ratio thermal shutdown
off/thermal prewarning
set
Tj switch off/
TjPW set
3.7
1.05
1.05
1.15
1.15
B
B
Ratio thermal shutdown
on/thermal prewarning
reset
Tj switch on/
TjPW reset
3.8
4
Output Specification (OUT1-OUT3)
2, 12,
15
4.1
IOut 1-3 = –0.9A
On resistance
RDSOn1-3
RDSOn1-3
IOut1-3
1.8
1.8
Ω
Ω
A
A
A
2, 12,
15
4.2
4.3
4.4
IOut 1-3 = +0.9A
VOut 1-3 = 0V
High-side output
leakage current
2, 12,
15
,
–60
µA
output stages off
VOut 1-3 = VVS,
Low-side output
leakage current
2, 12,
15
IOut1-3
VOut1-3 – VVS
VOut 1-3
300
2
µA
V
A
A
A
A
output stages off
High-side switch
reverse diode forward IOut 1-3 = 1.5A
voltage
2, 12,
15
4.5
4.6
4.7
Low-side switch reverse
IOut 1-3 = –1.5A
2, 12,
15
–2
V
diode forward voltage
High-side overcurrent
limitation and shutdown 7.5V < VS < 20V
threshold
2, 12,
15
IOut1-3
1.0
1.3
–1.3
1.3
1.7
–1.0
2.0
AA
Low-side overcurrent
limitation and shutdown 7.5V < VS < 20V
threshold
2, 12,
15
4.8
IOut1-3
IOut1-3
IOut1-3
–1.7
1.0
A
AA
A
A
A
A
High-side overcurrent
2, 12,
15
4.18 limitation and shutdown 20V < VS < 40V
threshold
Low-side overcurrent
4.19 limitation and shutdown 20V < VS < 40V
threshold
2, 12,
15
–2.0
–1.3
–1.0
Overcurrent shutdown
delay time
2, 12,
15
4.9
tdSd
IOut1-3
IOut1-3
tdSd
10
–55
5
40
–5
µs
mA
mA
µs
A
A
A
A
High-side open-load
4.10
2, 12,
15
–30
30
detection threshold
Low-side open-load
4.11
2, 12,
15
55
detection threshold
Open-load detection
delay time
4.12
200
600
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Delay time between rising edge of the input signal at pin CS after data transmission and switch on output stages to 90% of
final level. Device not in standby for t > 1 ms
9
4912D–AUTO–06/07
8. Electrical Characteristics (Continued)
7.5V < VVS < 40V; 4.75V < VVCC < 5.25 V; INH = High; –40°C ≤ Tj ≤ 200°C; Ta ≤ 150°C; unless otherwise specified, all values refer to
GND pins.
No. Parameters
High-side output switch VVS = 13V
on delay(1)
Load = 30Ω
Low-side output switch VVS = 13V
on delay(1)
RLoad = 30Ω
High-side output switch VVS = 13V
off delay(1)
RLoad = 30Ω
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
4.13
4.14
4.15
4.16
tdon
20
µs
A
R
tdon
tdoff
tdoff
20
20
3
µs
µs
µs
A
A
A
Low-side output switch VVS = 13V
off delay(1)
RLoad = 30Ω
Dead time between
4.17 corresponding high-
and low-side switches
VVS = 13V
Load = 30Ω
tdon – tdoff
1
µs
A
R
5
Logic Inputs DI, CLK, CS, INH
Input voltage low-level
threshold
3, 4, 5,
8
0.3 ×
VVCC
5.1
VIL
VIH
∆VI
IPD
IPU
V
V
A
A
B
A
A
Input voltage high-level
threshold
3, 4, 5,
8
0.7 ×
VVCC
5.2
5.3
5.4
5.5
Hysteresis of input
voltage
3, 4, 5,
8
50
5
700
70
mV
µA
µA
Pull-down current pin
DI, CLK, INH
VDI, VCLK, VINH = VCC
VCS = 0V
4, 5, 8
3
Pull-up current
Pin CS
–70
–5
6
Serial Interface – Logic Output DO
6.1
Output-voltage low level IDOL = 2 mA
7
7
VDOL
VDOH
0.4
+15
100
V
V
A
A
Output-voltage high
IDOL = –2 mA
level
VVCC
–0.7V
6.2
Leakage current
(tri-state)
VCS = VCC
0V < VDO < VVCC
6.3
7
IDO
–15
µA
A
7
Inhibit Input - Timing
Delay time from
standby to normal
operation
7.1
tdINH
µs
A
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Delay time between rising edge of the input signal at pin CS after data transmission and switch on output stages to 90% of
final level. Device not in standby for t > 1 ms
10
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4912D–AUTO–06/07
ATA6827
9. Serial Interface – Timing
No. Parameters
Test Conditions
Pin
Timing Chart No.(1)
Symbol
Min.
Typ.
Max.
Unit
Type*
DO enable after CS
falling edge
8.1
8.2
CDO = 100 pF
7
1
tENDO
200
ns
D
DO disable after CS
rising edge
CDO = 100 pF
7
2
tDISDO
200
ns
D
8.3 DO fall time
8.4 DO rise time
8.5 DO valid time
8.6 CS setup time
8.7 CS setup time
8.8 CS high time
8.9 CLK high time
8.10 CLK low time
8.11 CLK period time
8.12 CLK setup time
8.13 CLK setup time
8.14 DI setup time
8.15 DI hold time
CDO = 100 pF
CDO = 100 pF
CDO = 100 pF
7
7
7
3
3
3
5
5
5
5
5
4
4
-
-
tDOf
tDOr
100
100
200
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
D
D
D
D
D
D
D
D
D
D
D
D
D
10
4
tDOVal
tCSSethl
tCSSetlh
tCSh
225
225
500
225
225
500
225
225
40
8
9
5
tCLKh
6
tCLKl
-
tCLKp
7
tCLKSethl
tCLKSetlh
tDIset
3
11
12
tDIHold
40
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note: 1. Serial Interface Timing with Chart Numbers
11
4912D–AUTO–06/07
Figure 9-1. Serial Interface Timing with Chart Numbers
1
2
CS
DO
9
CS
4
7
CLK
5
3
6
8
DI
11
CLK
10
12
DO
Inputs DI, CLK, CS: High level = 0.7 × VCC, low level = 0.3 × VCC
Output DO: High level = 0.8 × VCC, low level = 0.2 × VCC
12
ATA6827
4912D–AUTO–06/07
ATA6827
10. Application Circuit
Figure 10-1. Application Circuit
V
CC
V
S
Enable
U5021M
Watchdog
O
S
C
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
S
R
R
n. n.
u. u.
n. n. n. n. n. n.
u. u. u. u. u. u.
BYT41D
VS
10
11
V
Batt
13V
Input register
Ouput register
Serial interface
VS
+
Charge
pump
P
S
F
O
P
L
S
C
D
n. n. n. n. n. n.
u. u. u. u. u. u.
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
T
P
DI
4
5
CLK
CS
INH
DO
3
8
7
V
CC
UV
protection
Micro-
controller
Fault
detector
Fault
detector
Fault
detector
V
CC
9
Control
logic
VCC
GND
5V
Power on
reset
+
14
17
18
Fault
detector
Fault
detector
Fault
detector
GND
GND
Thermal
protection
6
V
CC
GND
1
2
12
15
13
16
OUT3F
OUT2F
OUT1F
M
M
11. Application Notes
It is strongly recommended to connect the blocking capacitors at VCC and VS as close as possi-
ble to the power supply and GND pins.
Recommended value for capacitors at VS:
Electrolytic capacitor C > 22 µF in parallel with a ceramic capacitor C = 100 nF. The value for
electrolytic capacitor depends on external loads, conducted interferences and reverse conduct-
ing current IOut1,2,3 (see Section 4. ”Absolute Maximum Ratings” on page 7).
Recommended value for capacitors at VCC
:
Electrolytic capacitor C > 10 µF in parallel with a ceramic capacitor C = 100 nF.
To reduce thermal resistance it is recommended to place cooling areas on the PCB as close as
possible to the GND pins and to the die pad.
13
4912D–AUTO–06/07
12. Ordering Information
Extended Type Number
Package
Remarks
ATA6827-PIQW
QFN18, 4 mm × 4 mm
Taped and reeled, Pb-free
13. Package Information
Package: VQFN_4 x 4_18L
Exposed pad 2.7 x 3.175
Dimensions in mm
Bottom
2.5
Not indicated tolerances ±0.05
Z
12
7
0.5 nom.
18
Top
18
13
1
1
Pin 1 identification
6
6
4
0.2
2.7±0.15
0.9±0.1
Z 10:1
technical drawings
according to DIN
specifications
Drawing-No.: 6.543-5133.01-4
Issue: 1; 26.04.07
0.23±0.07
14. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
Revision No.
History
• Put datasheet in a new template
• Package drawing changed
• Block diagram changed
• Pinning drawing changed
4912D-auto-06/07
• Pin Description table changed
• Application circuit drawing changed
14
ATA6827
4912D–AUTO–06/07
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4912D–AUTO–06/07
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