ATA6663-TAQY [ATMEL]
LIN Transceiver; LIN收发器
| 型号： | ATA6663-TAQY |
| 厂家： | 
ATMEL |
| 描述： | LIN Transceiver |
| 文件： | 总20页 (文件大小：703K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Operating Range from 5V to 27V
• Baud Rate up to 20Kbaud
• Improved Slew Rate Control According to LIN Specification 2.0, 2.1 and SAEJ2602-2
• Fully Compatible with 3.3V and 5V Devices
• Atmel ATA6663: TXD Time-out Timer, Atmel ATA6664: No TXD Time-out Timer
• Normal and Sleep Mode
• Wake-up Capability via LIN Bus (90µs Dominant)
• External Wake-up via WAKE Pin (35µs Low Level)
• INH Output to Control an External Voltage Regulator or to Switch the Master Pull-up
• Very Low Standby Current During Sleep Mode (10µA)
• Wake-up Source Recognition
LIN Transceiver
• Bus Pin Short-circuit Protected versus GND and Battery
• LIN Input Current < 2µA if VBAT Is Disconnected
• Overtemperature Protection
Atmel ATA6663
Atmel ATA6664
• High EMC Level
• Interference and Damage Protection According to ISO/CD 7637
• Fulfills the OEM “Hardware Requirements for LIN in Automotive Applications Rev.1.1”
1. Description
The Atmel ATA6663 is a fully integrated LIN transceiver complying with the LIN
specification 2.0, 2.1 and SAEJ2602-2. The Atmel ATA6664 is an identical version,
the only difference is that the TXD-dominant Time-out function is disabled so the
device is able to send a static low signal to the LIN bus. It interfaces the LIN protocol
handler and the physical layer. The device is designed to handle the low-speed data
communication in vehicles, for example, in convenience electronics. Improved slope
control at the LIN bus ensures secure data communication at up to 20Kbaud with an
RC oscillator for protocol handling. Sleep Mode guarantees minimal current consump-
tion even in the case of a floating bus line or a short circuit on the LIN bus to GND.
The ATA6663/ATA6664 feature advanced EMI and ESD performance.
9146D–AUTO–09/10
Figure 1-1. Block Diagram
7
VS
Receiver
1
RXD
6
LIN
Filter
Short-circuit and over-
temperature protection
Wake-up bus timer
Slew rate control
TXD
time-out
timer
TXD
4
(only ATA6663)
VS
VS
Control unit
Sleep mode
Wake-up
timer
5
GND
WAKE
3
2
8
EN
INH
2. Pin Configuration
Figure 2-1. Pinning SO8
RXD
1
2
3
4
8
INH
VS
EN
WAKE
TXD
7
6
5
LIN
GND
Table 2-1.
Pin Description
Pin
1
Symbol
RXD
EN
Function
Receive data output (open drain)
2
Enables normal mode; when the input is open or low, the device is in sleep mode
High voltage input for local wake-up request. If not needed, connect directly to VS
Transmit data input; active low output (strong pull-down) after a local wake-up request
Ground, heat sink
3
WAKE
TXD
GND
LIN
4
5
6
LIN bus line input/output
7
VS
Battery supply
Battery-related inhibit output for controlling an external voltage regulator or to switch-off the LIN master
pull-up resistor; active high after a wake-up request
8
INH
2
Atmel ATA6663/ATA6664
9146D–AUTO–09/10
Atmel ATA6663/ATA6664
3. Functional Description
3.1
Physical Layer Compatibility
Since the LIN physical layer is independent from higher LIN layers (e.g., the LIN protocol
layer), all nodes with a LIN physical layer according to LIN2.x can be used along with LIN
physical layer nodes, which are according to older versions (i.e., LIN1.0, LIN1.1, LIN1.2,
LIN1.3), without any restrictions.
3.2
Supply Pin (VS)
Undervoltage detection is implemented to disable transmission if VS falls to a value below 5V
in order to avoid false bus messages. After switching on VS, the IC switches to fail-safe mode
and INHIBIT is switched on. The supply current in sleep mode is typically 10µA.
3.3
3.4
Ground Pin (GND)
The Atmel ATA6663/ATA6664 does not affect the LIN Bus in the case of a GND disconnec-
tion. It is able to handle a ground shift up to 11.5% of VS.
Bus Pin (LIN)
A low-side driver with internal current limitation and thermal shutdown, and an internal pull-up
resistor are implemented as specified by LIN2.x. The voltage range is from –27V to +40V. This
pin exhibits no reverse current from the LIN bus to VS, even in the case of a GND shift or VBatt
disconnection. The LIN receiver thresholds are compatible to the LIN protocol specifica-
tion.The fall time (from recessive to dominant) and the rise time (from dominant to recessive)
are slope controlled. The output has a self-adapting short-circuit limitation: During current limi-
tation, as the chip temperature increases, the current is reduced.
Note:
The internal pull-up resistor is only active in normal and fail-safe mode.
3.5
3.6
Input/Output Pin (TXD)
In Normal Mode the TXD pin is the microcontroller interface to control the state of the LIN out-
put. TXD must be at Low- level in order to have a low LIN Bus. If TXD is high, the LIN output
transistor is turned off and the Bus is in recessive state. The TXD pin is compatible to both a
3.3V or 5V supply. During fail-safe Mode, this pin is used as output and is signalling the wake-
up source (see Section 3.14 “Wake-up Source Recognition” on page 8). It is current limited to
< 8mA.
TXD Dominant Time-out Function (only Atmel ATA6663)
The TXD input has an internal pull-down resistor. An internal timer prevents the bus line from
being driven permanently in dominant state. If TXD is forced to low longer than tDOM > 40ms,
the pin LIN will be switched off (recessive mode). To reset this mode, TXD needs to be
switched to high (> 10µs) before switching LIN to dominant again.
Note:
The ATA6664 does not provide this functionality.
3
9146D–AUTO–09/10
3.7
3.8
Output Pin (RXD)
This pin forwards information on the state of the LIN bus to the microcontroller. LIN high
(recessive) is indicated by a high level at RXD, LIN low (dominant) is reported by a low voltage
at RXD. The output is an open drain, therefore, it is compatible to a 3.3V or 5V power supply.
The AC characteristics are defined by a pull-up resistor of 5kΩ to 5V and a load capacitor of
20pF. The output is short-current protected. In unpowered mode (VS = 0V), RXD is switched
off. For ESD protection a Zener diode with VZ = 6.1V is integrated.
Enable Input Pin (EN)
This pin controls the operation mode of the device. If EN = 1, the device is in normal mode,
with the transmission path from TXD to LIN and from LIN to RXD both active. At a falling edge
on EN, while TXD is already set to high, the device switches to sleep mode and transmission
is not possible. In sleep mode, the LIN bus pin is connected to VS with a weak pull-up current
source. The device can transmit only after being woken up (see Section 3.9, “Inhibit Output
Pin (INH)” ).
During sleep mode the device is still supplied from the battery voltage. The supply current is
typically 10µA. The pin EN provides a pull-down resistor in order to force the transceiver into
sleep mode in case the pin is disconnected.
3.9
Inhibit Output Pin (INH)
This pin is used to control an external voltage regulator or to switch on/off the LIN Master
pull-up resistor in case the device is used in a Master node. The inhibit pin provides an internal
switch towards pin VS which is protected by temperature monitoring. If the device is in normal
or fail-safe mode, the inhibit high-side switch is turned on. When the device is in sleep mode,
the inhibit switch is turned off, thus disabling the voltage regulator or other connected external
devices.
A wake-up event on the LIN bus or at pin WAKE will switch the INH pin to the VS level. After a
system power-up (VS rises from zero), the pin INH switches automatically to the VS level.
3.10 Wake-up Input Pin (WAKE)
This pin is a high-voltage input used to wake-up the device from sleep mode. It is usually
connected to an external switch in the application to generate a local wake-up. A pull-up cur-
rent source with typically –10µA is implemented. The voltage threshold for a wake-up signal is
3V below the VS voltage with an output current of typically –3µA.
If a local wake-up is not needed in the application, pin WAKE can directly be connected to pin
VS.
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Atmel ATA6663/ATA6664
9146D–AUTO–09/10
Atmel ATA6663/ATA6664
3.11 Operation Modes
1. Normal Mode
This is the normal transmitting and receiving mode. All features are available.
2. Sleep Mode
In this mode the transmission path is disabled and the device is in low-power mode.
Supply current from VBatt is typically 10µA. A wake-up signal from the LIN bus or via
pin WAKE will be detected and will switch the device to fail-safe mode. If EN then
switches to high, normal mode is activated. Input debounce timers at pin WAKE
(tWAKE), LIN (tBUS) and EN (tsleep,tnom) prevent unwanted wake-up events due to auto-
motive transients or EMI. In sleep mode the INH pin remains floating. The internal
termination between pin LIN and pin VS is disabled. Only a weak pull-up current (typ-
ical 10 µA) between pin LIN and pin VS is present. Sleep mode can be activated
independently from the actual level on pin LIN or WAKE.
3. Fail-safe Mode
At system power-up or after a wake-up event, the device automatically switches to
fail-safe mode. It switches the INH pin to a high state, to the VS level when VS
exceeds 5V. LIN communication is switched off. The microcontroller of the application
will then confirm normal mode by setting the EN pin to high.
Figure 3-1. Mode of Operation
Power-up
a: Power-up (VS > 3V)
b: VS < 5V
a
c: Bus wake-up event
d: Wake-up from wake switch
Fail-safe Mode
Communication: OFF
RXD: see table of Modes
b
INH: high (INH HS switch ON) if VS > 5V
b
EN = 1
c or d
& NOT b
Go to sleep command
EN = 0
Sleep Mode
INH: high impedance (INH HS switch OFF)
Normal Mode
INH: high (INH HS switch ON)
Communication: ON
Local wake-up event
EN = 1
Communication: OFF
Table 3-1.
Table of Operation Modes
Mode of Operation
Transceiver
INH
RXD
LIN
On, except
VS < 5V
High, except after
wake-up
Fail-safe
Off
Recessive
Normal
Sleep
On
Off
On
Off
LIN depending
High ohmic
TXD depending
Recessive
Wake-up events from sleep mode:
• LIN bus
• EN pin
• WAKE pin
• VS undervoltage
Figure 3-1 on page 5, Figure 3-2 on page 6 and Figure 3-5 on page 8 show the details of
wake-up operations.
5
9146D–AUTO–09/10
3.12 Remote Wake-up via Dominant Bus State
A voltage lower than the LIN pre-wake detection VLINL at pin LIN activates the internal LIN
receiver and starts the wake-up detection timer.
A falling edge at pin LIN, followed by a dominant bus level VBUSdom maintained for a certain
time period (tBUS) and a rising edge at pin LIN results in a remote wake-up request. The device
switches to fail-safe mode. Pin INH is activated (switches to VS) and the internal termination
resistor is switched on. The remote wake-up request is indicated by a low level at pin RXD to
interrupt the microcontroller (see Figure 3-2).
Figure 3-2. LIN Wake-up Waveform Diagram
Bus wake-up filtering time
(tBUS
)
LIN bus
High
Low
INH
Low or floating
High or floating
RXD
External
voltage
Off state
regulator
Normal
Mode
Regulator wake-up time delay
EN High
EN
Node in sleep state
Microcontroller start-up
delay time
In sleep mode the device has a very low current consumption, even during short-circuits or
floating conditions on the bus. A floating bus can arise if the Master pull-up resistor is missing,
e.g., in case it is switched off when the LIN Master is in sleep mode or if the power supply of
the Master node is switched off.
To minimize the current consumption IVS during voltage levels at the LIN-pin below the LIN
pre-wake threshold, the receiver is activated only for a specific time tmon. If tmon elapses while
the voltage at the bus is lower than pre-wake detection low (VLINL) and higher than the LIN
dominant level, the receiver is switched off again and the circuit reverts to sleep mode. The
current consumption is then the result of IVSsleep plus ILINwake. If a dominant state is reached on
the bus no wake-up will occur. Even if the voltage exceeds the pre-wake detection high
(VLINH), the IC will remain in sleep mode (see Figure 3-3 on page 7).
This means the LIN bus must be above the Pre-wake detection threshold VLINH for a few
microseconds before a new LIN wake-up is possible.
6
Atmel ATA6663/ATA6664
9146D–AUTO–09/10
Atmel ATA6663/ATA6664
Figure 3-3. Floating LIN Bus During Sleep Mode
LIN Pre-wake
V
V
LINL
LIN BUS
LIN dominant state
BUSdom
t
mon
I
VSsleep
I
VSfail
+ I
LINwake
I
VS
I
I
VSsleep
VSsleep
Mode of
operation
Sleep Mode
Wake-up Detection Phase
off (disabled)
Sleep Mode
Int. Pull-up
Resistor
RLIN
If the Atmel® ATA6663/ATA6664 is in sleep mode and the voltage level at the LIN is in domi-
nant state (VLIN < VBUSdom) for a time period exceeding tmon (during a short circuit at LIN, for
example), the IC switches back to sleep mode. The VS current consumption then consists of
IVSsleep plus ILINWAKE. After a positive edge at pin LIN the IC switches directly to fail-safe mode
(see Figure 3-4).
Figure 3-4. Short Circuit to GND on the LIN Bus During Sleep Mode
LIN Pre-wake
V
LINL
LIN BUS
LIN dominant state
V
BUSdom
t
mon
t
mon
I
I
VSfail
VSsleep
I
+ I
VS
LINwake
I
VSsleep
Mode of
operation
Sleep Mode
Wake-up Detection Phase Sleep Mode
off (disabled)
Fail-Safe Mode
on (enabled)
Int. Pull-up
Resistor
RLIN
7
9146D–AUTO–09/10
3.13 Local Wake-up via Pin WAKE
A falling edge at pin WAKE, followed by a low level maintained for a certain time period
(tWAKE), results in a local wake-up request. According to ISO7637, the wake-up time ensures
that no transient creates a wake-up. The device then switches to fail-safe mode. Pin INH is
activated (switches to VS) and the internal termination resistor is switched on. The local
wake-up request is indicated both by a low level at pin RXD to interrupt the microcontroller and
by a strong pull-down at pin TXD (see Figure 3-5). The voltage threshold for a wake-up signal
is 3V below the VS voltage with an output current of typically –3µA. Even in case of a continu-
ous low at pin WAKE it is possible to switch the IC into sleep mode via a low level at pin EN.
The IC will remain in sleep mode for an unlimited time. To generate a new wake-up at pin
WAKE, a high signal > 6 µs is required. A negative edge then starts the wake-up filtering time
again.
Figure 3-5. Wake-up from Wake-up Switch
Wake pin
State change
High
Low
INH
Low or floating
High or floating
RXD
TXD
High
Weak
pull-down
TXD weak pull-down resistor
TXD strong pull-down
On state
Wake filtering time
tWAKE
Voltage
regulator
Off state
Node in
operation
Regulator wake-up time delay
EN High
EN
Node in sleep state
Microcontroller start-up
delay time
3.14 Wake-up Source Recognition
The device can distinguish between a local wake-up request (pin WAKE) and a remote
wake-up request (LIN bus). The wake-up source can be read at pin TXD in fail-safe mode. If
an external pull-up resistor (typically 5kΩ) has been added on pin TXD to the power supply of
the microcontroller, a high level indicates a remote wake-up request (weak pull-down at pin
TXD), a low level indicates a local wake-up request (strong pull-down at pin TXD).
The wake-up request flag (indicated at pin RXD) as well as the wake-up source flag (indicated
at pin TXD) are reset immediately if the microcontroller sets pin EN to high (see Figure 3-2 on
page 6 and Figure 3-5 on page 8).
8
Atmel ATA6663/ATA6664
9146D–AUTO–09/10
Atmel ATA6663/ATA6664
3.15 Fail-safe Features
• During a short-circuit at LIN to VBAT, the output limits the output current to IBUS_LIM. Due
to the power dissipation, the chip temperature exceeds Toff, and the LIN output is switched
off. The chip cools down, and after a hysteresis of Thys, it switches the output on again.
• During a short-circuit from LIN to GND the IC can be switched to sleep mode, and even in
this case the current consumption is lower than 45µA. When the short-circuit has elapsed,
the IC starts with a remote wake-up.
• If the Atmel® ATA6663/ATA6664 is in sleep mode and a floating condition occurs on the
bus, the IC switches back to sleep mode automatically. The current consumption is lower
than 45µA in this case.
• The reverse current is < 2µA at pin LIN during loss of VBAT. This is the best behavior for bus
systems where some slave nodes are supplied from battery or ignition.
• Pin EN provides a pull-down resistor to force the transceiver into sleep mode if EN is
disconnected
• Pin RXD is set floating if VBAT is disconnected
• Pin TXD provides a pull-down resistor to provide a static low if TXD is disconnected
• The INH output transistor is protected by temperature monitoring
9
9146D–AUTO–09/10
4. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
Min.
Typ.
Max.
Unit
VS
–0.3
+40
V
- Continuous supply voltage
Wake DC and transient voltage (with 2.7kΩ serial resistor)
- Transient voltage according to ISO7637 (coupling 1nF)
–3
–150
+40
+100
V
V
Logic pins (RXD, TXD, EN)
–0.3
+5.5
V
LIN
- DC voltage
–27
–150
+40
+100
V
V
- Transient voltage according to ISO7637 (coupling 1nF)
INH
- DC voltage
–0.3
VS + 0.3
V
ESD according to IBEE LIN EMC
Test specification 1.0 according to IEC 61000-4-2
- Pin VS, LIN to GND
±8
±6
KV
KV
- Pin WAKE (2.7kΩ serial resistor)
ESD HBM according to STM5.1
with 1.5kΩ / 100pF
- Pin VS, LIN, WAKE, INH to GND
±6
±3
KV
KV
HBM ESD
ANSI/ESD-STM5.1
JESD22-A114
AEC-Q100 (002)
CDM ESD STM 5.3.1
±750
±200
–40
V
V
Machine Model ESD AEC-Q100-Rev.F (003)
Junction temperature
Tj
+150
+150
°C
°C
Storage temperature
Tstg
–55
5. Thermal Characteristics
Parameters
Symbol
Min.
Typ.
Max.
Unit
Thermal resistance junction ambient
RthJA
145
K/W
Special heat sink at GND (pin 5) on PCB (fused lead
frame to pin 5)
RthJA
80
K/W
Thermal shutdown
Toff
150
5
165
10
180
20
°C
°C
Thermal shutdown hysteresis
Thys
10
Atmel ATA6663/ATA6664
9146D–AUTO–09/10
Atmel ATA6663/ATA6664
6. Electrical Characteristics
5V < VS < 27V, Tj = –40°C to +150°C
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit Type*
1
VS Pin
1.1
DC voltage range nominal
7
7
VS
5
13.5
10
27
20
V
A
A
Sleep mode
VLIN > VS – 0.5V
VS < 14V
IVSsleep
µA
1.2
Supply current in sleep mode
Sleep mode,
bus shorted to GND
VLIN = 0V
7
IVSsleep_sc
23
45
µA
A
VS < 14V
Bus recessive
VS < 14V
1.3
1.4
1.5
7
7
7
IVSrec
IVSdom
IVSfail
0.9
1.2
1.3
2
mA
mA
mA
A
A
A
Supply current in normal mode
Supply current in fail-safe mode
Bus dominant
VS < 14V
Total bus load > 500Ω
Bus recessive
VS < 14V
0.5
1.1
1.6
1.7
VS undervoltage threshold on
VS undervoltage threshold off
7
7
VSth
VSth
4
4.95
5
V
V
A
A
4.05
VS undervoltage threshold
hysteresis
1.8
2
7
VSth_hys
50
500
mV
A
RXD Output Pin (Open Drain)
Low-level output sink current
RXD saturation voltage
Normal mode
VLIN = 0V, VRXD = 0.4V
2.1
2.2
2.3
1
1
1
1
IRXDL
VsatRXD
IRXDH
1.3
2.5
8
mA
V
A
A
A
A
5-kΩ pull-up resistor to 5V
0.4
+3
8.6
Normal mode
VLIN = VBAT, VRXD = 5V
High-level leakage current
–3
µA
V
2.4
3
ESD Zener diode
IRXD = 100µA
VZRXD
5.8
TXD Input Pin
3.1
3.2
3.3
3.4
Low-level voltage input
High-level voltage input
Pull-down resistor
4
4
4
4
VTXDL
VTXDH
RTXD
–0.3
2
+0.8
7
V
V
A
A
A
A
VTXD = 5V
VTXD = 0V
125
–3
250
2.5
600
+3
kΩ
µA
Low-level leakage current
ITXD_leak
Fail-safe mode, local wake-up
VTXD = 0.4V
3.5
Low-level output sink current
4
ITXD
1.3
8
mA
A
VLIN = VBAT
4
EN Input Pin
4.1
4.2
4.3
4.4
Low-level voltage input
High-level voltage input
Pull-down resistor
2
2
2
2
VENL
VENH
REN
IEN
–0.3
2
+0.8
7
V
V
A
A
A
A
VEN = 5V
VEN = 0V
125
–3
250
600
+3
kΩ
µA
Low-level input current
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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9146D–AUTO–09/10
6. Electrical Characteristics (Continued)
5V < VS < 27V, Tj = –40°C to +150°C
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit Type*
5
INH Output Pin
Normal or fail-safe mode
VS –
0.75
5.1
High-level voltage
8
8
8
VINHH
RINH
IINHL
VS
50
+3
V
Ω
A
A
A
I
INH = –15mA
Switch-on resistance between
VS and INH
5.2
Normal or fail-safe mode
30
Sleep mode
VINH = 0V/27V, VS = 27V
5.3
6
Leakage current
WAKE Pin
–3
µA
VS –
1V
VS +
0.3V
6.1
High-level input voltage
3
3
VWAKEH
VWAKEL
V
V
A
A
VS –
3.3V
6.2
Low-level input voltage
I
WAKE = typically –3µA
–1V
6.3
6.4
7
Wake pull-up current
High-level leakage current
LIN Bus Driver
VS < 27V
3
3
IWAKE
IWAKE
–30
–5
–10
µA
µA
A
A
VS = 27V, VWAKE = 27V
+5
0.9 ×
VS
7.1
7.2
7.3
7.4
Driver recessive output voltage RLOAD = 500Ω / 1kΩ
6
6
6
6
VBUSrec
V_LoSUP
VS
1.2
2
V
V
V
V
A
A
A
A
Driver dominant voltage
VVS = 7V, Rload = 500Ω
VBUSdom_DRV_LoSUP
Driver dominant voltage
VVS = 18V, Rload = 500Ω
VBUSdom_DRV_HiSUP
V_HiSUP
Driver dominant voltage
VVS = 7V, Rload = 1000Ω
VBUSdom_DRV_LoSUP
V_LoSUP_1k
0.6
Driver dominant voltage
VVS = 18V, Rload = 1000Ω
VBUSdom_DRV_HiSUP
7.5
7.6
7.7
6
6
6
V_HiSUP_1k_
RLIN
0.8
20
V
kΩ
V
A
A
D
Pull-up resistor to VS
The serial diode is mandatory
30
47
In pull-up path with Rslave
ISerDiode = 10mA
Voltage drop at the serial diodes
LIN current limitation
VSerDiode
0.4
1.0
7.8
7.9
6
6
IBUS_LIM
40
–1
120
200
mA
mA
A
A
VBUS = VBAT_max
Input leakage current at the
receiver, including pull-up
resistor as specified
Input leakage current
Driver off
VBUS = 0V, VS = 12V
IBUS_PAS_dom
Driver off
8V < VBAT < 18V
8V < VBUS < 18V
7.10 Leakage current LIN recessive
6
6
IBUS_PAS_rec
10
20
µA
µA
A
A
VBUS ≥ VBAT
Leakage current at ground loss;
control unit disconnected from
GNDDevice = VS
7.11 ground; loss of local ground must VBAT =12V
not affect communication in the 0V < VBUS < 18V
residual network
IBUS_NO_Gnd
–10
+0.5
+10
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
12
Atmel ATA6663/ATA6664
9146D–AUTO–09/10
Atmel ATA6663/ATA6664
6. Electrical Characteristics (Continued)
5V < VS < 27V, Tj = –40°C to +150°C
No. Parameters
Leakage current at loss of
battery; node has to substain the VBAT disconnected
Test Conditions
Pin
6
Symbol
IBUS_NO_Bat
CLIN
Min.
Typ.
Max.
2
Unit Type*
7.12 current that can flow under this
condition; bus must remain
V
SUP_Device = GND
0.1
µA
pF
A
D
0V < VBUS < 18V
operational under this condition
7.13 Capacitance on pin LIN to GND
6
20
8
LIN Bus Receiver
VBUS_CNT
(Vth_dom + Vth_rec) / 2
=
0.475 × 0.5 × 0.525
8.1
Center of receiver threshold
6
6
6
6
6
6
6
VBUS_CNT
VBUSdom
VBUSrec
VBUShys
VLINH
V
V
A
A
A
A
A
A
A
VS
VS
× VS
0.4 ×
VS
8.2
8.3
8.4
8.5
8.6
Receiver dominant state
Receiver recessive state
Receiver input hysteresis
VEN = 5V
–27
0.6 ×
VS
VEN = 5V
40
V
0.028 × 0.1 × 0.175
VHYS = Vth_rec – Vth_dom
V
VS
VS
× VS
Pre-wake detection LIN
High-level input voltage
VS –
2V
VS +
0.3V
V
Pre-wake detection LIN
Low-level input voltage
VS –
3.3V
Switches the LIN receiver on
VLINL
–27V
–30
V
VS < 27V
VLIN = 0V
8.7
9
LIN Pre-wake pull-up current
ILINWAKE
–10
µA
Internal Timers
Dominant time for wake-up via
LIN bus
9.1
V
LIN = 0V
6
3
tBUS
30
7
90
35
150
50
µs
µs
A
A
Time of low pulse for wake-up
via pin WAKE
9.2
9.3
VWAKE = 0V
tWAKE
Time delay for mode change
from fail-safe mode to normal
mode via pin EN
VEN = 5V
VEN = 0V
2
2
tnorm
2
7
15
24
µs
µs
A
A
Time delay for mode change
from normal mode into sleep
mode via pin EN
9.4
tsleep
7
15
60
Atmel ATA6663:
TXD dominant time out time
9.5
9.6
9.7
V
TXD = 0V
VS = 5V
4
7, 8
6
tdom
tVS
40
85
200
15
ms
µs
A
A
A
Power-up delay between VS = 5V
until INH switches to high
V
Monitoring time for wake-up via
LIN bus
tmon
6
10
ms
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
13
9146D–AUTO–09/10
6. Electrical Characteristics (Continued)
5V < VS < 27V, Tj = –40°C to +150°C
No. Parameters
LIN Bus Driver AC Parameter with Different Bus Loads
Load 1 (small): 1nF, 1kΩ ; Load 2 (large): 10nF, 500Ω ; RRXD = 5kΩ ; CRXD = 20pF;
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit Type*
10
Load 3 (medium): 6.8nF, 660Ω characterized on samples; 10.1 and 10.2 specifies the timing parameters for proper
operation at 20Kbit/s, 10.3 and 10.4 at 10.4Kbit/s.
THRec(max) = 0.744 × VS
THDom(max) = 0.581 × VS
10.1 Duty cycle 1
10.2 Duty cycle 2
10.3 Duty cycle 3
10.4 Duty cycle 4
VS = 7.0V to 18V
tBit = 50µs
D1 = tbus_rec(min) / (2 × tBit)
6
6
6
6
D1
D2
D3
D4
0.396
A
A
A
A
THRec(min) = 0.422 × VS
THDom(min) = 0.284 × VS
VS = 7.0V to 18V
0.581
t
Bit = 50µs
D2 = tbus_rec(max) / (2 × tBit)
THRec(max) = 0.778 × VS
THDom(max) = 0.616 × VS
VS = 7.0V to 18V
tBit = 96µs
D3 = tbus_rec(min) / (2 × tBit)
0.417
THRec(min) = 0.389 × VS
THDom(min) = 0.251 × VS
VS = 7.0V to 18V
0.590
tBit = 96µs
D4 = tbus_rec(max) / (2 × tBit)
Receiver Electrical AC Parameters of the LIN Physical Layer
LIN receiver, RXD load conditions: CRXD = 20pF, Rpull-up = 5kΩ
11
Propagation delay of receiver
(see Figure 6-1 on page 15)
trec_pd = max(trx_pdr , trx_pdf
VS = 7.0V to 18V
)
11.1
1
1
trx_pd
6
µs
µs
A
A
Symmetry of receiver
11.2 propagation delay rising edge
minus falling edge
trx_sym = trx_pdr – trx_pdf
VS = 7.0V to 18V
trx_sym
–2
+2
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
14
Atmel ATA6663/ATA6664
9146D–AUTO–09/10
Atmel ATA6663/ATA6664
Figure 6-1. Definition of Bus Timing Parameter
tBit
tBit
tBit
TXD
(Input to transmitting node)
tBus_dom(max)
tBus_rec(min)
Thresholds of
THRec(max)
receiving node 1
THDom(max)
VS
(Transceiver supply
of transmitting node)
LIN Bus Signal
Thresholds of
THRec(min)
THDom(min)
receiving node 2
tBus_dom(min)
tBus_rec(max)
RXD
(Output of receiving node 1)
trx_pdr(1)
trx_pdf(1)
RXD
(Output of receiving node 2)
trx_pdr(2)
trx_pdf(2)
15
9146D–AUTO–09/10
Figure 6-2. Application Circuit
Master node
pull-up
VBAT
100 nF
22 µF
12V
1k
5V
7
Atmel ATA6663/ATA6664
VDD
VS
Receiver
1
RXD
6
Filter
Microcontroller
LIN
Wake-up bus timer
Slew rate control
Short-circuit and
overtemperature
protection
4
TXD
Time-out
timer
TXD
220 pF
(only ATA6663)
GND IO
V
S
V
S
Control unit
Sleep mode
10 kΩ
5
2.7 kΩ
3
Wake-up
GND
timer
External
switch
WAKE
2
8
EN
INH
16
Atmel ATA6663/ATA6664
9146D–AUTO–09/10
Atmel ATA6663/ATA6664
7. Ordering Information
Extended Type Number
Package
DFN8
SO8
Remarks
ATA6663-FAQW
LIN transceiver, Pb-free, 8k, taped and reeled
LIN transceiver, Pb-free, 4k, taped and reeled
LIN transceiver, Pb-free, 4k, taped and reeled
ATA6663-TAQY
ATA6664-TAQY
SO8
8. Package Information
Figure 8-1. SO8
Package: SO 8
Dimensions in mm
5±0.2
4.9±0.1
3.7±0.1
3.8±0.1
6±0.2
0.4
1.27
3.81
8
5
technical drawings
according to DIN
specifications
1
4
Drawing-No.: 6.541-5031.01-4
Issue: 1; 15.08.06
17
9146D–AUTO–09/10
Figure 8-2. DFN8
Top View
D
8
PIN 1 ID
technical drawings
according to DIN
specifications
1
Dimensions in mm
Side View
Partially Plated Surface
Bottom View
1
4
COMMON DIMENSIONS
(Unit of Measure = mm)
Symbol MIN
NOM
0.9
MAX NOTE
8
5
A
A1
A3
D
0.8
0.0
1
Z
e
0.02
0.2
0.05
0.25
3.1
0.15
2.9
D2
3
D2
E
2.35
2.9
2.4
2.45
3.1
3
E2
L
1.55
0.35
0.25
1.6
1.65
0.45
0.35
Z 10:1
0.4
b
0.28
0.65 BSC
e
b
03/03/10
DRAWING NO.
TITLE
REV.
Package Drawing Contact:
packagedrawings@atmel.com
Package: VQFN_3x3_8L
Exposed pad 2.4x1.6
6.543-5165.02-4
1
18
Atmel ATA6663/ATA6664
9146D–AUTO–09/10
Atmel ATA6663/ATA6664
9. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
Revision No.
History
• Section 7 “Ordering Information” on page 17 changed
9146D-AUTO-09/10
• Section 8 “Package Information” on pages 17 to 18 changed
• Section 6 “Electrical Characteristics” numbers 9.4 and 9.5 on page 13
changed
9146C-AUTO-07/10
9146B-AUTO-05/10
• Features changed
• Headings 3.6 and 3.10: text changed
• Abs.Max.Ratings table: row “ESD HBM acc. to STM5.1” changed
19
9146D–AUTO–09/10
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